JP2003177721A - Synchronizing signal monitoring device for liquid crystal display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a synchronizing signal monitoring device for a liquid crystal display, capable of protecting the operating function of the liquid crystal display when there is an abnormality in a synchronizing signal to be transmitted from a host 1, and reducing the power consumption and also extending the service life of a back light. <P>SOLUTION: When a synchronizing signal (b) is not detected by monitoring the synchronizing signal (b) from the host 1 with a synchronizing signal monitoring circuit 5, the supplying of power source to a liquid crystal display 8 and a back light 9 is interrupted by allowing the synchronizing signal monitoring circuit 5 to transmit a stop signal (h) to a buffer circuit 6 and a power circuit 7. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing signal monitoring device for a liquid crystal display, and more particularly to a synchronizing signal monitoring device which constantly monitors a synchronizing signal which is an input signal to the liquid crystal display and when the synchronizing signal is not detected. The present invention relates to a synchronizing signal monitoring device for a liquid crystal display, which protects the operating function of the liquid crystal display by cutting off the power supply to the liquid crystal display, suppresses power consumption, and prolongs the useful life of the backlight.

[0002]

2. Description of the Related Art Conventionally, a liquid crystal display device is controlled by a host, and a signal is transmitted from the host at any time to display a screen. However, due to a change in the host hardware, a change in software, a version upgrade, etc. In some cases, the liquid crystal display device malfunctions due to the difference in power supply and signal sequence timing.

In the image display device described in Japanese Patent Application Laid-Open No. 11-249637, the control circuit controlled by the MPU is destroyed when the program of the microprocessor unit (MPU) runs out of control due to the function of the watchdog timer (WDT). There is disclosed a technique of automatically returning the MPU from the runaway state to the normal operation state without the need.

In the above image display device, when the MPU program runs out of control, the watchdog timer operates to generate a non-maskable interrupt (NMI).
Moving to the processing, the power supply is controlled so as to be in the off mode that operates in the low power consumption state, the low power consumption mode transition processing is executed, and then the video amplification control signal sent from the MPU,
A system initialization process is executed to initialize the ports that control the image amplification means, the horizontal deflection means, and the vertical deflection means, according to the horizontal deflection control signal and the vertical deflection control signal, and then the on mode is set to operate in the normal power state. By controlling the power supply so that the normal state transition processing is performed,
The image display device is automatically returned to the normal state without destroying the image amplification means, the horizontal deflection means, and the vertical deflection means.

However, in the NMI processing by the operation of the WDT, the low power consumption mode shift processing, the system initialization processing, and the normal state shift processing are sequentially executed so that the image display device is normally operated when the MPU program runs out of control. Although it is possible to automatically return to the state, there is a drawback in that it is not possible to prevent malfunction of the image display device due to occurrence of a slight timing shift of the power supply control signal and the synchronization signal transmitted from the host.

[0006]

As described above,
Conventional liquid crystal display device, and JP-A-11-24
In the image display device disclosed in Japanese Patent Publication No. 9637, malfunction of a liquid crystal display is caused by the fact that the timing of the sequence of the power supply control signal and the synchronization signal is different due to the change of the hardware and software of the host and the version upgrade. However, there is a problem that it is impossible to prevent the occurrence of.

An object of the present invention is to constantly monitor the sync signal from the host, and when the sync signal is not detected, shut off the power supply to the liquid crystal display and the backlight to protect the operating function of the liquid crystal display. With
An object of the present invention is to provide a synchronizing signal monitoring device for a liquid crystal display that suppresses power consumption and extends the useful life of the backlight.

[0008]

SUMMARY OF THE INVENTION A sync signal monitoring apparatus for a liquid crystal display according to the present invention includes an input section having a host for outputting a sync signal serving as a display reference of the liquid crystal display and an analog RBG signal, and an input from the host. And a signal creation unit that adjusts the synchronization signal and converts an analog RGB signal into a digital RGB signal, and an output unit that includes a liquid crystal display and a backlight to which an output from the signal creation unit is input, and a signal creation unit. Is an A / D conversion circuit that converts an analog RGB signal into a digital RGB signal, a synchronization signal adjustment circuit that adjusts the synchronization signal so as to match the display start position of the liquid crystal display, and a first output from the synchronization signal adjustment circuit. A clock generation circuit that generates the clock necessary for the LCD display based on the second synchronization signal, and the second synchronization signal and the clock. And a digital RGB signal are input, a power supply circuit that supplies power to the liquid crystal display, and a synchronization signal monitoring circuit that constantly monitors the synchronization signal input from the host. A horizontal signal WDT circuit for monitoring the horizontal signal of the synchronizing signal, a first temporary constant setting circuit for setting the monitoring time of the horizontal signal, a vertical signal WDT circuit for monitoring the vertical signal of the synchronizing signal, and a vertical signal monitoring time And a second time constant setting circuit for setting, and a logical product circuit to which signals of the horizontal signal WDT circuit and the vertical signal WDT circuit are input.

The synchronizing signal monitoring circuit has means for detecting that an abnormality has occurred in the host when the level of the synchronizing signal does not change after the set value of the monitoring time has elapsed since the synchronizing signal was input. And

When an abnormality is detected, the synchronization signal monitoring circuit sends a stop signal to the buffer circuit and the power supply circuit to supply the input signal to the liquid crystal display, the power supply from the power supply circuit and the power supply to the backlight. It is characterized by having a means for shutting off.

The AND circuit is characterized by having means for transmitting the stop signal to the buffer circuit and the power supply circuit when the stop signal is inputted from at least one of the horizontal signal WDT circuit and the vertical signal WDT circuit. .

The first temporary constant setting circuit and the second time constant setting circuit are characterized by having the same circuit.

The first temporary constant setting circuit and the second time constant setting circuit each include a resistor and a capacitor.

The resistor and the capacitor are characterized by having a variable resistor and a variable capacitor.

The horizontal signal WDT circuit and the vertical signal WDT circuit each have means for charging at the time set by the first temporary constant setting circuit and the second time constant setting circuit and discharging at the rising edge of the synchronizing signal. Is characterized by.

The synchronization signal monitoring circuit is characterized by having means that can be easily attached to and detached from the signal generating section.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an embodiment of a synchronizing signal monitoring apparatus for a liquid crystal display according to the present invention will be described with reference to the drawings.

FIG. 1 is a schematic block diagram showing a synchronizing signal monitoring device 50 for a liquid crystal display according to the present invention, and FIG.
It is a schematic block diagram which shows the synchronizing signal monitoring circuit 5 in FIG.

Referring to FIG. 1, a sync signal monitoring device 50 for a liquid crystal display includes a sync signal b serving as a display reference of the liquid crystal display 8 and analog RGB (Red / Gre).
an input unit 20 having a host 1 that outputs an en / Blue) signal a; a signal creation unit 30 that adjusts the synchronization signal b input from the host 1 and converts the analog RGB signal a into a digital RGB signal c; It is composed of a liquid crystal display 8 to which the output from the signal creating unit 30 is input and an output unit 40 having a backlight 9, and the signal creating unit 30 converts the analog RGB signal a into a digital RGB signal c A / D. The conversion circuit 4 and the synchronization signal b are sent to the liquid crystal display 8
Signal adjusting circuit 2 that adjusts so as to match the display start position of 1., and a clock creating circuit that creates a clock necessary for displaying on the liquid crystal display 8 based on the second synchronizing signal d output from the synchronizing signal adjusting circuit 2. 3, the buffer circuit 6 to which the second synchronizing signal d, the clock e and the digital RGB signal c are input, the power source circuit 7 for supplying power to the liquid crystal display 8, and the synchronizing signal b to be input from the host 1.
And a synchronization signal monitoring circuit 5 for constantly monitoring

Referring to FIG. 2, the synchronization signal monitoring circuit 5
Is a horizontal signal WD for monitoring the horizontal signal b1 of the synchronization signal b.
T (watchdog timer) circuit 10 and horizontal signal b1
And a vertical signal WDT circuit 1 for monitoring the vertical signal b2 of the synchronizing signal b.
2, the second time constant setting circuit 13 for setting the monitoring time of the vertical signal b2, the horizontal signal WDT circuit 10, and the vertical signal WD
The AND circuit 14 to which the signal from the T circuit 12 is input.

The first temporary constant setting circuit 11 is composed of a resistor R and a capacitor C as shown in the schematic circuit configuration in FIG. 5, and the second time constant setting circuit 13 is not shown in the figure but is a first temporary constant setting circuit. It has the same circuit configuration as 11.

Next, the operation of the liquid crystal display sync signal monitoring apparatus 50 configured as described above will be described with reference to the drawings.

FIG. 3 is a time chart of the sync signal b, the digital RGB signal c, the second sync signal d, and the clock e, and FIG. 4 is a time chart inside the sync signal monitoring circuit 5.

Referring to FIGS. 1 to 3, first, the host 1
Outputs a sync signal b and an analog RGB signal a from
The analog RGB signal a is input to the A / D conversion circuit 4, and the synchronization signal b is composed of two signals, a horizontal signal b1 and a vertical signal b2. The synchronization signal adjustment circuit 2, the clock generation circuit 3, and the synchronization signal monitoring circuit Input to 5.

The clock creating circuit 3 creates a clock e having a frequency necessary for displaying on the liquid crystal display 8 with the sync signal b from the host 1 as a reference, and the sync signal adjusting circuit 2 creates a sync signal output from the host 1. The second synchronization signal d adjusted for display on the liquid crystal display 8 is generated from b. The adjusted second synchronization signal d is generated based on the clock e and is always output from the host 1. A signal is output at a timing synchronized with b, and the A / D conversion circuit 4 samples the analog RGB signal a using the clock e, converts it into a digital RGB signal c, and outputs R
Each of ed, Green, and Blue is decomposed into n bits (where n is an arbitrary number capable of gradation display on the liquid crystal display 8).

Adjusted second sync signal d, clock e,
The digital RGB signal c is input to the buffer circuit 6, but is input to the buffer circuit 6 as a signal synchronized with the clock e.

The sync signal monitoring circuit 5 constantly monitors the sync signal b output from the host 1 and detects the rising edge of the sync signal b to determine whether it is in the normal state. The sync signal b shown in FIG. The case of monitoring the horizontal signal b1 of will be described.

Referring to FIGS. 2 and 4, the horizontal signal WDT
In the circuit 10, the internal signal f is repeatedly charged and discharged,
The discharge is performed at the rising edge of the horizontal signal b1, and the charging is performed according to the time set by the first temporary constant setting circuit 11.

The charging time set by the first temporary constant setting circuit 11 is set by the constants of the capacitor C and the resistor R (the monitoring time of the horizontal signal b1 is set to a value of one cycle or more of the horizontal signal b1). Exist).

When the internal signal f of the horizontal signal WDT circuit 10 reaches a certain level (abnormality detection level k in FIG. 4), it means that the change of the horizontal signal b1 has stopped (the rising of the horizontal signal b1 The level of the internal signal f of the WDT circuit 10 becomes high because it is not detected and is not discharged.) Therefore, the horizontal signal WDT circuit 10 outputs the horizontal signal b1.
When it is determined that an abnormality has occurred, the stop signal h is output to the AND circuit 14 as the output signal g.

Note that the case of monitoring the vertical signal b2 of the synchronizing signal b is the same as the case of monitoring the horizontal signal b1 of the synchronizing signal b described above, and a description thereof will be omitted.

The AND circuit 14 receives the stop signal h from at least one of the horizontal signal WDT circuit 10 for monitoring the horizontal signal b1 and the vertical signal WDT circuit 12 for monitoring the vertical signal b2.
Is input, the stop signal h is sent to the buffer circuit 6 and the power supply circuit 7, and the input signal from the buffer circuit 6 to the liquid crystal display 8, the power supply from the power supply circuit 7 and the power supply to the backlight 9 are supplied. Cut off.

As described above, the horizontal signal b1 and the vertical signal b2 of the synchronizing signal b transmitted from the host 1 are constantly monitored by the horizontal signal WDT circuit 10 and the vertical signal WDT circuit 12, respectively, and when an abnormality occurs. , Stop signal h and AND circuit 1
4 and the AND circuit 14 outputs the horizontal signal WDT circuit 1
When the stop signal h is input from at least one of 0 and the vertical signal WDT circuit 12, the stop signal h is sent to the buffer circuit 6 and the power supply circuit 7, and the power supply to the liquid crystal display 8 and the backlight 9 is cut off. As a result, it is possible to protect the operation function of the liquid crystal display 8, suppress power consumption, and extend the service life of the backlight 9.

Further, there is an effect that the hardware configuration required for the synchronization signal monitoring circuit 5 is small and simple.

In the embodiment of the liquid crystal display synchronization signal monitoring apparatus 50 described above, the monitoring time of the synchronization signal b is controlled by the resistors R and the capacitors C of the first temporary constant setting circuit 11 and the second time constant setting circuit 13. Although the charging / discharging time is set as, the monitoring time of the synchronization signal b can be set to an arbitrary value by using the resistor R as a volume variable resistor and the capacitor C as a variable capacitor.

Further, the synchronization signal monitoring circuit 5 is connected to the connector,
Various structures of the liquid crystal display 8 having different specifications can be supported by adopting a structure such that a socket or the like can be easily attached to and detached from the signal generating unit 30.

[0037]

As described above, the sync signal monitoring apparatus for a liquid crystal display according to the present invention constantly monitors the sync signal from the host by the sync signal monitoring circuit. By shutting off the power supply to the light, it is possible to protect the operating function of the liquid crystal display, suppress power consumption, and extend the useful life of the backlight.

There is an effect that the hardware configuration required for the synchronizing signal monitoring circuit is small and simple.

Further, by making the resistance and the capacitor of the time constant setting circuit respectively variable resistors and variable capacitors, there is an effect that the monitoring time of the synchronizing signal can be set to an arbitrary value.

Furthermore, by providing the synchronizing signal monitoring circuit with a structure that can be easily attached to and detached from the signal generating section, there is an effect that it can be applied to various types of liquid crystal displays having different specifications.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a sync signal monitoring device for a liquid crystal display according to the present invention.

FIG. 2 is a schematic block diagram showing a synchronization signal monitoring circuit in FIG.

FIG. 3 is a time chart of a synchronization signal.

FIG. 4 is a time chart inside a synchronization signal monitoring circuit.

FIG. 5 is a diagram showing a schematic circuit configuration of a first temporary constant setting circuit.

[Explanation of symbols]

1 host 2 Sync signal adjustment circuit 3 clock creation circuit 4 A / D conversion circuit 5 Sync signal monitoring circuit 6 buffer circuit 7 Power circuit 8 LCD display 9 backlight 10 Horizontal signal WDT circuit 11 Temporary constant setting circuit 12 Vertical signal WDT circuit 13 Second time constant setting circuit 14 AND circuit 20 Input section 30 signal generator 40 Output section 50 Liquid crystal display synchronization signal monitoring device a Analog RGB signal b Sync signal b1 horizontal signal b2 vertical signal c Digital RGB signal d Second synchronization signal e clock f Internal signal Output signal h Stop signal k Abnormality detection level C capacitor R resistance

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 670 G09G 3/20 670F 3/34 3/34 JF term (reference) 2H093 NA16 NC01 NC15 NC16 NC23 NC24 NC41 NC56 ND39 ND47 5C006 AA01 AA22 AF51 AF53 AF65 AF68 AF69 AF81 BB11 BF16 BF37 BF42 EA01 FA18 FA33 FA47 5C080 AA10 BB05 CC03 DD14 DD18 DD19 DD26 DD29 FF03 JJ02 JJ03 JJ04

Claims (9)

[Claims] 1. An input unit having a host for outputting a sync signal serving as a display reference of a liquid crystal display and an analog RBG signal, and adjusting the sync signal input from the host to convert the analog RGB signal into a digital RGB signal. A signal producing section for converting into an analog R signal, and an output section having the liquid crystal display and a backlight to which the output from the signal producing section is inputted.
An A / D conversion circuit that converts a GB signal into the digital RGB signal, a synchronization signal adjustment circuit that adjusts the synchronization signal so as to match the display start position of the liquid crystal display, and an output from the synchronization signal adjustment circuit A clock generation circuit that generates a clock necessary for displaying on the liquid crystal display with a second synchronization signal as a reference, a buffer circuit to which the second synchronization signal, the clock, and the digital RGB signal are input, and the liquid crystal display. It has a power supply circuit for supplying power and a sync signal monitoring circuit for constantly monitoring the sync signal input from the host, and the sync signal monitoring circuit is a horizontal signal WDT circuit for monitoring the horizontal signal of the sync signal. A first temporary constant setting circuit for setting the monitoring time of the horizontal signal, and a vertical signal WD for monitoring the vertical signal of the synchronizing signal. A circuit, and a second time constant setting circuit for setting the monitoring time of the vertical signal, the horizontal signal WDT
A synchronizing signal monitoring device for a liquid crystal display, comprising a circuit and a logical product circuit to which signals of the vertical signal WDT circuit are input. 2. The synchronization signal monitoring circuit detects that an abnormality has occurred in the host when the level of the synchronization signal has not changed after the setting value of the monitoring time has elapsed since the synchronization signal was input. The synchronizing signal monitoring apparatus for a liquid crystal display according to claim 1, further comprising: 3. The synchronization signal monitoring circuit, when detecting an abnormality, sends a stop signal to the buffer circuit and the power supply circuit to supply an input signal to the liquid crystal display and supply of power from the power supply circuit. 3. The synchronization signal monitoring device for a liquid crystal display according to claim 1, further comprising means for cutting off power supply to the backlight. 4. The AND circuit is configured to control the horizontal signal WDT.
4. The liquid crystal according to claim 1, further comprising means for transmitting a stop signal to the buffer circuit and the power supply circuit when a stop signal is input from at least one of a circuit and the vertical signal WDT circuit. Display synchronization signal monitoring device. 5. The synchronizing signal monitoring apparatus for a liquid crystal display according to claim 1, wherein the first temporary constant setting circuit and the second time constant setting circuit have the same circuit. 6. The synchronizing signal monitoring device for a liquid crystal display according to claim 1, wherein the first temporary constant setting circuit and the second time constant setting circuit each have a resistor and a capacitor. . 7. The synchronizing signal monitoring apparatus for a liquid crystal display according to claim 6, wherein the resistor and the capacitor include a variable resistor and a variable capacitor. 8. The horizontal signal WDT circuit and the vertical signal WDT circuit are charged at the monitoring time set by the first temporary constant setting circuit and the second time constant setting circuit, respectively, and the sync signal is generated. 2. The synchronizing signal monitoring device for a liquid crystal display according to claim 1, further comprising means for discharging at the rising edge of the. 9. The sync signal monitoring device for a liquid crystal display according to claim 1, wherein the sync signal monitoring circuit has means that can be easily attached to and detached from the signal generating unit.