JP2013092795A - Image processing apparatus, projection type display device, and method for reducing power consumption of image processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce, in an image processing apparatus using a CMOS type image processing circuit, power consumption due to current which wraps around, from a CPU connected to the image processing circuit and flows out from an output line of the image processing circuit, when the apparatus is stopped.SOLUTION: When an image processing apparatus is stopped, a reset signal is output from a CPU to an image processing circuit to set an output line of the image processing circuit to a low level or a high impedance state, and a clock signal supplied to the image processing circuit is stopped. Furthermore, power supply to a display device and its driving circuit is stopped, while continuing the power supply to the image processing circuit. As a result, power consumption due to wraparound of current from the CPU is suppressed.

Description

  The present invention relates to an image processing device, a projection display device, and a power consumption reduction method of the image processing device, and more particularly, an apparatus equipped with a CMOS type image processing circuit that obtains an operation clock signal and processes the image signal. And a power consumption reduction method thereof.

  Conventionally, in an apparatus such as a liquid crystal projector, a CMOS type image processing circuit that obtains an operation clock signal and processes an image signal is used for the purpose of reducing power consumption of the entire apparatus. The image processing circuit is connected to a display device that forms an image, for example, a drive circuit that drives a liquid crystal panel. This image processing circuit has a built-in look-up table for color adjustment for a liquid crystal panel. When an external digital video signal is received, the image processing circuit performs necessary processing to provide a driving circuit for a display device. Output.

  As a technique for reducing power consumption in such a projector, there is known a technique for stopping power supply to a device that consumes a large amount of power, such as a light source, when a video signal is not input for a predetermined time (for example, Patent Document 1 below). In addition, it is known that power consumption can be reduced for a semiconductor device using a CMOS element by lowering the frequency of a clock signal for operation (for example, see Patent Document 2 below).

JP 2002-182304 A JP 2004-326153 A

  However, in the case of an image processing circuit connected to a drive circuit for driving a display device, there is a case where power consumption cannot be sufficiently reduced only by shutting off the power supply to the image processing circuit or the drive circuit. It was. An object of the present application is to efficiently reduce power consumption in an image processing apparatus and a projection display apparatus.

  The present invention solves the above problems by the following application examples or embodiments. Hereinafter, it demonstrates in order.

[Application Example 1]
An image processing apparatus that processes an image signal input from the outside,
A CMOS type image processing circuit that obtains a clock signal for operation and processes the image signal;
A drive circuit connected to the image processing circuit for driving a display device;
A power supply unit that supplies power to each circuit in the image processing apparatus including the image processing circuit and the drive circuit;
When it is determined that the operation of the image processing apparatus is to be stopped, among the power supply from the power supply unit, at least the power supply to the drive circuit is stopped and the frequency of the clock signal is set to the operation of the image processing apparatus. And a stop processing unit that outputs a stop control signal that sets the output of the image processing circuit to a high impedance state or a low level.

  In this image processing apparatus, when it is determined that the operation of the image processing apparatus is to be stopped, a stop control signal is output, and among the power supply from the power supply unit, at least the power supply to the drive circuit is stopped and the clock signal The frequency is set lower than that during the operation of the image processing apparatus, and the output of the image processing circuit is set to a high impedance state or a low level. Therefore, in this application example, power supply to the CMOS type image processing circuit is continued, but the frequency of the clock signal is lower than that during the operation, and the output of the image processing circuit is in a high impedance state. Alternatively, since it is at the low level, current does not flow into the drive circuit via the image processing circuit due to the power supply to the drive circuit connected to the image processing circuit being cut off. As a result, it is possible to control the power consumption of the entire image processing apparatus.

[Application Example 2]
An image processing apparatus according to Application Example 1,
A controller connected to at least the image processing circuit via a common bus and controlling the operation of each circuit in the image processing apparatus;
An image processing apparatus that realizes the stop processing unit as one of processes executed by the control unit.

  In this image processing apparatus, the stop processing unit is realized as one of the processes executed by the control unit. Since the image processing apparatus is often equipped with hardware such as a computer that corresponds to a control unit that controls the entire apparatus, the stop time processing unit can also be incorporated as one function of such a control unit. By adopting such a configuration, it is not necessary to separately provide a stop processing unit, and the device configuration can be simplified.

[Application Example 3]
An image processing apparatus according to Application Example 1 or Application Example 2,
The stop processing unit
When the standby mode switch provided in the operation unit operated by the user of the device is operated,
When it is detected that the state of the device is in an abnormal state, or when at least one of a state in which no external image signal is detected continues for a predetermined time or more is satisfied, the image An image processing apparatus that performs the determination that the operation of the processing apparatus is stopped.

  According to such an image processing apparatus, it is possible to easily and accurately determine that the operation of the apparatus is to be stopped. As the operation unit, a switch panel or the like may be provided on the apparatus itself, or a switch may be provided on the remote controller side. Further, the standby mode switch may be shared with other switches or the like, or may be a switch using voice recognition or the like. Of course, when the image processing apparatus is connected to another device via a network or the like, a function similar to the standby mode switch can be realized by sending a command from the other device. In addition, the status of the device is abnormal when the temperature inside the device exceeds the upper limit, when vibrations of a predetermined level or higher are detected, or when the switches are improperly operated. Various situations can be assumed. Furthermore, when the image signal from the outside continues for a predetermined period or longer, it may be determined by the time after the image signal is lost, or may be determined by the cumulative number of clock signals after the image signal is lost. May be.

[Application Example 4]
An image processing apparatus according to any one of Application Examples 1 to 3,
The image processing circuit includes a gate made of a CMOS element at the final stage of a plurality of lines on the output side connected to the driving circuit, and when receiving a stop control signal, controls the gate, An image processing device that sets the output to a high impedance state or low level.
Such an image processing apparatus can set the output of the image processing circuit to a high impedance state or a low level as necessary with a simple configuration. In addition, as a configuration having the same function and effect, a configuration in which a gate is an external circuit, a configuration using an analog switch instead of the gate, a micro relay that requires electric power only at the time of switching, and the like can be employed.

[Application Example 5]
An image processing apparatus according to Application Example 4,
The image processing circuit includes a latch that holds the stop control signal corresponding to the plurality of lines, and the output of the gate is set to a high impedance state or a low level by the output signal of the latch. An image processing apparatus connected to the gate.
In such an image processing apparatus, since the image processing circuit includes a latch, it is not necessary to maintain a stop control signal. Therefore, the configuration can be adopted when the operation of the stop processing circuit is stopped intermittently. If this configuration is adopted, the power consumption can be further reduced.

[Application Example 6]
The image display device according to any one of application examples 1 to 5, wherein the image processing circuit includes a lookup table for color adjustment of the display device.
When the image processing circuit includes a color adjustment look-up table, the image processing circuit includes signal lines for each color and several bits (mostly 8 bits), and when the operation is stopped, a large number of signal lines are provided. In order to solve the problem that current flows through the, an excellent effect is obtained that it is not necessary to provide a large number of switches.

[Application Example 7]
The image processing apparatus according to any one of Application Examples 1 to 5, wherein the stop processing unit sets the frequency of the clock signal to 0.
When the frequency of the clock signal for operating the image processing circuit is reduced, the frequency is set to 0, so that the power consumption is 0 in principle except for the leakage current. Supply of power continues, but in the case of a CMOS type circuit, if the operation clock signal is lost, power is not consumed even if power is supplied.

The present invention can also be realized as a projection display device.
[Application Example 8]
A projection display device that processes and displays an image signal,
A display device for forming an image to be projected using light from a light source;
A CMOS type image processing circuit that obtains a clock signal for operation and processes the image signal;
A drive circuit connected to the image processing circuit for driving the display device;
A power supply unit that supplies power to each circuit in the projection display device including the image processing circuit and the drive circuit;
A control unit connected via at least a common bus to the image processing circuit and controlling the operation of each circuit in the projection display device;
When it is determined to stop the operation of the projection display device, at least the power supply to the drive circuit among the power supply from the power supply unit is stopped, and the frequency of the clock signal is set to the projection display device. And a stop processing unit that outputs a stop control signal that sets the output of the image processing circuit to a high impedance state or a low level.

  In this projection display device, similarly to the image display device, when it is determined that the operation of the projection display device is to be stopped, a stop control signal is output, and at least the power supply from the power supply unit is supplied to the drive circuit. At the same time, the frequency of the clock signal is set lower than that during the operation of the projection display device, and the output of the image processing circuit is set to the high impedance state or the low level. Therefore, in this application example, power supply to the CMOS type image processing circuit is continued, but the frequency of the clock signal is lower than that during the operation, and the output of the image processing circuit is in a high impedance state. Alternatively, since it is at the low level, current does not flow into the drive circuit via the image processing circuit due to the power supply to the drive circuit connected to the image processing circuit being cut off. As a result, it is possible to control the power consumption of the projection display device as a whole.

As such a projection display device, a liquid crystal panel is used for image formation, a so-called DMD (digital micromirror device) that drives a minute reflection element, a self-luminous light source such as an EL or plasma, etc. Various configurations such as those used can be employed. Further, the configuration is not limited to the type in which an image is projected onto a screen, and a configuration in which the image is stored in an apparatus having a screen, such as a rear projection television, can be employed.
The present invention can also be understood as a method invention. In addition, the present invention can be implemented in the form of a program that causes a computer to implement a method for reducing power consumption, a recording medium that records the program, or the like.

1 is a schematic configuration diagram showing a schematic configuration of a projector PJ as an embodiment of the present invention. It is a block diagram which shows the structural example of the image control circuit 170 in an Example. 3 is a circuit diagram showing a configuration of a final stage of an output line of the image processing circuit 180. FIG. FIG. 10 is a circuit diagram showing another configuration example for controlling the output line of the image processing circuit 180 to a low level. It is explanatory drawing which shows notionally the structure of the interface with the display device drive circuit 182 and the light valves 120R, G, and B which are display devices. It is a flowchart for demonstrating the process in an Example. It is a flowchart which shows the operation mode monitoring process routine in an Example. It is a timing chart which shows the mode of each signal in an Example.

Next, embodiments of the present invention will be described in the following order based on examples.
A. Projector configuration:
B. Image control circuit configuration:
C. Processing performed by the CPU built in the image control circuit:
D. Variations:

A. Projector configuration:
FIG. 1 is an explanatory diagram illustrating a schematic configuration of a projector PJ in the embodiment. This projector PJ is a rear projection type projector. In the rear projection type projector PJ, light representing an image is projected on the back side of the screen SC, and the observer observes the image from the surface side of the screen SC.

  The projector PJ includes three illumination optical systems 110R, G, and B, three liquid crystal light valves 120R, G, and B, a cross dichroic prism 130, a projection optical system 140, and an image control circuit that controls the operation of the entire projector. 170. In FIG. 1, the illustration of the optical system is considerably simplified. In addition, signal lines from the image control circuit 170 to the liquid crystal light valves 120R, 120G, and 120B are partially omitted. The image control circuit 170 corresponds to the claimed image processing apparatus, and the configuration and operation thereof will be described later.

  The first illumination optical system 110R includes a first light emitting device 102R that emits red light R, and guides the red light R to the first liquid crystal light valve 120R. Similarly, the second illumination optical system 110G includes a second light emitting device 102G that emits green light G, and guides the green light G to the second liquid crystal light valve 120G. The third illumination optical system 110B includes a third light emitting device 102B that emits blue light B, and guides the blue light B to the third liquid crystal light valve 120B. The light emitting devices 102R, G, and B may be configured to use light from a discharge lamp such as a metal halide lamp separated by each color filter, or an LED or semiconductor laser that emits light of each color of R, G, and B. It may be used.

  Each liquid crystal light valve 120R, G, B modulates the color light R, G, B emitted from the corresponding illumination optical system 110R, G, B. Accordingly, light (color image light) representing red, green, and blue images is emitted from the liquid crystal light valves 120R, G, and B.

  The cross dichroic prism 130 combines the three color image lights emitted from the three liquid crystal light valves 120R, G, and B. The projection optical system 140 projects the combined image light on the screen SC and forms a color image (combined image) on the screen SC.

  The first to third liquid crystal light valves 120R, 120G, and 120B included in the first to third illumination optical systems 110R, 110G, and 110B of the projector PJ are connected to the image control circuit 170 by a cable such as a flat cable. An image to be projected is formed based on a drive signal that is connected and output from a drive circuit built in the image control circuit 170. In addition to the image control circuit 170, a power supply unit 150 is provided inside the projector PJ. The power supply unit 150 generates a power source required by each unit of the projector PJ from a commercial power source. As will be described later, the power supply unit 150 receives a control signal from the image control circuit 170 and finely controls which device in the projector PJ is supplied with power.

B. Image control circuit configuration:
Next, the configuration of the image control circuit 170 will be described. FIG. 2 is a block diagram showing the configuration of the image control circuit 170 provided in the projector PJ of this embodiment together with the power supply unit 150. As shown in the figure, the image control circuit 170 is connected to the CPU 172 that controls the internal processing of the projector PJ, the memory 176 that is connected to the CPU 172 via the control signal bus 174, and the CPU 172 also via the control signal bus 174. A CMOS type image processing circuit 180, a display device driving circuit 182 connected to the image processing circuit 180, a switch panel 186 for transmitting a user operation to the CPU 172, and the like.

  The CPU 172 executes the program stored in the memory 176. In addition to the control signal bus 174, signal lines for outputting various control signals are connected to the CPU 172. Specifically, there are a signal line for outputting the clock signal CLK and the reset signal RST to the image processing circuit 180, a signal line for outputting the power control signal PCS to the relay 188, and the like. Further, a signal line for reading the switch state from the switch panel 186 is connected to the CPU 172.

  The memory 176 stores a program executed by the CPU 172 and various setting values. In this embodiment, a nonvolatile and electrically rewritable EEPROM is used. When the projector PJ is powered on, the CPU 172 starts processing from a predetermined address in the predetermined memory 176. As the memory 176, a volatile semiconductor memory is used, an external storage device such as a hard disk or a flash memory drive is built in, and a program is loaded and executed from a storage device such as a hard disk when the power is turned on. There is no problem.

  The image processing circuit 180 is an application specific integrated circuit (ASIC), and is configured to execute image processing necessary for the projector PJ. The image processing circuit 180 receives an external digital video signal, performs predetermined image processing on the digital video signal, and outputs the processed data to the display device driving circuit 182. Image processing executed by the image processing circuit 180 includes correction processing for absorbing differences in characteristics of the light valves 120R, G, and B, which are display devices, keystone correction for removing distortion of the projected image, contrast, There are image quality corrections that adjust the color tone. Since the projector PJ of this embodiment employs a rear projection method, the keystone correction is fixed and may be omitted.

  The image processing circuit 180 performs various corrections in response to an instruction from the CPU 172, such as on / off of execution or the degree of correction. Therefore, the CPU 172 and the image processing circuit 180 are connected by a control signal bus 174. The clock signal CLK received by the image processing circuit 180 from the CPU 172 is a reference signal that determines the operation timing of the image processing circuit 180. All logic circuits such as gates in the image processing circuit 180 operate in synchronization with the clock signal CLK. Therefore, if the frequency of the clock signal CLK is lowered, the processing operation of the image processing circuit 180 is also slowed down. The image processing circuit 180 is constituted by a CMOS element, and the power consumption thereof depends on the frequency of the clock signal CLK. When the frequency of the clock signal CLK for operation decreases, the power consumption decreases as the operation speed decreases.

  The image processing circuit 180 receives a reset signal RST from the CPU 172 in addition to the clock signal CLK. Upon receiving this reset signal RST, the image processing circuit 180 resets its operation mode to the initial mode and sets all outputs to low level. For this reason, the image processing circuit 180 includes an AND gate 201 of a CMOS element at the final stage of the output line, as illustrated in FIG. A reset signal RST is connected to one input of the AND gate 201. For this reason, as long as the CPU 172 keeps the reset signal RST at the low level, all outputs of the image processing circuit 180 are kept at the low level. Instead of the CPU 172 continuing to maintain the reset signal RST at the low level, a flip-flop circuit (D-FF) 194 is provided in the image processing circuit 180 as shown in FIG. There is no problem even if a circuit configuration of connecting to is used. In this case, the CPU 172 may output the reset signal RST once to the clock input terminal of the flip-flop circuit 194. Since the data terminal D of the flip-flop circuit 194 is pulled up, the negative logic output Q \ ("\" indicates negative logic) is set to the low level when the reset signal RST is received at the clock input terminal. Is done. To reset the flip-flop circuit 194, another signal output from the CPU 172 (the preset signal PRESET in FIG. 4) may be used.

  In this embodiment, the image processing circuit 180 outputs to the display device driving circuit 182 a signal obtained by dividing an image to be displayed into RGB and a display timing signal. The former is 8 bits for each color, This is a 24-bit signal. As described above, the AND gate 201 is provided at the final stage of the output of the image processing circuit 180, and when the reset signal RST is output from the CPU 172, the output of the image processing circuit 180 is all fixed at the low level. Therefore, no current flows from the image processing circuit 180 toward the display device driving circuit 182 regardless of the operations of the image processing circuit 180 and the display device driving circuit 182.

  The display device driving circuit 182 receives the RGB signals and the timing signal TS from the image processing circuit 180, and outputs signals for driving the light valves 120R, G, and B that are display devices. This drive signal is an analog video signal. Of course, the display device drive circuit 182 also outputs timing signals to the light valves 120R, 120G, and 120B.

  Next, the power supply unit 150 and its connection will be described. As described above, the power supply unit 150 generates a DC power supply for operation of each unit from commercial AC. In this embodiment, the power supply unit 150 generates a plus 5 volt power source for operation of the CPU 172, the image processing circuit 180, and the like, a 12 VDC power source used for an analog video signal, and the like. The power supply line from the power supply unit 150 is divided into three in this embodiment. One is a power supply line PS1 that supplies DC 5 volts. The power supply line PS1 supplies power to the CPU 172, the memory 176, and the image processing circuit 180 all at once. The other is a power supply line PS2 for supplying DC 5 volts. The power supply line PS2 processes the digital signal of the display device drive circuit 182 via the normally open contact Rb1 of the relay 188. Supply power to the circuit that is The last power supply line PS3 supplies DC 12 volts for an analog video signal, and is a circuit that drives the analog video signal of the display device drive circuit 182 via the normally open contact Rb2 of the relay 188. Are connected to the light valves 120R, G, B. These contacts Rb1 and Rb2 are closed when the CPU 172 drives the relay 188.

  FIG. 5 schematically shows the circuit configuration of the output stage that handles the display device driving circuit 182 for analog video signals. As shown in the figure, the final stage of the output of the display device drive circuit 182 is provided with an analog drive circuit (op-amp) so that an analog signal can be handled. The power supplied from the power supply line PS3 is used to drive the final stage drive circuit. The power supply line PS3 supplies the same power to the light valves 120R, G, and B. Note that the light emitting devices 102R, G, and B are also supplied with power from the same power supply line PS3.

C. Processing performed by the CPU built in the image control circuit:
Next, the processing executed by the CPU 172 and the operation of each circuit in that case will be described. FIG. 6 is a flowchart schematically showing processing executed by the CPU 172 of the image control circuit 170 in this embodiment. FIG. 7 is a flowchart showing an operation mode monitoring process routine executed by the CPU 172. The operation state of each circuit corresponding to these processes of the CPU 172 is shown in the timing chart of FIG.

  When the power is turned on, the CPU 172 starts the processing (main routine) shown in FIG. The CPU 172 first executes an initialization process (step S110). In the initialization process, the various settings of the projector PJ are returned to the initial values, and the relay 188 is driven to close both the normally open contacts Rb1 and Rb2. As a result, when the initialization process is completed, the digital signal processing circuit of the display device driving circuit 182 is supplied with power of 5 volts via the power supply line PS2, and the analog video signal processing circuit of the display device driving circuit 182 is connected. 12 volt power is supplied to the light valves 120R, G, and B through the power supply line PS3, and both circuits start operating.

  Subsequently, the CPU 172 checks the digital video signal DMS (step S120), and if it determines that the digital video signal is input (step S130), it executes a normal display processing routine (step S150). In this display processing routine (step S150), the CPU 172 turns on the light emitting devices 102R, G, B, for example, based on the operation of the switch panel 186, enables the image processing circuit 180, and processes the digital video signal DMS. Then, the display device driving circuit 182 converts the analog video signal, and starts the operation of outputting it to the light valves 120R, G, and B together with the required timing signal. The image processing circuit 180 continues the processing of the digital video signal based on the conditions set by the CPU 172 once the process of step S150 is performed. As a result, images corresponding to the input digital video signal DMS are formed on the light valves 120R, G, and B, and finally, the light from the light emitting devices 102R, G, and B, which are light sources, is used on the screen SC. Then, an image is displayed. The state of each signal in this state is shown as section A in FIG.

  On the other hand, if the CPU 172 determines that the digital video signal DMS has not been input for a predetermined period (step S130), the display processing routine (step S150) is not executed. In any case, a process for starting the monitoring process routine is subsequently performed (step S160). This process is a routine for executing a process for reducing the power consumption of the projector PJ based on the operating conditions of the projector PJ. Usually, the process resides in a memory and is managed by another application under the management of the OS. It is a process that operates in the background of the program.

  Therefore, the operation mode monitoring process will be described next with reference to FIG. This process is repeated at predetermined intervals and executed in the background. When this processing routine is started, the CPU 172 first determines whether or not the power switch (PSW) on the switch panel 186 has been operated (step S210). This power switch is not a power switch for supplying commercial power to the projector PJ, but a switch for operating on / off of use of the projector PJ. In general, by operating this switch, the light source of the projector PJ (in this embodiment, the light emitting devices 102R, G, B) is turned on or off. In the present embodiment, the processing shown in FIG. 7 is repeatedly performed at predetermined intervals. However, the processing may be realized as interrupt processing caused by the operation of the power switch. Further, the operation of the power switch may be determined by a simple on / off operation of a button on the switch panel 186, or it may be determined that the power switch has been operated by a long press or double press of the button. You may do it.

  If the power switch is not operated, the process is terminated without performing anything. On the other hand, if the power switch is operated, the projector PJ then determines whether or not it is operating (step S220). If the projector PJ is already operating, that is, if the input digital video signal is being projected, the processing of steps S230 to S260 is executed. If the projector PJ is not operating, the processing of steps S235 to S265 is executed. . These processes are symmetrical as will be described later.

First, processing when the projector PJ is operating will be described. If it is determined that the projector PJ is in operation (step S220), it is then determined whether or not the projector PJ stop condition is satisfied (step S230). It is determined that the projector PJ stop condition is satisfied.
(1) When the standby switch provided on the switch panel is operated
(2) When a digital video signal has not been input for a predetermined period (for example, 2 minutes) or longer,
(3) When it is detected by the temperature sensor built in the projector PJ that the temperature inside the projector PJ is higher than a predetermined temperature,
Etc. Of course, in other states, for example, when the current flowing through the light-emitting device is equal to or greater than a predetermined value and it is determined that the light-emitting device needs to be replaced, the accumulated usage time of the light-emitting device is equal to or greater than the predetermined value. When it is determined that it is necessary, it may be determined that the stop condition is satisfied, for example, when the rotation of the fan that cools the inside of the projector PJ is stopped or when there is an abnormality in which the rotation is less than or equal to a predetermined number of rotations. If it is determined that the projector PJ is operating and the stop condition is not satisfied, nothing is done and the process goes to RTN and ends.

  When determining that the projector PJ is in operation and the stop condition is satisfied, the CPU 172 first outputs the reset signal RST (step S240), and then stops the clock signal CLK (step S250). As a result, in the image processing circuit 180, one input of the gate (see FIGS. 3 and 4) provided in the final stage of output becomes inactive (low level), and all outputs to the display device driving circuit 182 become low level. Become. Further, since the clock signal CLK is stopped, the image processing circuit 180 substantially stops its operation.

  Subsequent to the above processing (steps S240 and S250), the CPU 172 sends a stop signal to the relay 188 and performs processing for switching the contact to a normally open state (step S260). Since the contact is in the open state, as a result, the CPU 172 stops the power supply to the power supply lines PS2 and PS3 as described in step S260 of FIG. The power supply line PS2 is a 5-volt DC power supply to the logic circuit of the display device driving circuit 182, and the power supply line PS3 is an analog circuit of the display device driving circuit 182 and light pulp 120R, G, B, which are display devices. Since 12 volt DC power is supplied to the light emitting devices 102R, G, B, respectively, the display device driving circuit 182 and the light valves 120R, G, B and the light emitting devices 102R, G are stopped by stopping both of them. , B completely stops the operation. The state of each signal in this state is shown in period B of FIG.

  In this case, since the power supply by the power supply line PS1 is continued as shown in the section B of FIG. 8, the CPU 172, the memory 176, and the image processing circuit 180 continue to operate. However, since all outputs of the digital video signal of the image processing circuit 180 are at a low level, no matter what the output from the CPU 172 to the image processing circuit 180 is, the image processing circuit 180 drives the display device. No current flows through the circuit 182. Further, since the clock signal CLK is stopped, the power consumption of the image processing circuit 180 is infinitely close to 0. As a result, when it is determined that the stop condition is satisfied (step S230), the power consumption of the projector PJ is reduced to the power saving level of the CPU 172 and the memory 176.

After performing the above processing, the process exits to RTN and is temporarily terminated. In this case, the projector PJ is stopped. Therefore, when the power switch is operated when the operation mode monitoring process routine is executed next time, the determination in step S220 is “NO”, that is, it is determined that the projector PJ is not operating. The process proceeds to step S235 and subsequent steps. In step S235, it is determined whether or not the restart condition for the stopped projector PJ is satisfied. “Establishment of resumption condition” is a state in which “establishment of stop condition” described above is not established. For example,
(1) When the standby switch provided on the switch panel is operated,
(2) When a digital video signal is input,
(3) When it is detected by the temperature sensor built in the projector PJ that the inside of the projector PJ has dropped to a temperature lower than a predetermined temperature and has returned to the normal state,
Can be considered.

  If the restart condition is not satisfied, the process exits to RTN and ends this routine. On the other hand, if it is determined that the resumption condition is satisfied (step S235), the clock signal CLK is returned and supplied (step S245), the reset signal RST is further turned off (step S255), and the relay 188 is operated. Thus, the normally open contact is closed (step S265). As a result, the power supply lines PS2 and PS3 are restored to the original state, and each power supply is resumed.

  This state is shown in a period C in FIG. Since the clock signal CLK is supplied, the reset signal RST is turned off, and the power supply is restarted, the image processing circuit 180 restarts the processing, and the display device driving circuit 182 and the light valves 120R, G, and B are supplied. Alternatively, the light emitting devices 102R, G, and B also resume their operations. As a result, the video is displayed on the screen SC in accordance with the input digital video signal. As shown in FIG. 8, each signal in the period C is restored to the period A state.

  Although one embodiment of the present invention has been described above, according to the projector PJ of the present embodiment, the display device driving circuit 182 and the light emitting devices 102R, G, B when the video signal is not input for a predetermined time. Since power supply to the projector is stopped, the power consumption of the projector PJ can be reduced. In addition, since all the digital video signals DMS of the image processing circuit 180 are at a low level at this time, no current flows from the image processing circuit 180 to the display device driving circuit 182. Even if the supply of power to the image processing circuit 180 is stopped, the current flows from the CPU 172 connected to the image processing circuit 180 via the control signal bus 174 when the CPU 172 is operating. May be caused by wraparound. When current wraparound occurs, the image processing circuit 180 made of a CMOS element may cause latch-up. In order to prevent such a situation, for example, a switch for disconnecting the connection with the image processing circuit 180 may be provided on the control signal bus with the CPU 172. However, switches are provided on a number of signal lines constituting the bus. That will increase costs. In this embodiment, a gate is provided at the output of the image processing circuit 180 and the output is set to a low level to prevent such a situation from occurring, and a switch for latch-up countermeasures is not required.

  At the same time, since the supply of the clock signal CLK to the image processing circuit 180 is stopped, the power consumption in the image processing circuit 180 is also substantially reduced to zero. As a result, although the power supply to the image processing circuit 180 is continued, the flow of current to the display device driving circuit 182 due to the sneak from the CPU 172 is avoided, and the total power consumption is sufficiently suppressed.

D. Variations:
As mentioned above, although the Example of this invention was described, this invention is not limited to such an Example at all, and can implement in a various aspect within the range which does not deviate from the summary of this invention. For example, instead of stopping the clock signal CLK in step S250, it is possible to perform a process of sufficiently reducing the frequency of the clock signal CLK. In a circuit using a CMOS element, the power consumption depends on the frequency of the clock signal CLK. Therefore, even if the clock signal CLK is not stopped, the power consumption of the image processing circuit 180 can be sufficiently suppressed by reducing the frequency. Further, the power supply lines of the light valves 120R, G, B and the light emitting devices 102R, G, B may be separated and controlled at different timings. Further, the light emitting devices 102R, G, B and the light valves 120R, G, B may be integrated, for example, a self-light emitting type and a configuration using a CRT, EL, or the like that can directly form an image. There is no problem.

  In this embodiment, when it is determined in step S230 that the stop condition of the projector PJ is satisfied, all the digital video outputs of the image processing circuit 180 are set to the low level, but all outputs may be set to the high impedance state. good. In this case as well, no current flows from the image processing circuit 180 to the display device driving circuit 182.

  Of the circuits and configurations used in the embodiments described above, or the processes performed, those not described in the scope of the claims are not essential requirements for carrying out the present invention. Of course, the present invention can also be implemented by a circuit, configuration, or processing equivalent to those described in the embodiments.

102R, G, B ... Light-emitting device 110R, G, B ... Illumination optical system 120R, G, B ... Liquid crystal light valve 130 ... Cross dichroic prism 140 ... Projection optical system 150 ... Power supply unit 170 ... Image control circuit 172 ... CPU
174 ... Control signal bus 176 ... Memory 180 ... Image processing circuit 182 ... Display device drive circuit 186 ... Switch panel 188 ... Relay 194 ... Flip-flop circuit PJ ... Projector PS1 ... Power supply line PS2 ... Power supply line PS3 ... Power supply line RST ... Reset signal Rb1, Rb2 ... Contact SC ... Screen TS1 ... Timing signal TS2 ... Timing signal

The present invention solves the above problems by the following application examples or embodiments. Hereinafter, it demonstrates in order. An image processing apparatus for processing an image signal input from the outside of the present invention obtains a clock signal for operation and displays a CMOS type image processing circuit for processing the image signal and connected to the image processing circuit. A drive circuit for driving a device for use, a power supply unit for supplying power to each circuit in the image processing apparatus including the image processing circuit and the drive circuit, and the power supply when it is determined to stop the operation of the image processing apparatus A stop processing unit for stopping a power supply to at least the drive circuit among the power supply from the unit and outputting a stop control signal for lowering the frequency of the clock signal than during the operation of the image processing apparatus; And when the stop control signal is input, the image processing circuit outputs a high impedance output to the drive circuit in a state where the input of the image signal is continued. As Nsu state or a low level, and summarized in that to prevent the occurrence of latch-up phenomenon of the image processing circuit of the CMOS type.

Claims (9)

An image processing apparatus that processes an image signal input from the outside,
A CMOS type image processing circuit that obtains a clock signal for operation and processes the image signal;
A drive circuit connected to the image processing circuit for driving a display device;
A power supply unit that supplies power to each circuit in the image processing apparatus including the image processing circuit and the drive circuit;
When it is determined that the operation of the image processing apparatus is to be stopped, among the power supply from the power supply unit, at least the power supply to the drive circuit is stopped and the frequency of the clock signal is set to the operation of the image processing apparatus. And a stop processing unit that outputs a stop control signal that sets the output of the image processing circuit to a high impedance state or a low level. The image processing apparatus according to claim 1,
A controller connected to at least the image processing circuit via a common bus and controlling the operation of each circuit in the image processing apparatus;
An image processing apparatus that realizes the stop processing unit as one of processes executed by the control unit. The image processing apparatus according to claim 1 or 2,
The stop processing unit
When the standby mode switch provided in the operation unit operated by the user of the device is operated,
When it is detected that the state of the device is in an abnormal state, or when at least one of a state in which no external image signal is detected continues for a predetermined time or more is satisfied, the image An image processing apparatus that performs the determination that the operation of the processing apparatus is stopped. An image processing apparatus according to any one of claims 1 to 3,
The image processing circuit includes a gate made of a CMOS element at the final stage of a plurality of lines on the output side connected to the driving circuit, and when receiving a stop control signal, controls the gate, An image processing device that sets the output to a high impedance state or low level. The image processing apparatus according to claim 4,
The image processing circuit includes a latch that holds the stop control signal corresponding to the plurality of lines, and the output of the gate is set to a high impedance state or a low level by the output signal of the latch. An image processing apparatus connected to the gate.   6. The image display apparatus according to claim 1, wherein the image processing circuit includes a lookup table for color adjustment of the display device.   The image processing apparatus according to claim 1, wherein the stop processing unit sets a frequency of the clock signal to zero. A projection display device that processes and displays an image signal,
A display device for forming an image to be projected using light from a light source;
A CMOS type image processing circuit that obtains a clock signal for operation and processes the image signal;
A drive circuit connected to the image processing circuit for driving the display device;
A power supply unit that supplies power to each circuit in the projection display device including the image processing circuit and the drive circuit;
A control unit connected via at least a common bus to the image processing circuit and controlling the operation of each circuit in the projection display device;
When it is determined to stop the operation of the projection display device, at least the power supply to the drive circuit among the power supply from the power supply unit is stopped, and the frequency of the clock signal is set to the projection display device. And a stop processing unit that outputs a stop control signal that sets the output of the image processing circuit to a high impedance state or a low level. A method for reducing power consumption of an image processing apparatus that processes an image signal input from the outside,
Each of the image processing apparatuses includes a CMOS type image processing circuit that obtains an operation clock signal and processes the image signal, and a drive circuit that is connected to the image processing circuit and drives a display device. Supply power to the circuit during operation of the image processing apparatus,
When it is determined to stop the operation of the image processing apparatus, among the power supply from the power supply unit, at least power supply to the drive circuit is stopped,
A method for reducing power consumption of an image processing apparatus, wherein a frequency of the clock signal is set lower than that during operation of the image processing apparatus, and an output of the image processing circuit is set to a high impedance state or a low level.

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