JP2008305250A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor reducing power consumption for carrying out signal processing of continuous data. <P>SOLUTION: The data processor is provided with: a first signal processing section 120 for carrying out signal processing of data stored in a first data storage section 110 a plurality of number of times; a second data storage section 112 for storing data processed by the first signal processing section 120; a second signal processing section 130 for reading out data stored in the second data storage section 112 by real-time processing, and carrying out signal processing; a signal processing control section 150 for having the first signal processing section 120 process data in a pipeline configuration in which each signal processing is assigned to a pipeline stage based on a feature of data, and controlling the first signal processing section 120 so as to operate intermittently, by performing each signal processing at higher speed than the real-time processing; and a clock/power supply control section 160 for restricting the supply of a clock or power supply to the first signal processing section 120 and the signal processing control section 150, while the intermittent operation is stopped. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data processing apparatus, and more particularly to a data processing apparatus that performs signal processing for reproduction of audiovisual data, broadcast signals, and the like.

  As a conventional data processing apparatus, as shown in FIG. 4, a broadcast receiving unit 196 that receives broadcast waves, a signal processing unit 126 that decodes data received by the broadcast receiving unit 196, and a result of decoding by the signal processing unit 126 An output data storage unit 136 for storing decoded data, an output unit 146 for outputting data stored in the output data storage unit 136, a control unit 156 for controlling the operation of each unit of the apparatus, a broadcast receiving unit 196, and a signal A data broadcast that includes a power supply unit 166 that controls power supply to the processing unit 126 and the output data storage unit 136 and a timer unit 176 that notifies activation timing of the control unit 156 is updated several times a day. There is one that receives and decodes by intermittently operating the receiving unit 196 and the signal processing unit 126 (see, for example, Patent Document 1).

  In this conventional data processing apparatus, when it is time to receive a data broadcast, the control unit 156 that receives an interrupt from the timer unit 176 starts supplying power to the broadcast receiving unit 196, the signal processing unit 126, and the output data storage unit 136. Is done. Thereafter, the broadcast wave is received by the broadcast receiving unit 196, and the result decoded by the signal processing unit 126 is stored in the output data storage unit 136. Thereafter, the control unit 156 stops the processes in the broadcast receiving unit 196, the signal processing unit 126, and the output data storage unit 136, and the power supply unit 166 cuts off the power supply.

  As described above, the conventional data processing apparatus reduces the power consumption in the standby state by cutting off the power supply during the intermittent operation stop period.

As a conventional data processing apparatus, as shown in FIG. 5, when the clock frequency is 50 MHz, a three-stage pipeline configuration of IF stage, DEC stage, and EX stage is adopted, and when the clock frequency is 100 MHz, Process high-performance elements by switching the number of pipeline stages according to the clock frequency and power supply voltage, such as adopting a 4-stage pipeline configuration in which EX processing with long processing time is divided into EX1 stage and EX2 stage There is one that suppresses power consumption by not processing a stage with a long time (see, for example, Patent Document 2).
JP-A-11-122586 JP-A-9-319578

  However, although the data processing apparatus described in Patent Document 1 can reduce power consumption in applications such as data broadcasting in which the data update frequency is several times a day, audio visual data and broadcast signals can be reduced. In the case of use for signal processing of continuous data as in the case of reproduction, there is a problem that power consumption cannot be reduced.

  Moreover, although the data processing apparatus described in Patent Document 2 can improve the processing performance of the system by equalizing the processing time of each stage and reducing the processing time of the pipeline stage, In the case of an application that processes continuous data like a broadcast signal, it always operates, so the current consumption increases due to the offset current consumed just by supplying the power and clock to each part, and the power consumption is reduced. There was such a problem.

  The present invention has been made to solve the conventional problems, and provides a data processing device capable of reducing power consumption required for signal processing of continuous data such as audiovisual data and broadcast signals. For the purpose.

  A data processing apparatus according to the present invention includes a first data storage unit that stores data and a pipeline configuration in which the number of pipeline stages is smaller than the number of signal processes that process data read from the data storage unit. A first signal processing unit to process, a second data storage unit for storing data processed by the first signal processing unit, and data stored in the second data storage unit are read in real time The signal processing is performed in the pipeline stage so that the processing time of each pipeline stage is shortened based on the characteristics of the data to be processed by the second signal processing unit that performs signal processing by the first signal processing unit. The first signal processing to perform intermittent operation by allocating and causing the signal processing performed by the first signal processing unit to be performed at a speed faster than the real-time processing. A signal processing control unit configured to control the first signal processing unit, and the first signal processing unit and at least a part of the signal processing control unit during the stop period of the intermittent operation by limiting supply of at least one of a clock and power. A clock / power control unit that controls supply of at least one of a clock and power to the first signal processing unit and the signal processing control unit so as to limit power consumption of the signal processing unit and the signal processing control unit, A trigger signal output unit for outputting a trigger signal based on a data storage amount of the second data storage unit, and a clock for at least a part of the first signal processing unit and the signal processing control unit according to the trigger signal Alternatively, the clock / power control unit is requested to cancel the restriction on the supply of at least one of the power supplies, and the transition to the operation period of the intermittent operation is performed. The has a configuration in which a start control unit that requests the signal processing control unit.

  The present invention can provide a data processing apparatus capable of reducing power consumption required for signal processing of continuous data such as audiovisual data and broadcast signals.

  Embodiments of the present invention will be described below with reference to the drawings.

  A data processing apparatus according to an embodiment of the present invention is shown in FIG.

  As shown in FIG. 1, the data processing device 1 includes a first data storage unit 110 that stores data, and a first data processing unit that reads data stored in the first data storage unit 110 and performs a plurality of signal processes. The signal processing unit 120, the intermediate data storage unit 111 for temporarily storing data delivered between each signal processing performed by the first signal processing unit 120, and the data processed by the first signal processing unit 120 A second data storage unit 112 to store, a second signal processing unit 130 that performs signal processing by reading data stored in the second data storage unit 112 by real-time processing, and a first data storage unit 110 The feature extraction unit 140 that extracts the features of the data stored in the signal processing unit, the signal processing control unit 150 that controls the first signal processing unit 120 to operate intermittently, the first signal processing unit 120, A clock / power control unit 160 that controls supply of at least one of a clock and power to at least a part of the signal processing control unit 150, a start control unit 180 that controls the clock / power control unit 160, and a clock to the start control unit 180 A trigger signal output unit 170 that outputs a trigger signal at a timing for controlling the power supply control unit 160 is provided.

  In the present embodiment, an example in which the data processing apparatus of the present invention is configured by a mobile phone terminal will be described.

  The first data storage unit 110 is configured by a memory card. The data stored in the first data storage unit 110 is audio compression data in which audio is encoded by AAC (Advanced Audio Codec) or AAC + SBR (Spectral Band Replication).

  The first signal processing unit 120 includes a first processing unit 121, a second processing unit 122, and a third processing unit 123. The first processing unit 121 is configured by a hardware block that performs decoding processing for decoding voice compression data encoded by AAC, AAC + SBR, or the like, and outputs PCM (Pulse Code Modulation) data obtained by the decoding processing. Yes.

  The second processing unit 122 is configured by a hardware block that performs processing such as high-quality sound processing on the PCM data and outputs the processed PCM data. The third processing unit 123 performs an SBC encoding process for converting the processed PCM data into audio compression data encoded by SBC (Sub Band Codec) that can be processed by the second signal processing unit 130, and performs SBC encoding. It is composed of hardware blocks that output audio compression data obtained by processing.

  The intermediate data storage unit 111 is configured by a semiconductor memory, and stores data transferred between the first processing unit 121 and the second processing unit 122 and between the second processing unit 122 and the third processing unit 123. Configure an intermediate buffer to temporarily store. The second data storage unit 112 is configured by a semiconductor memory, and stores data processed by the first signal processing unit 120.

  The second signal processing unit 130 is configured by hardware that reads the data stored in the second data storage unit 112 in real time and converts it into an analog audio signal. The feature extraction unit 140 extracts features such as an encoding method, a bit rate, and a frame rate of the data stored in the first data storage unit 110.

  The signal processing control unit 150 is configured by a processor for controlling each unit of the data processing apparatus 1 such as a microcomputer. For example, the signal processing control unit 150 instructs the first signal processing unit 120 to start or stop the signal processing. It has become.

  In particular, the signal processing control unit 150 controls the first signal processing unit 120 to perform an intermittent operation by causing each signal processing to be performed at a speed faster than the real time processing.

  Specifically, the signal processing control unit 150 instructs the amount of data to be processed by the first signal processing unit 120 and notifies the first signal processing unit 120 that the processing of the specified amount of data has been completed. After receiving a request from the activation control unit 180 and receiving a request from the activation control unit 180 to receive a request for shifting to the operation period, the first signal processing unit 120 is instructed again for the amount of data to be processed. ing. As a result, the first signal processing unit 120 operates intermittently so as to alternate between an operation state in which signal processing is performed and a stop state in which signal processing is stopped.

  Further, the signal processing control unit 150 controls the first signal processing unit 120 so that the signal processing by the first processing unit 121, the second processing unit 122, and the third processing unit 123 is performed in a pipeline configuration. ing.

  Specifically, the signal processing control unit 150 calculates each processing time of the first processing unit 121 and the third processing unit 123 based on the information extracted by the feature extraction unit 140, and the calculated processing time is short. And the second processing unit 122 perform signal processing in one pipeline stage, and the first signal is generated in a two-stage pipeline configuration in which signal processing based on the longer processing time is performed in one pipeline stage. The processing unit 120 is configured to execute each signal processing.

  For example, when “AAC + SBR decoding processing time”> “SBC encoding processing time”> “AAC decoding processing time” is satisfied, the signal processing control unit 150 includes the first data storage unit 110. When the feature extraction unit 140 extracts that the encoding method of the data stored in is AAC + SBR, the first processing unit 121 performs “AAC + SBR decoding processing” in one pipeline stage, The first signal processing unit 120 is controlled so that the “higher sound quality processing” by the second processing unit 122 and the “SBC encoding processing” by the third processing unit 123 are performed in another pipeline stage. Yes.

  The trigger signal output unit 170 includes a timer, and based on the processing speed of the first signal processing unit 120 and the real-time reading speed of data by the second signal processing unit 130, the second data storage unit The timing at which the data storage amount 112 becomes less than the prescribed amount is measured, and a trigger signal is output to the activation control unit 180 at this timing.

  Here, the specified amount is determined in advance so that the data storage amount of the second data storage unit 112 from which data is read by the second signal processing unit 130 in real time processing does not become zero.

  In response to a stop request from the signal processing control unit 150, the activation control unit 180 requests to limit the supply of at least one of the clock and the power to at least a part of the first signal processing unit 120 and the signal processing control unit 150. A stop control process for outputting a request signal to the clock / power control unit 160 is performed. Here, at least a part of the signal processing control unit 150 includes a part that controls the first signal processing unit 120.

  In addition, the activation control unit 180 outputs a release request signal for requesting the release of the restriction requested in the stop control process to the clock / power control unit 160 in accordance with the trigger signal output by the activation control unit 180, thereby intermittent operation. The signal processing control unit 150 is requested to shift to the operation period.

  The clock / power control unit 160 responds to the restriction request signal output from the activation control unit 180, and supplies at least one of the clock and the power supplied to at least a part of the first signal processing unit 120 and the signal processing control unit 150. By limiting, the power consumption of the data processing apparatus 1 is suppressed. Further, the clock / power supply control unit 160 is configured to cancel the restriction in accordance with the cancellation request signal output from the activation control unit 180.

  When the clock supplied to at least a part of the first signal processing unit 120 and the signal processing control unit 150 is limited, the clock / power control unit 160 may cut off the clock, reduce the frequency, or reduce the voltage It is configured to control a clock generation circuit (not shown) that generates the clock so as to perform this.

  Further, when the power supplied to at least a part of the first signal processing unit 120 and the signal processing control unit 150 is limited, the clock / power control unit 160 can either shut off the power or lower the voltage. It is configured to control a power supply circuit (not shown) that supplies the power.

  The operation of the data processing apparatus 1 configured as described above will be described with reference to FIG. Note that the data processing apparatus 1 performs processing in units of frames that are processing units such as AAC, AAC + SBR, and SBC. In FIG. 2, it is assumed that data A is encoded by AAC + SBR, and data B is encoded by AAC.

  Here, it is assumed that the first signal processing unit 120 performs processing in units of 10 frames. In the following description, the data of 10 frames of data A are represented in order as A-1, A-2, A-3, and A-4, and the data of 10 frames of data B are sequentially represented by B-. 1, B-2, and B-3.

  Each data A and B is sampled at 48 kHz. That is, it takes 200 ms to process 10 frames of data A and B in real time.

  The first processing unit 121 can decode 10 frames of data encoded with AAC + SBR in 40 msec, and can decode 10 frames of data encoded with AAC in 20 msec. To do.

  Further, the second processing unit 122 can improve the sound quality of 10 frames of data in 20 msec, and the third processing unit 123 can perform SBC encoding of 10 frames of data in 30 msec. .

  In such a case, “AAC + SBR decoding processing” by the first processing unit 121 is performed on the data A in one pipeline stage, and “higher sound quality processing” and second processing by the second processing unit 122 are performed. A two-stage pipeline configuration is employed in which the “SBC encoding process” by the three processing units 123 is performed in another pipeline stage.

  The upper part of FIG. 2 shows the timing of each process for the data A and B by the first signal processing unit 120 and the second signal processing unit 130. First, when the intermittent operation becomes the first operation period, the first processing unit 121 performs AAC + SBR decoding processing on A-3. In parallel with this, the second processing unit 122 performs sound quality enhancement processing on A-2, and then the third processing unit 123 performs SBC coding processing on A-2 and performs SBC coding processing. A-2 is stored in the second data storage unit 112.

  When each process by the first processing unit 121, the second processing unit 122, and the third processing unit 123 is completed, the intermittent operation becomes a stop period. Then, at least a part of the first signal processing unit 120 and the signal processing control unit 150 is in a power saving state because supply of at least one of the clock and the power is restricted by the clock / power control unit 160.

  On the other hand, in the second signal processing unit 130, the data stored in the second data storage unit 112 is continuously read out in real time, decoded, and converted into an analog audio signal. As a result, the data stored in the second data storage unit 112 is read from the second signal processing unit 130 and consumed as needed.

  When the amount of data stored in the second data storage unit 112 is less than the specified amount, the restriction by the clock / power control unit 160 on the first signal processing unit 120 and the signal processing control unit 150 is released, and the operation state is reached. The first signal processing unit 120 starts storing data in the second data storage unit 112, and the intermittent operation becomes the second operation period.

  Further, when the intermittent operation is in the third operation period, the processing target is switched from data A to data B. Here, signal processing for B-1 of data B is started after all signal processing for A-4 of data A is completed.

  In the second processing unit 122, in order to avoid a conflict between the signal processing for the A-4 of the data A and the signal processing for the B-1 of the data B, the signal processing for the A-4 of the data A The signal processing for data B with respect to B-1 is not executed in parallel.

  Similar to the signal processing for data A, the signal processing for data B is executed intermittently based on the data storage amount of the second data storage unit 112.

  The lower part of FIG. 2 shows the transition of the data storage amount of the second data storage unit 112. First, the data is read from the second data storage unit 112 by the second signal processing unit 130 from time T1 to T2, while the data is written by the first signal processing unit 120. The data storage amount of the second data storage unit 112 increases rapidly.

  Since the data is only read from the second data storage unit 112 by the second signal processing unit 130 from the time T2 when the data writing is completed, the data storage amount of the second data storage unit 112 is Decrease.

  At time T3, which is the timing when the data storage amount of the second data storage unit 112 becomes less than the specified amount, the trigger signal is output to the activation control unit 180 by the trigger signal output unit 170, whereby the intermittent operation is performed during the operation period. become.

  When the intermittent operation becomes an operation period, each signal processing by the first signal processing unit 120 is appropriately executed, and the data storage amount of the second data storage unit 112 is rapidly recovered again from the time T4. The specified amount is determined so that the data storage amount of the second data storage unit 112 does not become zero at time T4. In this way, continuous reproduction is realized without the data stored in the second data storage unit 112 being exhausted.

  For data A, the time required for processing by the second processing unit 122 and third processing unit 123 is 50 ms, and for the 200 ms required for processing 10 frames of data A in real time. The first signal processing unit 120 and at least a part of the signal processing control unit 150 are in a power saving state in a period of 75%.

  For data B, the time 40 ms required for processing by the first processing unit 121 and the second processing unit 122 is an operation period, and 200 ms required for processing 10 frames of data B in real time. On the other hand, the first signal processing unit 120 and at least a part of the signal processing control unit 150 are in a power saving state in a period of 80%.

  Such a data processing apparatus 1 according to an embodiment of the present invention supplies at least one of a clock and power to at least a part of the first signal processing unit 120 and the signal processing control unit 150 during a period in which the intermittent operation is stopped. Therefore, it is possible to reduce power consumption required for signal processing of continuous data such as audiovisual data and broadcast signals.

  In the present embodiment, the example in which the data processing apparatus of the present invention is configured by a mobile phone terminal has been described. However, the present invention is not limited to this, and may be configured by a mobile audio visual terminal such as a portable music playback device. Good.

  In the present embodiment, the first data storage unit 110 is described as being configured by a memory card. However, the present invention is not limited to this, and the first data storage unit 110 may be a magnetic tape or a magnetic disk. It is only necessary to be configured by what can store audiovisual data such as a semiconductor memory or a hard disk.

  In the present embodiment, the data stored in the first data storage unit 110 has been described as compressed audio data encoded by AAC or AAC + SBR. However, the present invention is not limited to this. The data stored in the data storage unit 110 may be data obtained by compressing digitized audio data such as MP3 (MPEG Audio Layer-3) data.

  The data stored in the first data storage unit 110 may be moving image data such as MPEG-4 video or still image data such as JPEG (Joint Photographic Experts Group).

  The data stored in the first data storage unit 110 may be ciphertext encrypted by DES (Data Encryption Standard), AES (Advanced Encryption Standard), or the like. In this case, the first signal processing unit 120 is configured to further perform the encryption decryption process.

  In this embodiment, the second signal processing unit 130 is described as performing analog conversion processing. However, the present invention is not limited to this, and the output destination of the second signal processing unit 130 is that of the liquid crystal display device. As described above, when digital data is input, the second signal processing unit 130 may not perform analog conversion processing.

  In the present embodiment, the trigger signal output unit 170 has been described as outputting a trigger signal at a timing when the data storage amount of the second data storage unit 112 becomes less than the specified amount. However, the present invention is not limited to this. Instead, the trigger signal output unit 170 monitors the data storage amount of the second data storage unit 112 by pointer control, and outputs a trigger signal to the activation control unit 180 when the data storage amount becomes less than the specified amount. It may be.

  In the present embodiment, the first signal processing unit 120 is described as performing the decoding process, the sound quality enhancement process, and the SBC encoding process. However, the present invention is not limited to this, and the first signal processing is performed. The unit 120 performs other signal processing applied to the audiovisual data such as sound quality conversion processing, image quality conversion processing, sampling frequency conversion processing, spatial resolution conversion processing, frame rate conversion processing, data format conversion processing, and communication protocol processing. You may do it.

  In addition, the signal processing control unit 150 selects a signal processing for processing the data based on the characteristics of the data to be processed by the first signal processing unit 120, and the selected signal processing is performed for the processing time of each pipeline stage. You may make it allocate to each pipeline stage so that it may become shorter.

  For example, when the second signal processing unit 130 is configured to process data sampled at 44.1 kHz, the signal processing control unit 150 performs processing on data sampled at 48 kHz and encoded with AAC. In other words, the decoding process, the sound quality enhancement process, the sampling frequency conversion process, and the SBC encoding process are allocated to each pipeline stage, and the data sampled at 44.1 kHz and encoded with the AAC is decoded. Sound quality improvement processing and SBC encoding processing may be assigned to each pipeline stage.

  In the present embodiment, the first processing unit 121, the second processing unit 122, and the third processing unit 123 are described as being configured by hardware blocks. However, the present invention is not limited to this. The first processing unit 121, the second processing unit 122, and the third processing unit 123 may be configured by a processor such as a DSP (Digital Signal Processor) or a CPU (Central Processing Unit).

  In the present embodiment, the number of frames processed by the first signal processing unit 120 in one operation period has been described as 10 frames. However, the present invention is not limited to this. However, the transition between the operation period and the stop period has processing overhead required for transition, such as clock control processing and power supply control processing, and as the number of transitions increases, the overhead count increases and the load increases. It is preferable that the number of frames processed in one operation period is large.

  In the present embodiment, the first signal processing unit 120 has been described as performing signal processing on the data divided in units of frames. However, the present invention is not limited to this, and the first signal processing unit 120 You may make it perform signal processing to the data divided | segmented by the sample unit of audio | voice data or the macroblock or pixel unit of image data.

  In FIG. 2, the signal processing control unit 150 switches each signal processing to each pipeline stage by switching the data to be processed from the data A encoded by AAC + SBR to the data B encoded by AAC. Although an example of re-allocation is shown, the signal processing control unit 150 is in a state of ON / OFF or setting of each signal processing via an input device (not shown) when data is processed by the first signal processing unit 120 May be reassigned to the pipeline stage based on the changed state.

  In the present embodiment, the signal processing control unit 150 is described as having the first signal processing unit 120 execute each signal processing in a two-stage pipeline configuration, but the present invention is not limited to this. The control unit 150 may have a short processing period and cause at least one pair of processes adjacent in the sequence to be performed in the same pipeline stage.

  Further, the signal processing control unit 150 may reduce the processing performance of at least one other pipeline stage within a range not exceeding the processing period of the pipeline stage having the longest processing period among the pipeline stages. .

  For example, in the upper part of FIG. 2, the signal processing control unit 150 performs the processing capability of the first processing unit 121 on the data A within a range not exceeding the processing period of the second processing unit 122 and the third processing unit 123. For the data B, the processing capability of the third processing unit 123 may be reduced within a range not exceeding the processing period of the first processing unit 121 and the second processing unit 122.

  In this case, for the data A, the signal processing control unit 150 requests the clock / power control unit 160 to reduce the frequency of the clock supplied to the first processing unit 121, and for the data B Is configured to request the clock / power control unit 160 to reduce the frequency of the clock supplied to the third processing unit 123.

  In FIG. 2, the second processing unit 122 and the third processing unit 123 have been described as performing sequential processing on the data A. However, the processing unit has a pipeline configuration smaller than the pipeline configuration described above. Processing may be performed.

  For example, as shown in FIG. 3, the processing unit of the above-described pipeline configuration is 10 frames, but the second processing unit 122 and the third processing unit 123 perform processing with a pipeline configuration of one frame unit. You may do it.

  Therefore, if the output data for 10 frames of the first processing unit 121 is 40 Kbytes and the output data for 10 frames of the second processing unit 122 is 40 Kbytes, the intermediate data storage unit 111 has a minimum required memory capacity. The output data for 10 frames of the second processing unit 122 becomes 4K bytes while the total is 80K bytes, and the intermediate data storage unit 111 is combined with the 40K bytes of output data for 10 frames of the first processing unit 121. The minimum required memory capacity is 44 Kbytes in total, and the minimum memory capacity required for the intermediate data storage unit 111 is reduced. Particularly, image data that requires a large amount of memory capacity is stored in the intermediate data storage unit 111. The minimum required memory capacity is significantly reduced.

  The data processing apparatus according to the present invention is particularly useful for an audio player and a video player for portable devices driven by a battery, a mobile phone for performing audiovisual processing, and the like.

The block diagram of the data processor in one embodiment of the present invention Timing chart of data processing apparatus according to one embodiment of the present invention The timing diagram of the other aspect of the data processor in one embodiment of this invention Block diagram of a conventional data processing device Timing diagram of another conventional data processing apparatus

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data processing apparatus 110 1st data storage part 111 Intermediate data storage part 112 2nd data storage part 120 1st signal processing part 121 1st processing part 122 2nd processing part 123 3rd processing part 126 Signal processing part 130 Second signal processing unit 136 Output data storage unit 140 Feature extraction unit 146 Output unit 150 Signal processing control unit 156 Control unit 160 Clock / power supply control unit 166 Power supply unit 170 Trigger signal output unit 176 Timer unit 180 Start control unit 196 Broadcast reception Part

Claims (16)

A first data storage unit for storing data;
A first signal processing unit that processes the data in a pipeline configuration in which the number of pipeline stages is smaller than the number of signal processings that process data read from the data storage unit;
A second data storage unit for storing data processed by the first signal processing unit;
A second signal processing unit that performs signal processing by reading out data stored in the second data storage unit in real time;
Based on the characteristics of data processed by the first signal processing unit, the signal processing is allocated to the pipeline stage so as to shorten the processing time of each pipeline stage, and is performed by the first signal processing unit. A signal processing control unit that controls the first signal processing unit to perform an intermittent operation by performing signal processing at a speed faster than the real-time processing;
The first signal processing unit and the signal processing control are limited by restricting supply of at least one of a clock and a power source to at least a part of the first signal processing unit and the signal processing control unit during the stop period of the intermittent operation. A clock / power control unit that controls supply of at least one of a clock and a power source to the first signal processing unit and the signal processing control unit so as to limit power consumption of the unit;
A trigger signal output unit that outputs a trigger signal based on a data storage amount of the second data storage unit;
In response to the trigger signal, the clock / power control unit is requested to cancel the restriction on the supply of at least one of the clock and the power to at least a part of the first signal processing unit and the signal processing control unit, and the intermittent A data processing apparatus comprising: an activation control unit that requests the signal processing control unit to shift to an operation period of operation.   The trigger signal output unit measures the timing when the data storage amount of the first data storage unit becomes less than a prescribed amount, and outputs the trigger signal to the activation control unit at the timing. The data processing apparatus described in 1.   The trigger signal output unit monitors the data storage amount of the second data storage unit, and outputs the trigger signal to the activation control unit when the data storage amount becomes less than a prescribed amount. The data processing apparatus according to claim 1. The first signal processing unit performs at least three signal processes,
4. The signal processing control unit according to claim 1, wherein the signal processing control unit allocates the signal processing to the pipeline stage so that at least two of them are performed in the same pipeline stage. Data processing equipment.   The signal processing control unit assigns the signal processing to the pipeline stage so that the signal processing to be performed in the same pipeline stage is the signal processing continuously performed in the first signal processing unit. The data processing apparatus according to claim 4.   The signal processing control unit controls the first signal processing unit so that signal processing to be performed in the same pipeline stage is performed in a pipeline configuration of processing units smaller than the pipeline configuration. Item 6. The data processing device according to Item 5.   The signal processing control unit reduces processing performance of at least one other pipeline stage within a range not exceeding a processing period of a pipeline stage having the longest processing period among the pipeline stages. The data processing apparatus according to any one of claims 1 to 6.   The signal processing control unit requests the clock / power control unit to reduce a frequency of a clock supplied to a part of the first signal processing unit that processes a pipeline stage that degrades the processing performance. The data processing apparatus according to claim 7.   The signal processing control unit selects a signal processing for processing the data based on the characteristics of the data to be processed by the first signal processing unit, and the processing time of each pipeline stage is shortened for the selected signal processing. The data processing apparatus according to claim 1, wherein the data processing apparatus is assigned to a pipeline stage.   The data processing apparatus according to claim 1, wherein the signal processing by the first signal processing unit includes an encoding process of the data.   The data processing apparatus according to claim 1, wherein the signal processing by the first signal processing unit includes a decoding process of the data.   The data processing apparatus according to claim 1, wherein the signal processing by the first signal processing unit includes a sampling frequency conversion process of the data.   The data processing apparatus according to any one of claims 1 to 9, wherein the signal processing by the first signal processing unit includes a spatial resolution conversion process of the data.   The data processing apparatus according to any one of claims 1 to 9, wherein the signal processing by the first signal processing unit includes a frame rate conversion process of the data.   10. The data processing apparatus according to claim 1, wherein the signal processing by the first signal processing unit includes a format conversion process of the data.   The clock / power control unit includes at least one of a frequency reduction and cutoff of a clock supplied to at least a part of the first signal processing unit and the signal processing control unit, and a power supply voltage reduction and cutoff. 16. The method according to claim 1, wherein supply of at least one of a clock and a power supply to at least a part of the first signal processing unit and the signal processing control unit is limited by performing A data processing device according to any one of the above.

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