JP2003174188A - Optical semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an optical semiconductor device that inhibits the collector voltage dependency of the collector current of a transistor while achieving a structure for reducing the capacity and increasing the speed of a photodiode, and at the same time can inhibit the increase in the saturation voltage of the transistor in the transistor and the photodiode formed on the same substrate, and the provide a manufacturing method of the optical semiconductor device. <P>SOLUTION: In the optical semiconductor device, a photodiode PD and an NPN transistor TR are formed on the same semiconductor substrate. The photodiode PD has a high-concentration P-type layer PDP, an I-type PDI, and a high-concentration N-type layer PDN. The NPN transistor TR comprises a P-type base region B having a high-concentration P-type region B1 physically connected to the high concentration P-type PDP of the photodiode PD as its one region, and an N-type emitter region E that is formed in an N-type collector region and the P-type base region B with the high-concentration N-type region C1 physically connected to the high-concentration N-type layer of the photodiode PD as the partial region. The N-type collector region C has an N-type well region CW reaching the P-type base region B from the high- concentration N-type region C1. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to an optical semiconductor device.

[0002]

2. Description of the Related Art A conventional optical semiconductor device is disclosed in Japanese Patent Laid-Open No. 4-360.
No. 854. This optical semiconductor device is
A photodiode having a PIN structure, a P-type base region whose partial region is a high-concentration P-type region physically connected to the high-concentration P-type layer of the photodiode, and a high-concentration N-type layer of the photodiode are physically formed. An NPN transistor having an N-type collector region and an N-type emitter region formed in a P-type base region of which the connected high-concentration N-type region is a partial region is formed on the same semiconductor substrate. Since the photodiode is connected to the base region of the NPN transistor, the collector current flowing between the collector region and the emitter region of the NPN transistor is controlled or detected by the base current flowing into the base region through the photodiode. This makes it possible to measure the light intensity incident on the photodiode.

[0003]

However, since the I-type layer of the photodiode is interposed between the collector region and the base region of the transistor, the transistor output current is reduced when the I-type layer is completely depleted. It varies with collector voltage dependency. Further, if there is an I-type layer left undepleted, there arises a problem that the saturation voltage of the transistor increases as the collector resistance increases.
Further, there is a method of completely filling the I-type layer of the transistor with the rising of the buried diffusion layer, but in that case, it is very difficult to control the current amplification factor of the transistor by affecting the impurity profile of the P-type base layer. Had a problem. On the other hand, when the impurity concentration of the I-type layer is increased to reduce the collector resistance, the depletion layer of the photodiode does not spread and the junction capacitance increases. In particular, the electric field in the undepleted region is weak and the response speed of the photodiode is low. There was a problem of lowering.

The present invention has been made in view of the above problems, and suppresses the fluctuation of the collector current of a transistor, reduces the saturation voltage of the transistor, and further reduces the capacitance of the photodiode and during running. It is an object of the present invention to provide an optical semiconductor device capable of high-speed response by decreasing the constant and a manufacturing method thereof.

[0005]

In order to solve the above problems, an optical semiconductor device according to the present invention includes a photodiode having a PIN structure and a high concentration P physically connected to a high concentration P-type layer of the photodiode. A P-type base region whose partial region is the type region, and an N-type region whose partial region is a high-concentration N-type region physically connected to the high-concentration N-type layer of the photodiode.
In an optical semiconductor device in which an NPN transistor having an N-type emitter region formed in a P-type base region and a P-type collector region is formed on the same semiconductor substrate, the N-type collector region is formed from a high-concentration N-type region to a P-type. It is characterized by having an N-type well region reaching the base region.

The I-type layer does not mean an intrinsic semiconductor in a narrow sense, but a semiconductor having a relatively low impurity concentration of less than 1 × 10 ¹⁵ / cm ³ . It may be an N-type impurity or a P-type impurity.

A high concentration means an impurity concentration of 1 × 10 ¹⁷
/ Cm ³ or more.

When such an I-type layer is interposed between the high-concentration N-type region of the N-type collector region and the P-type base region, the saturation voltage of the transistor increases as described above. In the device of the present invention, the N-type collector region has an N-type well region reaching the P-type base region from the high-concentration N-type region. The average N-type impurity concentration in this N-type well region is preferably 1 × 10 ¹⁵ / cm ³ or more. That is, the N-type well region has a higher impurity concentration than the I-type layer.

If a reverse bias voltage that completely depletes the I-type layer interposed in the photodiode is applied, the same reverse bias is applied between the P-type base region and the N-type collector region of the transistor. However, even in this case, the N-type well region is not depleted in the entire region. When the reverse bias voltage, that is, the collector voltage is further increased,
The depletion layer in the N-well region is gradually expanded to make the fluctuation of the base potential small and suppress the fluctuation of the current amplification factor to provide a stable collector current, that is, an output current.

Further, since the collector current flows in the N-type well region in which the impurity concentration is increased and the resistivity is decreased, the increase in the transistor saturation voltage is suppressed. Therefore, the collector current does not decrease particularly in low voltage operation. Further, the high resistance region of the I layer interposed in the photodiode is
Since the introduction of the N-well layer eliminates the influence of the saturation voltage and the collector modulation on the transistor, the resistance layer can be set to a large resistance layer close to the original intrinsic semiconductor, thereby lowering the voltage operation and reducing the capacitance of the photodiode. High speed can be easily realized.

It is preferable that the N-type emitter region, the P-type base region and the N-type collector region have respective electrodes on the same surface side of the semiconductor substrate. In this case, the electrodes can be easily provided from the same surface side. Lead wires can be attached.

The method of manufacturing such an optical semiconductor device is
A step of epitaxially growing an I-type layer on the surface of a semiconductor substrate having a high-concentration N-type layer on at least the surface side, and adding an N-type impurity from the surface side of the I-type layer into an N-type well region formation planned region Forming a type well region, forming a P type main base region in the N type well region, forming an N type emitter region in the P type main base region, an I type layer and a P type Forming a high-concentration P-type layer on the surface side of the I-type layer and the P-type main base region by adding a P-type impurity from the surface side of the main type base region of the N-type well region. The heat treatment is performed until the added N-type impurity reaches the high-concentration N-type layer. According to this manufacturing method, since the N-type well region is formed by adding the N-type impurity from the surface side, this functions as a part of the collector region. In this case, the above-mentioned effect is obtained. In addition, the impurity concentration and distribution of the collector region can be controlled with high precision as compared with the case where this is the buried layer, and therefore,
The characteristics of the transistor can be improved.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION An optical semiconductor device according to an embodiment will be described below. The same elements will be denoted by the same reference symbols, without redundant description.

FIG. 1 is an explanatory view showing the outline of an optical semiconductor device. This figure shows the connection of each element, and if the optical semiconductor device has such a connection relationship, optical semiconductor devices of various shapes can be manufactured. FIG. 2 is a circuit diagram of the optical semiconductor device shown in FIG.

This optical semiconductor device comprises a photodiode PD.
And the NPN transistor TR are formed on the same semiconductor substrate. It should be noted that each of the elements in the figure is made of a semiconductor, and the description of the protective film, the passivation film, etc. is omitted.

The photodiode PD is a high concentration P-type layer PD.
_P , an I-type layer PD _I and a high concentration N-type layer PD _N are provided,
It has a PIN structure. The high-concentration P-type layer PD _P and the high-concentration N-type layer PD _N form the anode and cathode of the photodiode, respectively. The I-type layer PD _I does not mean an intrinsic semiconductor in a narrow sense,
A semiconductor having an impurity concentration of less than 1 × 10 ¹⁵ / cm ³ is meant. It is assumed that the I-type layer PD _I is doped with some N-type impurities or P-type impurities. Further, in the description, high concentration means that the impurity concentration is 1
It means x10 ¹⁷ / cm ³ or more.

The NPN transistor TR includes a P-type base region B whose partial region is a high-concentration P-type region B1 physically connected to the high-concentration P-type layer PD _P of the photodiode PD, and a high concentration N of the photodiode PD. It has an N-type collector region having a high-concentration N-type region C1 physically connected to the mold layer as a partial region and an N-type emitter region E formed in a P-type base region B.

Here, the N-type collector region C has an N-type well region CW which reaches the P-type base region B from the high-concentration N-type region C1. Average N of this N-type well region CW
The type impurity concentration is preferably 1 × 10 ¹⁵ / cm ³ or more. That is, the N-type well region CW is the I-type layer PD.
Higher impurity concentration than _I.

In order to completely deplete the I-type layer PD _I , if a reverse bias is applied to the photodiode PD, the P-type base region B and the N-type collector region C of the transistor TR will be described.
Although a reverse bias is applied between and, the N-type well region CW is not depleted in the entire region even when the entire I-type layer PD _I is depleted in this case.

That is, the I-type layer PD _I is not interposed between the P-type base region B and the N-type collector region C. Therefore, as the static characteristic of the transistor TR, the resistance due to such an I-type layer PD _I decreases, and the collector current increases.

When the N-type well region CW is the I-type layer PD _I , the collector and base regions of the collector and base regions are changed by the resistance change and the substrate potential change due to the carriers generated by the incidence of light on the I-type layer PD _I. The electric potential is affected. Even when the potential change is not considered, the collector resistance Rc changes.

In this device, since the N-type well region CW is not the I-type layer PD _I , the potentials of the collector region C and the base region B and the collector resistance Rc are stabilized, and the variation of the collector current Ic of the transistor TR is suppressed. can do. The collector current Ic is a current amplification factor (h _fe ) times the base current Ib, but the base current Ib is a current flowing through the photodiode PD.

Further, the N-type emitter region E, the P-type base region B and the N-type collector region C are provided with respective electrodes (not shown) on the same surface side of the semiconductor substrate. In this case, from the same surface side. Lead wires can be attached to the electrodes.

Next, an example of the above-mentioned optical semiconductor device will be described together with a manufacturing method.

FIG. 3 is a perspective view of the optical semiconductor device, in which the optical semiconductor device is partially cut away. The conductivity type, impurity concentration, and thickness of each semiconductor element forming the optical semiconductor device are as follows. The semiconductor material is Si.

[Table 1]

[Table 2] The N-type well region CW is an inner N-type well region CW1 located inside the outer N-type well region CW1 with an I-type layer PD _I interposed in a plane perpendicular to the substrate. The well region CW2 is formed. Outside N
On the surface side of the type well region CW1, a high concentration P type region IS _P functioning as an isolation or a channel stopper for electrically isolating an adjacent element is formed in an annular shape. In addition, the N-type emitter regions E and P on the substrate surface side
High-concentration P-type region forming part of the surface side of the mold base region B
An emitter electrode, a base electrode, and a collector electrode are provided on the high-concentration N-type region C2 forming part of the surface side of B1 and the N-type collector region C, respectively.

This optical semiconductor device is manufactured by sequentially performing the following steps. Epitaxial growth process

A high-concentration N-type layer (P
D _N : A semiconductor substrate having a high concentration N type region C1) is prepared. In this example, the semiconductor substrate itself is a high-concentration N-type substrate (0.01 Ω · cm). An I-type layer PD _I is epitaxially grown on the surface of this semiconductor substrate. The epitaxial growth layer is required to have a high resistance under the assumption of low voltage operation, and the thicker the epi thickness is, the higher the resistance of the epitaxial growth layer is set. For example, when the I layer has a thickness of 15 μm, the resistivity of the epitaxial layer is 50
High resistance of 0 Ω · cm or more. Or 20μ for I layer
When the thickness is m or more, the resistance is as high as 700 Ωcm or more. In this way, the I layer becomes a depletion layer completely at a low voltage, and the photodiode can have a low capacitance and a high speed response. N-type well region formation process

A mask in which the N-type well region formation planned region is exposed is formed on the surface of the I-type layer PD _I. This mask is formed by photoresist. In the masked state, an N-type impurity is added from the surface side of the I-type layer PD _I into the N-type well region formation planned region to form the N-type well region CW (CW
1, CW2) is formed. Examples of the impurity addition method include a diffusion method and an ion implantation method. N-type well region CW
Is a high-concentration N-type layer C1 (P
It is heat treated until it reaches D _N ). Main base region formation process

A P-type main base region B2 is formed in the N-type well region CW. I type layer PD _I and N type well region C
A mask in which the main base region formation planned region is exposed on the surface of W is prepared. This mask is formed by photoresist. In the masked state, a P-type impurity is added from the surface side of the I-type layer PD _I and the N-type well region CW into the main base region formation planned region to form the main base region B2. Examples of the impurity addition method include a diffusion method and an ion implantation method. Emitter region formation process

An N type emitter region is formed in the main base region B2. A mask in which an emitter region formation planned region is exposed is formed on the surfaces of the I-type layer PD _I , the N-type well region CW and the main base region B2. This mask is formed by photoresist. I-type layer PD with mask
_An emitter region E is formed by adding an N-type impurity from the surface side of the _I , N-type well region CW and the main base region B2 into the region where the emitter region is to be formed. As a method of adding impurities,
A diffusion method and an ion implantation method can be used. High-concentration P-type layer PD _P formation process

By adding P-type impurities from the surface side of the I-type layer PDI, the N-type well region CW, the main base region B2 and the N-type emitter region E, the high concentration P-type is added to the surface side of the region outside the emitter. Form the layer B1 (PD _P ). I
The high concentration P-type layer PD _P is formed on the surfaces of the type layer PD _I , the N-type well region CW, the main base region B2 and the N-type emitter region E.
A mask in which a region to be formed is exposed is manufactured. This mask is formed by photoresist. In the masked state, P-type impurities are added from the surface side to the high-concentration P-type layer PD _P formation planned region to form the high-concentration P-type layer B1 (PD _P ).
To form. Examples of the impurity addition method include a diffusion method and an ion implantation method. Finally, the optical semiconductor device is completed by providing isolation, passivation, and metal electrodes. According to the present manufacturing method, since the N-type well region CW is formed by adding the N-type impurity from the surface side, it functions as a part of the collector region. In addition to the effect, the impurity concentration and distribution in the collector region can be controlled with higher accuracy than in the case where the collector region is a buried layer, and therefore the characteristics of the transistor TR can be improved.

Next, the advantages of the above-described optical semiconductor device will be described using a comparative example. The optical semiconductor device according to the comparative example has an N-type buried layer BL in place of the N-type well region and the high-concentration N-type layer C1.

FIG. 4 is a partial vertical sectional view of the optical semiconductor device shown in FIG. 3, and FIG. 5 is a graph showing an impurity concentration distribution on the depth direction measurement line t shown in FIG. Similarly, FIG. 6 is a longitudinal sectional view of an optical semiconductor device according to a comparative example.
7 is a graph showing an impurity concentration distribution on the depth direction measurement line t shown in FIG. The shaded area indicates the depletion layer.

As shown in the above graph, the impurity concentration of the N-type well region CW according to the embodiment is higher than that of the comparative example, and the high-concentration N-type layer C1 (from the main base region B2 to the substrate side). PD _N ) has been reached. Therefore, in the photodiode portion, even if the PDI region is entirely depleted, the depletion layer between the base and the collector formed in the N well region is formed in an extremely narrow range, and its width is slightly changed according to the fluctuation of the collector voltage. Change. Therefore, the base potential becomes constant without depending on the fluctuation of the collector voltage. Further, since the N well region has a higher impurity concentration than the comparative example, the collector resistance becomes low.

In the comparative example, since the resistance Rc due to the I-type layer PD _I is large, the collector resistance is large and the transistor saturation voltage is large when the photodiode PD is partially depleted. Further, when the depletion layer reaches the BL region in order to eliminate the collector resistance Rc, the depletion layer cannot change any more, the base potential rises as the collector voltage increases, and the current amplification factor increases and the collector increases. The current fluctuates. Further, assuming that PDI is completely depleted, the BL formed due to the decrease in collector resistance.
Even if there is no layer, the collector resistance Rc of the transistor becomes small and the existence of the BL layer becomes meaningless.

In the embodiment, the photodiode PD
Can be fully depleted at a low voltage, and the depletion layer on the transistor TR side is 2 to 3 μm from the junction with the base in the N-type well region.
Since there is only a depth of m, there is an advantage that the collector voltage dependence of the transistor is small. Further, since the PDI of the photodiode portion is completely depleted, the average drift velocity of electrons becomes higher than that of the comparative example.
High-speed response is possible.

Further, in the optical semiconductor device of the embodiment, the collector junction capacitance also becomes small. The decrease in resistance reduces the saturation voltage of the transistor, and the output does not decrease even with a large current, so the dynamic range is expanded. Furthermore, there is an advantage that the dependency of the voltage between the collector and the emitter is reduced because it is less likely to receive the Early effect.

Further, it is preferable that the emitter electrode provided in the emitter region of the transistor TR has a stripe shape and the collector electrode has a ring shape surrounding the light incident region of the emitter electrode and the photodiode PD. The narrower the width of this stripe, the higher the speed. Since the collector junction capacitance is reduced in the structure of this example, it is striped, that is, in the thickness direction of the substrate rather than in the direction of the current flowing through the high-concentration N-type layer in the emitter electrode (emitter region E). By increasing the length of the electrodes in the vertical direction, higher speed can be achieved.

[0039]

As described above, according to the optical semiconductor device of the present invention, in the transistor and the photodiode formed on the same substrate, while the collector voltage is reduced while the capacitance and speed of the photodiode can be reduced. It is possible to suppress the dependency and suppress an increase in the saturation voltage of the transistor. Moreover, according to this manufacturing method, the characteristics of the transistor can be further improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an outline of an optical semiconductor device.

FIG. 2 is a circuit diagram of the optical semiconductor device shown in FIG.

FIG. 3 is a perspective view of an optical semiconductor device in which the optical semiconductor device is partially broken away.

4 is a partial vertical cross-sectional view of the optical semiconductor device shown in FIG.

5 is a graph showing an impurity concentration distribution on a depth direction measurement line t shown in FIG.

FIG. 6 is a vertical cross-sectional view of an optical semiconductor device according to a comparative example.

7 is a graph showing an impurity concentration distribution on the depth direction measurement line t shown in FIG.

[Explanation of symbols]

E ... N-type emitter region, B ... Base region, C ... Collector
Region, B1 ... High-concentration P-type layer, B2 ... Main base region, C1
... High-concentration N-type layer, CW ... N-type well region, IS _P... P type
Area, PD ... Photodiode, PD_I… I-type layer, PD_N…
High concentration N-type layer, PD_P... High-concentration P-type layer, Rc ... Resistance, t
… Direction measurement line, TR… Transistor.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hitoshi Inoue             1 Hamamatsuho, 1126 Nomachi, Hamamatsu City, Shizuoka Prefecture             Tonics Co., Ltd. F-term (reference) 4M118 AA01 CA05 CA09                 5F049 MA04 MB03 NA03 PA03 PA09                       QA20 RA06

Claims (4)

[Claims] 1. A photodiode having a PIN structure,
A P-type base region having a high-concentration P-type region physically connected to the high-concentration P-type layer of the photodiode as a partial region, and a high-concentration N physically connected to the high-concentration N-type layer of the photodiode. An optical semiconductor device comprising an N-type collector region having a type region as a partial region and an NPN transistor having an N-type emitter region formed in the P-type base region on the same semiconductor substrate. The type collector region is formed from the high concentration N type region to the P type.
An optical semiconductor device comprising an N-type well region reaching a type base region. 2. The optical semiconductor device according to claim 1, wherein the average N-type impurity concentration of the N-type well region is 1 × 10 ¹⁵ / cm ³ or more. 3. The optical semiconductor according to claim 1, wherein the N-type emitter region, the P-type base region and the N-type collector region have respective electrodes on the same surface side of the semiconductor substrate. apparatus. 4. A step of epitaxially growing an I-type layer on the surface of a semiconductor substrate having a high-concentration N-type layer on at least the surface side, and N from the surface side of the I-type layer in an N-type well region formation scheduled region. Forming an N-type well region by adding a type impurity, forming a P-type main base region in the N-type well region, and forming an N-type emitter region in the P-type main base region From the surface side of the I-type layer and the P-type main base region
The I-type layer and the P-type layer by adding a type impurity.
Forming a high-concentration P-type layer on the surface side of the main base region of the mold, wherein the N-type well region is heat-treated until the added N-type impurity reaches the high-concentration N-type layer. A method for manufacturing an optical semiconductor device, comprising: