JP2003174117A - Electronic component assembling method and electronic component - Google Patents
Electronic component assembling method and electronic componentInfo
- Publication number
- JP2003174117A JP2003174117A JP2001372737A JP2001372737A JP2003174117A JP 2003174117 A JP2003174117 A JP 2003174117A JP 2001372737 A JP2001372737 A JP 2001372737A JP 2001372737 A JP2001372737 A JP 2001372737A JP 2003174117 A JP2003174117 A JP 2003174117A
- Authority
- JP
- Japan
- Prior art keywords
- circuit forming
- electronic component
- forming portion
- assembling method
- sealing material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
- H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
- H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/251—Materials
- H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】
【課題】 製品品質の安定化、及び生産タクトの向上を
含めた実装コストの低減が可能な、電子部品の組立方法
及び電子部品を提供する。
【解決手段】 回路形成部113を封止材114にて覆
った後、バンプ112が露出するまで上記封止材を除去
するようにしたことにより、上記回路形成部に損傷を与
えることがなく、製品品質の安定化を図ることができ
る。又、従来のように特殊形状のパッケージは不要であ
り蓋をするという工程も必要ない。よって、生産タクト
の向上を含めた実装コストの低減が可能である。
To provide an electronic component assembling method and an electronic component capable of reducing the mounting cost including stabilization of product quality and improvement of production tact. After the circuit forming portion 113 is covered with a sealing material 114, the sealing material is removed until a bump 112 is exposed, so that the circuit forming portion is not damaged. Product quality can be stabilized. Further, a specially shaped package is not required as in the prior art, and a process of covering is not necessary. Therefore, it is possible to reduce the mounting cost including improvement of production tact.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、電子部品の組立方
法、及び該組立方法により組み立てられた電子部品に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic component assembling method and an electronic component assembled by the assembling method.
【0002】[0002]
【従来の技術】近年、電子部品の生産量は増加し続け、
それに伴い多種、多様なパッケージ形態が提案されてい
る。例えばCSP(chip sides package)、C4(Cont
rolledCollapse Chip Connection)やBGA(Ball Gri
d Allay)、QFPなどの形態がある。特に小型、軽量
を実現する電子部品のCSPは重要なものになると考え
られている。従来のICチップなどの半導体素子は、電
極に金バンプ、半田バンプなどを形成して実装基板に実
装した後、封止材で固定するものであった。この一例と
して、図22を参照して説明すると、半導体素子1の電
極にスタッドバンプボンディングなどにより、例えば金
にてなるバンプ3を形成する。そしてセラミックや樹脂
材等からなる実装基板2上の基板電極4上に超音波振動
を加えながらバンプ3を接合する。その後、バンプ3と
基板電極4との接合箇所及び半導体素子1の周辺部分を
含めて絶縁樹脂などの封止材5により封止を行う。2. Description of the Related Art In recent years, the production volume of electronic parts has continued to increase,
Along with this, various types of package forms have been proposed. For example, CSP (chip sides package), C4 (Cont
rolledCollapse Chip Connection) and BGA (Ball Gri)
d Allay), QFP, etc. In particular, it is considered that CSP of electronic parts that realizes small size and light weight will be important. In a conventional semiconductor element such as an IC chip, gold bumps, solder bumps, etc. are formed on electrodes, mounted on a mounting board, and then fixed with a sealing material. As an example of this, referring to FIG. 22, the bumps 3 made of gold, for example, are formed on the electrodes of the semiconductor element 1 by stud bump bonding or the like. Then, the bumps 3 are bonded onto the substrate electrodes 4 on the mounting substrate 2 made of ceramic or resin material while applying ultrasonic vibration. After that, sealing is performed with a sealing material 5 such as an insulating resin including a bonding portion between the bump 3 and the substrate electrode 4 and a peripheral portion of the semiconductor element 1.
【0003】又、SAW(surface acoustic wave)フ
ィルターなどの半導体素子は回路形成面に異物が介在し
てはならないため、図23に示すようなキャビティータ
イプのセラミック基板7にSAWフィルタ6を、バンプ
3を介してフリップチップボンディング工法で導通させ
たり、図24に示すように、ダイボンド材11にてSA
Wフィルタ6を固定し金ワイヤ8を用いてワイヤボンデ
ィング工法にて導通させる。その後、両者とも、セラミ
ック基板7の上部に、ガラス材又は半田10を用いて金
属プレート9の蓋を施し、上記キャビティーを密閉する
形態があった。Further, since a semiconductor element such as a SAW (surface acoustic wave) filter must have no foreign matter on the circuit forming surface, the SAW filter 6 is bumped onto the cavity type ceramic substrate 7 as shown in FIG. 24 is conducted by a flip chip bonding method, or as shown in FIG.
The W filter 6 is fixed, and the gold wire 8 is used to conduct electricity by the wire bonding method. After that, both of them had a mode in which the metal plate 9 was covered with the glass material or the solder 10 on the upper part of the ceramic substrate 7 to seal the cavity.
【0004】[0004]
【発明が解決しようとする課題】しかしながら、上述の
従来の方法では、上記基板電極4上に超音波振動を加え
ながらバンプ3を接合するとき、バンプ3と半導体素子
1の電極との接合箇所付近に応力が集中し、半導体素子
1の回路形成面にダメージを与える場合が考えられる。
又、上記キャビティーに収納する場合には、パッケージ
の形状が特殊となり、蓋をするという工程が必要とな
る。よっていずれの場合も、製品品質の安定化、実装コ
ストの低下、及び生産タクトの向上を図ることが困難で
あるという問題がある。本発明は、このような問題点を
解決するためになされたもので、製品品質の安定化、及
び生産タクトの向上を含めた実装コストの低減が可能
な、電子部品の組立方法、及び該組立方法により組み立
てられた電子部品を提供することを目的とする。However, in the above-mentioned conventional method, when the bumps 3 are bonded on the substrate electrode 4 while applying ultrasonic vibration, the vicinity of the bonding portion between the bump 3 and the electrode of the semiconductor element 1 is considered. It is conceivable that stress concentrates on the surface of the semiconductor element 1 and damages the circuit formation surface of the semiconductor element 1.
Further, in the case of storing in the above-mentioned cavity, the shape of the package becomes special and a step of covering the lid is required. Therefore, in either case, it is difficult to stabilize the product quality, reduce the mounting cost, and improve the production tact. The present invention has been made to solve the above problems, and an electronic component assembling method capable of stabilizing the product quality and reducing the mounting cost including the improvement of the production tact, and the assembling method. An object is to provide an electronic component assembled by the method.
【0005】[0005]
【課題を解決するための手段】本発明の第1態様の電子
部品組立方法は、回路形成部を形成した半導体素子の回
路形成面に形成された突起電極を覆い上記回路形成面に
封止材を設けた後、上記回路形成部を保護した状態で上
記突起電極が上記封止材に露出するまで上記封止材を除
去することを特徴とする。According to a first aspect of the present invention, there is provided an electronic component assembling method, which covers a protruding electrode formed on a circuit forming surface of a semiconductor element having a circuit forming portion and covers the circuit forming surface with a sealing material. Is provided, the sealing material is removed until the protruding electrodes are exposed to the sealing material while the circuit forming portion is protected.
【0006】又、上記封止材の除去後、上記封止材に露
出した上記突起電極の露出面に上記突起電極と導通する
導電性材料を設けることもできる。Further, after removing the encapsulating material, a conductive material that is electrically connected to the protruding electrode may be provided on the exposed surface of the protruding electrode exposed on the encapsulating material.
【0007】又、上記封止材を設ける前に、上記回路形
成部に接触して該回路形成部を覆い保護する保護材を設
けることもできる。Before the sealing material is provided, a protective material may be provided to contact the circuit forming portion to cover and protect the circuit forming portion.
【0008】本発明の第2態様の電子部品組立方法は、
半導体素子の回路形成部を形成した回路形成面上に、上
記回路形成部に接触して該回路形成部を覆い保護する保
護材を設けた後、該保護材を密閉する密閉部材を設ける
ことを特徴とする。The electronic component assembling method according to the second aspect of the present invention is
After providing a protective material on the circuit formation surface on which the circuit formation portion of the semiconductor element is formed so as to contact the circuit formation portion to cover and protect the circuit formation portion, a sealing member for sealing the protection material may be provided. Characterize.
【0009】上記第2態様の組立方法において、上記密
閉部材を設けた後、上記回路形成面上に突起電極を形成
することもできる。In the assembly method of the second aspect, it is possible to form the protruding electrodes on the circuit forming surface after providing the sealing member.
【0010】上記第1態様及び第2態様の組立方法にお
いて、上記半導体素子は、上記突起電極と電気的に接続
される実装基板上に実装するようにしてもよい。In the assembling methods of the first aspect and the second aspect, the semiconductor element may be mounted on a mounting board electrically connected to the protruding electrode.
【0011】上記第1態様の組立方法において、上記回
路形成部は、半導体ウエハ上に格子状に形成され、上記
封止材の除去後、各回路形成部に切り分けられ、上記突
起電極と電気的に接続される実装基板上に実装するよう
にしてもよい。In the assembly method of the first aspect, the circuit forming portion is formed in a grid pattern on a semiconductor wafer, and after the encapsulating material is removed, the circuit forming portion is cut into each circuit forming portion and electrically connected to the protruding electrodes. You may make it mount on the mounting board connected to.
【0012】上記第2態様の組立方法において、上記回
路形成部は、半導体ウエハ上に格子状に形成され、上記
回路形成面上への突起電極の形成後、各回路形成部に切
り分けられ、実装基板上に実装するようにしてもよい。In the assembling method according to the second aspect, the circuit forming portions are formed in a grid pattern on a semiconductor wafer, and after the protruding electrodes are formed on the circuit forming surface, the circuit forming portions are cut into each circuit forming portion and mounted. It may be mounted on a substrate.
【0013】又、本発明の第3態様の電子部品は、上記
第1態様及び第2態様の電子部品組立方法にて組み立て
られたことを特徴とする。An electronic component according to a third aspect of the present invention is characterized in that it is assembled by the electronic component assembling method according to the first and second aspects.
【0014】[0014]
【発明の実施の形態】本発明の実施形態である電子部品
組立方法、及び該組立方法にて組み立てられた電子部品
について、図を参照しながら以下に説明する。尚、各図
において、同じ構成部分に付いては同じ符号を付してい
る。
第1実施形態;上記電子部品組立方法の第1実施形態に
ついて説明する。まず、図6に示すように本実施形態で
はスタッドバンプボンディング装置のキャピラリー20
1の導線通路201aを通して突出した金線などの金属
線202の先端箇所を放電溶融させ、金属ボール202
aを形成する。そして半導体素子111の回路形成面1
11aに形成されている回路形成部113に備わる電極
上に対して上記金属ボール202aを押圧するとともに
超音波振動を作用させて金属ボール202aを上記電極
に接合する。該接合後、キャピラリー201を上昇さ
せ、キャピラリー201の横移動、下降、及び上昇の各
動作を行なうことで、上記金属ボール202aにつなが
っている金属線202を破断し、図7に示すように上記
電極上に、突起電極に相当するバンプ112を形成す
る。尚、バンプ112の材質は、金に限らず、半田でも
よい。尚、上記半導体素子111は、Si半導体、化合
物半導体、セラミック、樹脂、又はガラス等の基板上に
形成された回路を備える。BEST MODE FOR CARRYING OUT THE INVENTION An electronic component assembling method according to an embodiment of the present invention and an electronic component assembled by the assembling method will be described below with reference to the drawings. In each figure, the same components are designated by the same reference numerals. First Embodiment: A first embodiment of the electronic component assembling method will be described. First, as shown in FIG. 6, in this embodiment, the capillary 20 of the stud bump bonding apparatus is used.
No. 1 metal wire 202 such as a gold wire protruding through the first wire passage 201a is melted by electric discharge,
a is formed. The circuit forming surface 1 of the semiconductor element 111
The metal ball 202a is pressed against the electrode provided in the circuit forming portion 113 formed on the electrode 11a, and ultrasonic vibration is applied to bond the metal ball 202a to the electrode. After the joining, the capillary 201 is moved up, and the capillary 201 is laterally moved, moved down, and moved up to break the metal wire 202 connected to the metal ball 202a, and as shown in FIG. Bumps 112 corresponding to the protruding electrodes are formed on the electrodes. The material of the bump 112 is not limited to gold, but may be solder. The semiconductor element 111 includes a circuit formed on a substrate such as Si semiconductor, compound semiconductor, ceramic, resin, or glass.
【0015】次のステップでは、図8に示すように、バ
ンプ112を形成した半導体素子111の回路形成面1
11a上に、本実施形態では絶縁樹脂にてなる封止材1
14を供給し、バンプ112を覆うように上記回路形成
面111aを封止材114にて封止する。具体的には図
示するように、封止材114は、塗布機115のノズル
116から供給され、回路形成面111aとバンプ11
2との全体を覆い、封止材114の厚みはバンプ112
の高さを超える値であり、例えば、バンプ高さの2倍、
又はバンプ高さ+設定値とすることができる。又、封止
材114は、ガラス系、アクリル系、エポキシ系、又は
ポリイミド系の樹脂であり、熱硬化性、熱可塑性、及び
光硬化性のものである。供給後、封止材114は硬化さ
れる。In the next step, as shown in FIG. 8, the circuit forming surface 1 of the semiconductor element 111 on which the bumps 112 are formed is formed.
The encapsulant 1 made of an insulating resin in this embodiment is provided on the surface 11a.
14 is supplied, and the circuit forming surface 111a is sealed with a sealing material 114 so as to cover the bumps 112. Specifically, as shown in the figure, the sealing material 114 is supplied from the nozzle 116 of the coating machine 115, and the circuit forming surface 111a and the bumps 11 are formed.
2 and the entire thickness of the encapsulant 114 is bump 112.
Is greater than the height of, for example, twice the bump height,
Alternatively, the bump height + the set value can be set. The encapsulant 114 is a glass-based, acrylic-based, epoxy-based, or polyimide-based resin, and is thermosetting, thermoplastic, and photocurable. After the supply, the sealing material 114 is hardened.
【0016】封止材114を上述のように塗布方法で供
給することで、上記回路形成面111aを保護できると
伴に、塗布後、硬化した封止材114を研磨してバンプ
112の露出面を平滑化することができる。尚、本実施
形態では封止材114を上述のように塗布方法にて供給
したが、印刷方法、スピンコート、又は転写方法により
供給してもよい。尚、一般的には、粘度の高い封止材を
供給するときには、施工時間の短縮化が可能なことか
ら、印刷方法が好ましい。一方、粘度の低い封止材を供
給するときには、その膜厚を安定させるため、スピンコ
ート方法が好ましい。By supplying the encapsulating material 114 by the coating method as described above, the circuit forming surface 111a can be protected, and after the application, the hardened encapsulating material 114 is polished to expose the exposed surface of the bump 112. Can be smoothed. Although the sealing material 114 is supplied by the coating method as described above in the present embodiment, it may be supplied by a printing method, spin coating, or a transfer method. In addition, in general, when supplying a sealing material having a high viscosity, the printing method is preferable because the construction time can be shortened. On the other hand, when a sealing material having a low viscosity is supplied, the spin coating method is preferable in order to stabilize the film thickness.
【0017】次のステップでは、図1に示すように、半
導体素子111の回路形成面111aを封止材114に
て保護した状態で、バンプ112が封止材114に露出
するまで封止材114及びバンプ112を除去する。本
実施形態では、図示するように駆動部205にて駆動さ
れる研削工具206を用いて封止材114及びバンプ1
12を研削する。封止材114の材質により、封止材1
14に対する上記研削工具206の押圧力、回転数、及
び削り深さが調整される。尚、封止材114及びバンプ
112の除去方法は、上記研削に限らず研磨により除去
するようにしてもよい。上記研削及び研磨動作によれ
ば、除去後の封止材114の表面とバンプ112の露出
面112aとを同一面とすることができる。又、バンプ
112の周囲を封止材114にて包囲することができ、
実装基板の電極とバンプ112との接合時にバンプ11
2に作用する力を封止材114へ分散させることもでき
る。又、上記研削によれば、完成される電子部品の厚み
を均一にすることができる。又、上記研磨する場合、上
述の工程をウエハ状の基板に対して行ったときには、一
括的に処理できるのでコスト低減を図ることができる。In the next step, as shown in FIG. 1, with the circuit forming surface 111a of the semiconductor element 111 protected by the encapsulant 114, the encapsulant 114 is exposed until the bumps 112 are exposed to the encapsulant 114. And the bump 112 is removed. In this embodiment, the sealing material 114 and the bumps 1 are formed by using the grinding tool 206 driven by the driving unit 205 as shown in the figure.
Grind 12 Depending on the material of the sealing material 114, the sealing material 1
The pressing force of the grinding tool 206 against 14, the number of revolutions, and the cutting depth are adjusted. The method for removing the encapsulating material 114 and the bumps 112 is not limited to the above grinding, but may be removed by polishing. According to the above grinding and polishing operation, the surface of the sealing material 114 after removal and the exposed surface 112a of the bump 112 can be made flush. Further, the periphery of the bump 112 can be surrounded by the sealing material 114,
When the electrodes on the mounting board and the bumps 112 are joined, the bumps 11
It is also possible to disperse the force acting on 2 to the sealing material 114. Further, according to the above grinding, the thickness of the completed electronic component can be made uniform. Further, in the case of the above-mentioned polishing, when the above-mentioned steps are performed on the wafer-shaped substrate, it is possible to collectively process, so that the cost can be reduced.
【0018】又、上記研削工具206にて研削されたバ
ンプ112の高さは、バンプ112の横断面積が最も大
きい、つまり封止材114から露出するバンプ112の
露出面112aの面積が最も大きくなる高さが好まし
い。具体的には、図10に示すように、バンプ112の
形状において、一般的に最大周囲を有する、バンプ11
2の台座部112bにおける上記回路形成面111aか
らの高さhの1/2の高さが好ましい。このようにして
図9に示すように、半導体素子111のバンプ112の
一部が露出した状態で、半導体素子111の回路形成部
113が封止材114にて覆われている電子部品161
が形成される。該電子部品161の一例として、LED
(発光ダイオード)が挙げられる。尚、上述のような、
回路形成部113に直接、封止材114が接触する方法
は、SAWフィルタには適用できない。The bump 112 ground by the grinding tool 206 has the largest cross-sectional area of the bump 112, that is, the largest exposed surface 112a of the bump 112 exposed from the encapsulant 114. Height is preferred. Specifically, as shown in FIG. 10, in the shape of the bump 112, the bump 11 that generally has the maximum circumference is used.
It is preferable that the height of the second pedestal portion 112b is half the height h from the circuit forming surface 111a. In this way, as shown in FIG. 9, the electronic component 161 in which the circuit forming portion 113 of the semiconductor element 111 is covered with the encapsulant 114 in a state where a part of the bump 112 of the semiconductor element 111 is exposed.
Is formed. As an example of the electronic component 161, an LED
(Light emitting diode). In addition, as described above,
The method in which the sealing material 114 directly contacts the circuit forming portion 113 cannot be applied to the SAW filter.
【0019】このように本実施形態の電子部品組立方
法、及び該組立方法にて組み立てられる電子部品によれ
ば、回路形成部113が封止材114にて覆われた状態
でバンプ112を露出させていることから、実装基板上
の電極に例えば超音波振動を加えながらバンプ112を
接合する場合であっても、バンプ112と半導体素子1
11の電極との接合箇所付近に応力が集中することはな
く、上記回路形成部113に損傷を与えることはない。
よって、製品品質の安定化を図ることができる。As described above, according to the electronic component assembling method of the present embodiment and the electronic component assembled by the assembling method, the bump 112 is exposed while the circuit forming portion 113 is covered with the sealing material 114. Therefore, even when the bumps 112 are bonded to the electrodes on the mounting substrate while applying ultrasonic vibration, for example, the bumps 112 and the semiconductor element 1
The stress is not concentrated in the vicinity of the junction with the electrode 11 and the circuit forming portion 113 is not damaged.
Therefore, product quality can be stabilized.
【0020】上述のように作製された電子部品161
は、図2に示すように、実装基板180の基板電極18
1上に、半田、導電性ペースト、又は導電性シートを介
してバンプ112の上記露出面を対向させて配置し、上
記基板電極181とバンプ112とを電気的、及び機械
的に接合し、電子部品実装済基板101を作製する。こ
のように電子部品実装済基板101によれば、回路形成
部113が封止材114にて保護された状態にて基板電
極181とバンプ112とを半田等にて接続することか
ら、回路形成部113に損傷を与えることがなく、製品
品質の安定化を図ることができる。さらに、従来のよう
に特殊形状のパッケージは不要であり蓋をするという工
程も必要ない。よって、生産タクトの向上を含めた実装
コストの低減が可能である。The electronic component 161 manufactured as described above
As shown in FIG. 2, the board electrode 18 of the mounting board 180 is
1, the exposed surfaces of the bumps 112 are arranged so as to face each other via solder, a conductive paste, or a conductive sheet, and the substrate electrodes 181 and the bumps 112 are electrically and mechanically bonded to each other. The component-mounted board 101 is manufactured. As described above, according to the electronic component-mounted board 101, the board electrodes 181 and the bumps 112 are connected by solder or the like while the circuit forming portion 113 is protected by the sealing material 114. The product quality can be stabilized without damaging 113. Further, unlike the conventional case, a specially shaped package is not necessary and a step of covering the lid is not necessary. Therefore, it is possible to reduce the mounting cost including the improvement of the production tact.
【0021】図6から図9に示すように、上述の説明
は、一つの半導体素子111に対してバンプ112の形
成、封止材114の供給、及びバンプ112の露出の各
動作を行ったが、図11及び図12に示すように、半導
体ウエハ170上に格子状に形成された各回路形成部1
13に対して上記各動作を行ってもよい。そしてその
後、各回路形成部113に対応して半導体ウエハ170
をダイシングし、それぞれの電子部品161に切り分け
てもよい。このようにウエハ状態で処理することで、一
度に電子部品161を複数生産することができ、又、個
々の半導体素子111にて処理する場合に比べて取り扱
いが容易になる。As shown in FIGS. 6 to 9, in the above description, the operations of forming the bumps 112, supplying the sealing material 114, and exposing the bumps 112 are performed on one semiconductor element 111. As shown in FIGS. 11 and 12, each circuit forming portion 1 formed in a grid pattern on the semiconductor wafer 170.
The above operations may be performed for 13. Then, thereafter, the semiconductor wafer 170 corresponding to each circuit forming unit 113 is formed.
May be diced into individual electronic components 161. By performing processing in the wafer state in this manner, a plurality of electronic components 161 can be produced at one time, and handling becomes easier than in the case where processing is performed on individual semiconductor elements 111.
【0022】第2実施形態;上述の第1実施形態では、
図2に示すように、封止材114に露出したバンプ11
2の露出面112aと、実装基板180の基板電極18
1とが導電性ペースト等を介して接続されるように構成
した。一方、図3に示す電子部品実装済基板102のよ
うに、封止材114に対するバンプ112の露出動作
後、実装基板180への装着前に、少なくとも上記露出
面112aに接触する金属膜117を形成する。該金属
膜117は、導電性材料の一例に相当し例えば銅又は金
にてなる。又、金属膜117の形成方法は、下記のウエ
ハ状態の場合に同じである。Second Embodiment: In the above-mentioned first embodiment,
As shown in FIG. 2, the bumps 11 exposed on the sealing material 114
2 of the exposed surface 112a and the substrate electrode 18 of the mounting substrate 180.
1 and 1 are connected via a conductive paste or the like. On the other hand, like the electronic component mounted substrate 102 shown in FIG. 3, after the bump 112 is exposed to the encapsulant 114 and before being mounted on the mounting substrate 180, a metal film 117 that contacts at least the exposed surface 112a is formed. To do. The metal film 117 corresponds to an example of a conductive material and is made of copper or gold, for example. The method of forming the metal film 117 is the same in the case of the wafer state described below.
【0023】ウエハ状態にて処理する場合には、図13
に示すように、露出面112aが露出している封止材1
14の表面114aの全てに、スパッタ、蒸着、又はメ
ッキにより、金属膜117を形成する。その後、図14
に示すように、電気的接続の必要なバンプ112を導通
させるようにパターニングレジストを塗布し、パターニ
ング後、上記金属膜117の不要部分をドライエッチン
グ又はウエットエッチングにより除去する。次に、パタ
ーニングされた金属膜117上に、例えば印刷方法によ
り半田を供給しリフロー後、電極を形成する。そして、
各回路形成部113に対応して半導体ウエハ170をダ
イシングし、それぞれの電子部品に切り分ける。When processing is performed in a wafer state, FIG.
As shown in FIG. 1, the sealing material 1 in which the exposed surface 112a is exposed
A metal film 117 is formed on all the surfaces 114a of 14 by sputtering, vapor deposition, or plating. After that, FIG.
As shown in, a patterning resist is applied so that the bumps 112 that require electrical connection are made conductive, and after patterning, unnecessary portions of the metal film 117 are removed by dry etching or wet etching. Next, electrodes are formed on the patterned metal film 117 by supplying solder by, for example, a printing method and reflowing. And
The semiconductor wafer 170 is diced so as to correspond to each circuit forming portion 113, and is cut into each electronic component.
【0024】個々の半導体素子111にて作製する場
合、及びウエハ状態から切り分けて作製する場合のいず
れの方法においても、作製された電子部品162は、上
記金属膜117上の半田と基板電極181とを対向させ
て実装基板180に配置され、リフローにより上記金属
膜117上の半田を溶融して、電子部品162と実装基
板180とを導通させ、上記電子部品162を実装基板
180に装着する。In any of the method of manufacturing with individual semiconductor elements 111 and the method of manufacturing by separating from the wafer state, the manufactured electronic component 162 includes the solder on the metal film 117 and the substrate electrode 181. Are placed on the mounting substrate 180 so as to face each other, and the solder on the metal film 117 is melted by reflow to electrically connect the electronic component 162 and the mounting substrate 180, and the electronic component 162 is mounted on the mounting substrate 180.
【0025】上記金属膜117の形成前に、上記露出面
112a及び封止材114への金属膜117の密着性を
向上させるために、露出面112a及び封止材114の
表面にアルゴンプラズマ、又は亜硫酸アンモニウム等の
化学研磨を施した後、上記スパッタ、蒸着、又はメッキ
を実施するのが好ましい。以上説明したステップを有す
る第2実施形態によれば、上述の第1実施形態の場合と
同様の効果を奏することができるとともに、さらに、上
述の第1実施形態に比べて、研磨面への電極の密着性が
向上し、機械的外部応力に対して剥がれ難い、つまり信
頼性の高い構成を実現することができる。Before forming the metal film 117, in order to improve the adhesion of the metal film 117 to the exposed surface 112a and the sealing material 114, argon plasma is applied to the surface of the exposed surface 112a and the sealing material 114, or It is preferable to perform the above-mentioned sputtering, vapor deposition, or plating after chemical polishing with ammonium sulfite or the like. According to the second embodiment having the steps described above, it is possible to obtain the same effect as in the case of the above-described first embodiment, and further, compared with the above-described first embodiment, the electrode on the polishing surface is provided. It is possible to realize a highly reliable structure in which the adhesiveness is improved and peeling is difficult with respect to mechanical external stress.
【0026】第3実施形態;上述の第1実施形態及び第
2実施形態は、上記封止材114のみにて上記回路形成
部113を保護する形態である。本第3実施形態では、
上記回路形成部113に対して専用の保護材を設け、該
保護材をも含めて封止材114にて封止を行う形態を採
る。図4、及び図15〜図17を参照して以下に詳しく
説明する。尚、以下の説明では、ウエハ状態にて処理す
る場合を例に採るが、勿論、個々の半導体素子111毎
に処理を行っても良い。Third Embodiment: The above first and second embodiments are modes in which the circuit forming portion 113 is protected only by the sealing material 114. In the third embodiment,
A dedicated protective material is provided for the circuit forming portion 113, and the sealing material 114 is used to seal the protective material. This will be described in detail below with reference to FIGS. 4 and 15 to 17. In the following description, the case where the wafer is processed is taken as an example, but it goes without saying that the processing may be carried out for each individual semiconductor element 111.
【0027】第1実施形態及び第2実施形態で説明した
ように、半導体ウエハ170の回路形成部113にバン
プ112を形成した後、図15に示すように、回路形成
部113の全体を覆う大きさにてなり、本実施形態では
アクリル樹脂にてなる保護材131を回路形成部113
に載置し密着させて回路形成部113を保護する。又、
アクリル樹脂以外にエポキシ系樹脂が使用可能である。
以後、上述の第1実施形態及び第2実施形態の場合と同
様にして、バンプ112を覆うように、本実施形態では
さらに上記保護材131をも覆い図16に示すように半
導体ウエハ170の回路形成面111aに封止材114
を供給し、その後、図17に示すようにバンプ112の
一部が封止材114から露出するように封止材114を
除去する。尚、このように封止材114及びバンプ11
2の一部を除去する工程が含まれることから、該除去動
作に上記保護材131が干渉しては回路形成部113の
損傷を招く場合も考えられる。又、上述したようにバン
プ112は、上記h/2の高さまで除去される場合があ
ることから、保護材131における回路形成面111a
からの高さは、上記h/2未満とする。As described in the first and second embodiments, after forming the bumps 112 on the circuit forming portion 113 of the semiconductor wafer 170, as shown in FIG. 15, a size that covers the entire circuit forming portion 113. In the present embodiment, the protective material 131 made of acrylic resin is added to the circuit forming portion 113.
The circuit forming portion 113 is protected by being placed on and closely contacted with. or,
Epoxy resin can be used in addition to acrylic resin.
After that, as in the case of the above-described first and second embodiments, the circuit of the semiconductor wafer 170 is covered so as to cover the bumps 112, and in the present embodiment, the protective material 131, as shown in FIG. The sealing material 114 is formed on the formation surface 111a.
Then, as shown in FIG. 17, the encapsulating material 114 is removed so that a part of the bump 112 is exposed from the encapsulating material 114. In addition, in this way, the sealing material 114 and the bumps 11 are formed.
Since the step of removing a part of 2 is included, there is a possibility that the protective material 131 interferes with the removing operation to cause damage to the circuit forming portion 113. In addition, as described above, the bump 112 may be removed up to the height of h / 2, so that the circuit forming surface 111a of the protective material 131 may be removed.
The height from is less than the above-mentioned h / 2.
【0028】次のステップでは、各回路形成部113に
対応して、半導体ウエハ170をダイシングして個々の
電子部品163に切り分ける。そして、図4に示すよう
に、分割した電子部品163を実装基板180に対向さ
せ、基板電極181とバンプ112とを半田、導電性ペ
ースト、又は導電性シート等を介して電気的及び機械的
に接合する。これにて電子部品実装済基板103が完成
する。In the next step, the semiconductor wafer 170 is diced into individual electronic components 163 corresponding to each circuit forming portion 113. Then, as shown in FIG. 4, the divided electronic component 163 is opposed to the mounting substrate 180, and the substrate electrode 181 and the bump 112 are electrically and mechanically connected via solder, a conductive paste, a conductive sheet, or the like. To join. This completes the electronic component-mounted board 103.
【0029】このように本第3実施形態によれば、上述
の各実施形態の場合と同様の効果を奏することができ
る。又、本第3実施形態では、上述の第1実施形態に比
べて、封止材114が保護材131を覆って設けられる
ことでより高い信頼性にて回路形成部113を保護する
ことができる。尚、上述の説明では、保護材131は、
回路形成部113の全体を覆う大きさの場合を例に採っ
たが、回路形成部113の一部を覆う大きさとすること
もできる。As described above, according to the third embodiment, it is possible to obtain the same effect as that of each of the above-described embodiments. Further, in the third embodiment, the sealing material 114 is provided so as to cover the protective material 131, so that the circuit forming portion 113 can be protected with higher reliability than in the first embodiment described above. . In the above description, the protective material 131 is
Although the size of the circuit forming portion 113 is entirely covered, the size of the circuit forming portion 113 may be partially covered.
【0030】第4実施形態;上述の第3実施形態では、
上記回路形成部113に接触して保護材131を設けた
後、上記回路形成面111aの全面を封止材114にて
封止した。これに対し、本第4実施形態では回路形成部
113に保護材131を設けた後、該保護材131のみ
を密閉部材132にて覆う形態を採る。図5、及び図1
8〜図21を参照して以下に詳しく説明する。尚、以下
の説明では、個々の半導体素子111毎に処理を行う場
合を例に採るが、勿論、ウエハ状態にて処理を行いダイ
シングにて個々の電子部品に切り分けてもよい。Fourth Embodiment: In the above-described third embodiment,
After the protective material 131 was provided in contact with the circuit forming portion 113, the entire surface of the circuit forming surface 111a was sealed with the sealing material 114. On the other hand, in the fourth embodiment, after the protective material 131 is provided on the circuit forming portion 113, only the protective material 131 is covered with the sealing member 132. 5 and 1
This will be described in detail below with reference to FIGS. In the following description, the case where the processing is performed for each individual semiconductor element 111 is taken as an example, but it goes without saying that the processing may be performed in a wafer state and divided into individual electronic components by dicing.
【0031】図18及び図19に示すように、半導体素
子111の回路形成面111aの一部にバンプ112を
形成するとともに、上記第3実施形態と同様に、回路形
成部113に上記保護材131を設ける。さらに次のス
テップでは、該保護材131に対応した形状をなし保護
材131を収納する凹部133を有し、シリコン系のガ
ラス部材にてなる密閉部材132を、保護材131を囲
うようにして回路形成面111a上に設け固定して保護
材131を密閉する。又、密閉部材132の材料として
はエポキシ系、アクリル系の材料が使用可能である。
又、保護材131と密閉部材132とは非接触であるよ
うに図示しているが、保護材131と密閉部材132と
は密着している。このようにして電子部品164が完成
する。そして図20に示すように、電子部品164を実
装基板180に対向させ、実装基板180の基板電極1
81と電子部品164のバンプ112とを、半田、導電
性ペースト、又は導電性シート等を介して電気的及び機
械的に接合する。これにて図5に示すように電子部品実
装済基板103が完成する。As shown in FIGS. 18 and 19, the bumps 112 are formed on a part of the circuit forming surface 111a of the semiconductor element 111, and the protective material 131 is formed on the circuit forming portion 113 as in the third embodiment. To provide. Further, in the next step, the sealing member 132, which has a shape corresponding to the protective material 131 and accommodates the protective material 131, and which is made of a silicon-based glass member, surrounds the protective material 131. The protective material 131 is sealed by being provided and fixed on the formation surface 111a. Further, as the material of the sealing member 132, an epoxy-based material or an acrylic-based material can be used.
Further, although the protective material 131 and the sealing member 132 are illustrated as not in contact with each other, the protective material 131 and the sealing member 132 are in close contact with each other. In this way, the electronic component 164 is completed. Then, as shown in FIG. 20, the electronic component 164 is opposed to the mounting board 180, and the board electrode 1 of the mounting board 180 is mounted.
81 and the bumps 112 of the electronic component 164 are electrically and mechanically joined via solder, a conductive paste, a conductive sheet, or the like. This completes the electronic component mounted substrate 103 as shown in FIG.
【0032】尚、上述の説明では、半導体素子111の
回路形成面111aにバンプ112を形成したが、図2
1に示すように、実装基板180の基板電極181にバ
ンプ112を形成することで電子部品164側にはバン
プ112形成を省略することもできる。又、バンプ11
2の設置箇所を問わず、図5に示すように電子部品16
4を実装基板180に確実に装着するためには、装着中
さらに装着完了後の状態において、上記密閉部材132
が実装基板180に干渉してはならない。よって、回路
形成面111aからの密閉部材132の高さは、装着完
了後における、上記回路形成面111aと実装基板18
0の基板表面180aとの隙間169よりも小さくなけ
ればならない。In the above description, the bump 112 is formed on the circuit forming surface 111a of the semiconductor element 111.
As shown in FIG. 1, by forming the bumps 112 on the substrate electrodes 181 of the mounting substrate 180, the formation of the bumps 112 on the electronic component 164 side can be omitted. Also, the bump 11
2 regardless of the installation location, as shown in FIG.
In order to securely mount the mounting member 180 on the mounting board 180, the sealing member 132 may be mounted during mounting and after completion of mounting.
Must not interfere with the mounting substrate 180. Therefore, the height of the sealing member 132 from the circuit forming surface 111a is determined by the height of the circuit forming surface 111a and the mounting substrate 18 after the mounting is completed.
It must be smaller than the gap 169 of the substrate surface 180a of 0.
【0033】又、バンプ112の設置箇所を問わず、バ
ンプ112の形成動作と、上記密閉部材132の取付動
作とは、どちらを先に行っても良いが、上述のように密
閉部材132の高さに注意を払う必要があることを考慮
すると、バンプ112の高さはバンプ112の形成動作
において比較的容易に制御可能であることから、密閉部
材132を設置した後にバンプ112を形成する方が好
ましい。Regardless of where the bumps 112 are installed, either the forming operation of the bumps 112 or the attaching operation of the sealing member 132 may be performed first, but as described above, the height of the sealing member 132 is increased. Considering that the height of the bump 112 can be controlled relatively easily in the forming operation of the bump 112, it is better to form the bump 112 after the sealing member 132 is installed. preferable.
【0034】以上説明したように、本第4実施形態によ
れば、上述の各実施形態の場合と同様の効果を奏するこ
とができる。又、さらに本第4実施形態によれば、上述
の第3実施形態に比べて、密閉部材132の設置後、バ
ンプ112を形成できるため、バンプ形状の制御が容易
である。又、保護される部分とバンプ112とが分離し
ているため、熱による応力が保護部分に集中せず、部品
の信頼性が向上する。As described above, according to the present fourth embodiment, it is possible to obtain the same effects as those of the above-described embodiments. Further, according to the fourth embodiment, the bump 112 can be formed after the sealing member 132 is installed, so that the bump shape can be controlled more easily than in the above-described third embodiment. Further, since the protected portion and the bump 112 are separated, the stress due to heat is not concentrated on the protected portion, and the reliability of the component is improved.
【0035】又、上記第4実施形態では、回路形成部1
13を保護材131にて覆ったが、保護材131の設置
を省略することもできる。即ち、回路形成部113を上
記密閉部材132のみにて密閉することで、回路形成部
113の保護を行っても良い。In the fourth embodiment, the circuit forming section 1
Although 13 is covered with the protective material 131, the installation of the protective material 131 can be omitted. That is, the circuit forming portion 113 may be protected by only sealing the circuit forming portion 113 with the sealing member 132.
【0036】又、上述の各実施形態では、電子部品の実
装基板180への装着方法は、フリップチップ方法を例
に採って説明したが、ダイボンドにて電子部品を実装基
板180へ固定しワイヤボンディング法にて電気的接続
を図っても良い。Further, in each of the above-described embodiments, the method of mounting the electronic component on the mounting substrate 180 has been described by taking the flip chip method as an example, but the electronic component is fixed to the mounting substrate 180 by die bonding and wire bonding is performed. Electrical connection may be achieved by the method.
【0037】[0037]
【発明の効果】以上詳述したように本発明の第1態様の
電子部品組立方法、及び第3態様の電子部品によれば、
回路形成部を封止材にて覆った後、該封止材に突起電極
が露出するまで上記封止材を除去したことにより、実装
基板上の電極に例えば超音波振動を加えながら突起電極
を接合する場合であっても、突起電極と半導体素子との
接合箇所付近に応力が集中することはない。よって、上
記回路形成部に損傷を与えることがなく、製品品質の安
定化を図ることができる。又、従来のように特殊形状の
パッケージは不要であり蓋をするという工程も必要な
い。よって、生産タクトの向上を含めた実装コストの低
減が可能である。As described above in detail, according to the electronic component assembling method of the first aspect and the electronic component of the third aspect of the present invention,
After the circuit forming portion is covered with the sealing material, the sealing material is removed until the protruding electrodes are exposed on the sealing material, so that the protruding electrodes can be formed while applying, for example, ultrasonic vibration to the electrodes on the mounting substrate. Even in the case of joining, stress is not concentrated near the joining portion between the protruding electrode and the semiconductor element. Therefore, it is possible to stabilize the product quality without damaging the circuit forming portion. Further, unlike the conventional case, a specially shaped package is not required, and a step of covering the lid is not necessary. Therefore, it is possible to reduce the mounting cost including the improvement of the production tact.
【0038】又、上記封止材にて覆う前に、上記回路形
成部に保護材を設けることで、より一層、回路形成部の
損傷を防止でき、製品品質の安定化を図ることができ
る。By providing a protective material on the circuit forming portion before covering with the encapsulating material, damage to the circuit forming portion can be further prevented, and product quality can be stabilized.
【0039】又、本発明の第2態様の電子部品組立方
法、及び第3態様の電子部品によれば、回路形成部に保
護材を設けさらに該保護材を密閉材にて覆うことで、実
装基板上の電極に例えば超音波振動を加えながら突起電
極を接合する場合であっても、突起電極と半導体素子と
の接合箇所付近に応力が集中することはない。よって、
上記回路形成部に損傷を与えることがなく、製品品質の
安定化を図ることができる。又、従来のように特殊形状
のパッケージは不要であり蓋をするという工程も必要な
い。よって、生産タクトの向上を含めた実装コストの低
減が可能である。Further, according to the electronic component assembling method of the second aspect of the present invention and the electronic component of the third aspect, mounting is performed by providing a protective material on the circuit forming portion and further covering the protective material with a sealing material. Even when the protruding electrode is bonded to the electrode on the substrate while applying ultrasonic vibration, for example, stress is not concentrated near the bonding portion between the protruding electrode and the semiconductor element. Therefore,
The product quality can be stabilized without damaging the circuit forming portion. Further, unlike the conventional case, a specially shaped package is not required, and a step of covering the lid is not necessary. Therefore, it is possible to reduce the mounting cost including the improvement of the production tact.
【図1】 本発明の第1実施形態における電子部品組立
方法における一工程を示す図であり、封止材を除去して
いる状態を示す図である。FIG. 1 is a diagram showing a step in an electronic component assembling method according to a first embodiment of the present invention, showing a state in which a sealing material is removed.
【図2】 本発明の第1実施形態における電子部品組立
方法にて組み立てられた電子部品を実装基板へ実装した
状態を示す図である。FIG. 2 is a diagram showing a state in which the electronic component assembled by the electronic component assembling method according to the first embodiment of the present invention is mounted on a mounting board.
【図3】 本発明の第2実施形態における電子部品組立
方法にて組み立てられた電子部品を実装基板へ実装した
状態を示す図である。FIG. 3 is a diagram showing a state in which an electronic component assembled by an electronic component assembling method according to a second embodiment of the present invention is mounted on a mounting board.
【図4】 本発明の第3実施形態における電子部品組立
方法にて組み立てられた電子部品を実装基板へ実装した
状態を示す図である。FIG. 4 is a diagram showing a state in which an electronic component assembled by an electronic component assembling method according to a third embodiment of the present invention is mounted on a mounting board.
【図5】 本発明の第4実施形態における電子部品組立
方法にて組み立てられた電子部品を実装基板へ実装した
状態を示す図である。FIG. 5 is a diagram showing a state in which an electronic component assembled by an electronic component assembling method according to a fourth embodiment of the present invention is mounted on a mounting board.
【図6】 本発明の各実施形態における電子部品組立方
法における一工程を示す図であり、半導体素子上にバン
プを形成している状態を説明する図である。FIG. 6 is a diagram showing a step in an electronic component assembling method according to each embodiment of the present invention, and is a diagram illustrating a state in which bumps are formed on a semiconductor element.
【図7】 半導体素子上にバンプが形成された状態を示
す図である。FIG. 7 is a diagram showing a state in which bumps are formed on a semiconductor element.
【図8】 本発明の第1〜第3実施形態における電子部
品組立方法における一工程を示す図であり、バンプを覆
い封止材を供給している状態を示す図である。FIG. 8 is a diagram showing a step in an electronic component assembling method according to the first to third embodiments of the present invention, and is a diagram showing a state in which a bump is covered and a sealing material is supplied.
【図9】 本発明の第1〜第3実施形態における電子部
品組立方法における一工程を示す図であり、バンプの一
部を露出させるまで封止材を除去した状態を示す図であ
る。FIG. 9 is a diagram showing a step in an electronic component assembling method according to the first to third embodiments of the present invention, and is a diagram showing a state in which the sealing material is removed until a part of the bump is exposed.
【図10】 図1に示すように、封止材を除去するとき
の除去量をバンプの高さから説明するための図である。FIG. 10 is a diagram for explaining the removal amount when the sealing material is removed from the height of the bump as shown in FIG.
【図11】 本発明の第1〜第3実施形態における電子
部品組立方法をウエハに対して行っている場合であっ
て、バンプの一部を露出させるまで封止材を除去した状
態を示す図である。FIG. 11 is a diagram showing a case where the electronic component assembling method according to the first to third embodiments of the present invention is performed on a wafer, and a state in which the sealing material is removed until a part of the bump is exposed. Is.
【図12】 図11に示すウエハを切り分けた状態を示
す図である。FIG. 12 is a diagram showing a state in which the wafer shown in FIG. 11 is cut into pieces.
【図13】 本発明の第2実施形態における電子部品組
立方法の一工程を示す図であり、封止材上に金属膜を形
成した状態を示す図である。FIG. 13 is a diagram showing a step in the electronic component assembling method according to the second embodiment of the present invention, showing a state in which a metal film is formed on the sealing material.
【図14】 図13に示す金属膜の一部をエッチングに
より除去した状態を示す図である。FIG. 14 is a diagram showing a state where a part of the metal film shown in FIG. 13 is removed by etching.
【図15】 本発明の第3実施形態における電子部品組
立方法の一工程を示す図であり、回路形成部に保護材を
設置した状態を示す図である。FIG. 15 is a diagram showing a step in the electronic component assembling method according to the third embodiment of the present invention, showing a state in which a protective material is installed in the circuit forming portion.
【図16】 図15に示すウエハ上に封止材を供給した
状態を示す図である。16 is a diagram showing a state in which a sealing material is supplied onto the wafer shown in FIG.
【図17】 図16に示す封止材を除去した状態を示す
図である。17 is a diagram showing a state in which the sealing material shown in FIG. 16 is removed.
【図18】 本発明の第4実施形態における電子部品組
立方法にて組み立てられた電子部品の一部断面を含む側
面図である。FIG. 18 is a side view including a partial cross section of an electronic component assembled by the electronic component assembling method according to the fourth embodiment of the present invention.
【図19】 図18に示す電子部品の平面図である。FIG. 19 is a plan view of the electronic component shown in FIG.
【図20】 図18及び図19に示す電子部品を実装基
板へ装着する状態を示す図である。FIG. 20 is a diagram showing a state where the electronic component shown in FIGS. 18 and 19 is mounted on a mounting board.
【図21】 図18及び図19に示す電子部品の変形例
を、バンプを形成した実装基板へ装着する状態を示す図
である。FIG. 21 is a diagram showing a state in which a modified example of the electronic component shown in FIGS. 18 and 19 is mounted on a mounting substrate having bumps formed thereon.
【図22】 従来の電子部品組立方法におけるフリップ
チップ実装にて組み立てられた電子部品実装済み基板を
示す図である。FIG. 22 is a diagram showing a board on which electronic components are mounted, which is assembled by flip-chip mounting in a conventional electronic component assembling method.
【図23】 従来の電子部品組立方法にて組み立てられ
た電子部品実装済み基板を示す図であって、パッケージ
内に電子部品をフリップチップ実装した場合の電子部品
実装済み基板を示す図である。FIG. 23 is a diagram showing an electronic component-mounted board assembled by a conventional electronic component assembling method, showing an electronic component-mounted board when an electronic component is flip-chip mounted in a package.
【図24】 従来の電子部品組立方法にて組み立てられ
た電子部品実装済み基板を示す図であって、パッケージ
内に電子部品をワイヤボンディング実装した場合の電子
部品実装済み基板を示す図である。FIG. 24 is a diagram showing an electronic component-mounted board assembled by a conventional electronic component assembling method, showing an electronic component-mounted board when an electronic component is wire-bonded and mounted in a package.
111…半導体素子、111a…回路形成面、112…
バンプ、112a…露出面、113…回路形成部、11
4…封止材、117…金属膜、131…保護材、132
…密閉部材、180…実装基板。111 ... Semiconductor element, 111a ... Circuit formation surface, 112 ...
Bumps, 112a ... exposed surface, 113 ... circuit forming part, 11
4 ... Sealing material, 117 ... Metal film, 131 ... Protective material, 132
... sealing member, 180 ... mounting substrate.
───────────────────────────────────────────────────── フロントページの続き (72)発明者 後川 和也 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 冨田 和之 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5F061 AA01 BA07 CA10 CB13 FA06 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Kazuya Gokawa 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. (72) Inventor Kazuyuki Tomita 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. F-term (reference) 5F061 AA01 BA07 CA10 CB13 FA06
Claims (9)
素子(111)の回路形成面(111a)に形成された
突起電極(112)を覆い上記回路形成面に封止材(1
14)を設けた後、上記回路形成部を保護した状態で上
記突起電極が上記封止材に露出するまで上記封止材を除
去することを特徴とする電子部品組立方法。1. A semiconductor device (111) having a circuit forming portion (113) formed thereon, covering a protruding electrode (112) formed on a circuit forming surface (111a) of the semiconductor element (111).
After providing 14), the encapsulating material is removed until the protruding electrodes are exposed to the encapsulating material while the circuit forming portion is protected.
した上記突起電極の露出面(112a)に上記突起電極
と導通する導電性材料(117)を設ける、請求項1記
載の電子部品組立方法。2. The conductive material (117), which is electrically connected to the protruding electrode, is provided on the exposed surface (112a) of the protruding electrode exposed on the sealing material after removing the sealing material. Electronic parts assembly method.
部に接触して該回路形成部を覆い保護する保護材(13
1)を設ける、請求項1又は2記載の電子部品組立方
法。3. A protective material (13) for contacting and covering the circuit forming portion before providing the encapsulating material so as to cover and protect the circuit forming portion.
The electronic component assembling method according to claim 1 or 2, wherein 1) is provided.
13)を形成した回路形成面(111a)上に、上記回
路形成部に接触して該回路形成部を覆い保護する保護材
(131)を設けた後、該保護材を密閉する密閉部材
(132)を設けることを特徴とする電子部品組立方
法。4. A circuit forming portion (1) of a semiconductor element (111)
A protective member (131) is provided on the circuit forming surface (111a) on which the circuit forming portion (13a) is formed to come into contact with the circuit forming portion to cover and protect the circuit forming portion, and then a sealing member (132) for sealing the protective material. ) Is provided, an electronic component assembling method.
面上に突起電極(112)を形成する、請求項4記載の
電子部品組立方法。5. The method of assembling an electronic component according to claim 4, wherein after the sealing member is provided, a protruding electrode (112) is formed on the circuit formation surface.
的に接続される実装基板(180)上に実装される、請
求項1から3、又は5のいずれかに記載の電子部品組立
方法。6. The electronic component assembling method according to claim 1, wherein the semiconductor element is mounted on a mounting substrate (180) electrically connected to the protruding electrode.
子状に形成され、上記封止材の除去後、各回路形成部に
切り分けられ、上記突起電極と電気的に接続される実装
基板(180)上に実装される、請求項1記載の電子部
品組立方法。7. The mounting substrate (wherein the circuit forming portion is formed in a grid pattern on a semiconductor wafer, is cut into each circuit forming portion after the encapsulating material is removed, and is electrically connected to the protruding electrode ( 180) The electronic component assembling method according to claim 1, which is mounted on.
子状に形成され、上記回路形成面上への突起電極の形成
後、各回路形成部に切り分けられ、実装基板上に実装さ
れる、請求項5記載の電子部品組立方法。8. The circuit forming portion is formed in a grid pattern on a semiconductor wafer, and after the protruding electrodes are formed on the circuit forming surface, the circuit forming portion is cut into each circuit forming portion and mounted on a mounting substrate. The electronic component assembling method according to claim 5.
部品組立方法により組み立てられたことを特徴とする電
子部品。9. An electronic component assembled by the electronic component assembling method according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001372737A JP3843235B2 (en) | 2001-12-06 | 2001-12-06 | Electronic component assembly method and electronic component mounted substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001372737A JP3843235B2 (en) | 2001-12-06 | 2001-12-06 | Electronic component assembly method and electronic component mounted substrate |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2003174117A true JP2003174117A (en) | 2003-06-20 |
| JP2003174117A5 JP2003174117A5 (en) | 2005-06-02 |
| JP3843235B2 JP3843235B2 (en) | 2006-11-08 |
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ID=19181573
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|---|---|---|---|
| JP2001372737A Expired - Fee Related JP3843235B2 (en) | 2001-12-06 | 2001-12-06 | Electronic component assembly method and electronic component mounted substrate |
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| Country | Link |
|---|---|
| JP (1) | JP3843235B2 (en) |
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- 2001-12-06 JP JP2001372737A patent/JP3843235B2/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| JP3843235B2 (en) | 2006-11-08 |
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