JP2003174051A - Semiconductor device and manufacturing method therefor - Google Patents

Semiconductor device and manufacturing method therefor

Info

Publication number
JP2003174051A
JP2003174051A JP2001370487A JP2001370487A JP2003174051A JP 2003174051 A JP2003174051 A JP 2003174051A JP 2001370487 A JP2001370487 A JP 2001370487A JP 2001370487 A JP2001370487 A JP 2001370487A JP 2003174051 A JP2003174051 A JP 2003174051A
Authority
JP
Japan
Prior art keywords
substrate
conductor pattern
hole
semiconductor device
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001370487A
Other languages
Japanese (ja)
Inventor
Osamu Yoda
修 依田
Yuuki Kuro
勇旗 黒
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SAINEKKUSU KK
Scinex Corp
Original Assignee
SAINEKKUSU KK
Scinex Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SAINEKKUSU KK, Scinex Corp filed Critical SAINEKKUSU KK
Priority to JP2001370487A priority Critical patent/JP2003174051A/en
Publication of JP2003174051A publication Critical patent/JP2003174051A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a simple and highly reliable semiconductor device where the loading of a solder bump for outer electrode is not required. <P>SOLUTION: A semiconductor element 3 is bonded to the center of a side where the conductor pattern 4 of a substrate 1 is formed. An aluminum bonding pad 6 formed on the surface of the semiconductor element 3, and a gold-plated bonding pad 5 on a conductor pattern 4-side are connected by ball-bonded metal wire 7. The substrate is set in upper/lower molds 9 and 10, where the semiconductor device is generated. The whole face of a side where the semiconductor element 3 is loaded is resin-sealed by sealing resin 8. Sealing pressure at the time of sealing resin is made strong enough to project the conductor pattern 4 to a through hole 2 side. The conductor pattern 4 is depressed to the through hole 2 side, and the prescribed quantity of it is projected at the time of sealing resin. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置及び半
導体装置の製造方法に係り、特にチップサイズパッケー
ジ構造を有する半導体装置及び半導体装置の製造方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly to a semiconductor device having a chip size package structure and a method of manufacturing the semiconductor device.

【0002】[0002]

【従来の技術】電子機器の小型・軽量化に伴い、半導体
装置のパッケージについても薄型化や小型・軽量化が求
められている。CSP(Chip Size Package)は、半導
体チップのサイズと同等またはわずかに大きいパッケー
ジの総称であって、小型・軽量化を実現できる上、内部
の配線長を短くすることができるので、信号遅延や雑音
等を低減できるパッケージ構造として実用化されてい
る。このようなチップサイズパッケージ構造を有する半
導体装置の製造方法は種々あるが、半導体ウエハから半
導体チップを切り出した後、その半導体チップを、半導
体チップと同等またはわずかに大きな配線基板上に搭載
し、その状態で樹脂封止するのが一般的である。
2. Description of the Related Art As electronic equipment becomes smaller and lighter, semiconductor device packages are required to be thinner and smaller and lighter. CSP (Chip Size Package) is a generic name for packages that are the same size as or slightly larger than the size of a semiconductor chip. It can be made smaller and lighter, and because the internal wiring length can be shortened, signal delay and noise can be reduced. It has been put to practical use as a package structure that can reduce such problems. Although there are various methods of manufacturing a semiconductor device having such a chip size package structure, after cutting a semiconductor chip from a semiconductor wafer, the semiconductor chip is mounted on a wiring board that is the same size as or slightly larger than the semiconductor chip. Generally, resin sealing is performed in this state.

【0003】図6は、従来のチップサイズパッケージ構
造を有する半導体装置の断面構造を示したものである。
図6に示したように、基板1には、外部接続端子となる
半田バンプ12の形成位置に貫通穴2が形成され、ま
た、基板1の表面には銅(Cu)箔からなる導体パター
ン4が形成され、その表面には金(Au)メッキされた
ボンディングパッド5が形成されている。そして、上記
導体パターン4が形成された側の基板中央部に半導体素
子3が接着され、この半導体素子3の表面に形成された
アルミ(Al)ボンディングパッド6と、上記金メッキ
されたボンディングパッドがボールボンディングされた
金(Au)ワイヤ7で結線されている。
FIG. 6 shows a cross-sectional structure of a semiconductor device having a conventional chip size package structure.
As shown in FIG. 6, a through hole 2 is formed in the substrate 1 at a position where a solder bump 12 to be an external connection terminal is formed, and a conductor pattern 4 made of a copper (Cu) foil is formed on the surface of the substrate 1. Is formed, and a bonding pad 5 plated with gold (Au) is formed on the surface thereof. Then, the semiconductor element 3 is adhered to the central portion of the substrate on the side where the conductor pattern 4 is formed, and the aluminum (Al) bonding pad 6 formed on the surface of the semiconductor element 3 and the gold-plated bonding pad form a ball. It is connected by a bonded gold (Au) wire 7.

【0004】また、上記半導体素子3が搭載された側の
基板上には、その全面にわたって、半導体素子3、金ワ
イヤ7、それらの接合部及び導体パターン4等を保護す
るために封止樹脂8によって樹脂封止されている。ま
た、これと反対側に形成された基板開口部(貫通穴)に
は半田バンプ12が形成されている。この半田バンプ1
2は、基板開口部底面の導体面にフラックスを塗布し、
その上に半田ボールを搭載して全体を加熱し、半田ボー
ルを溶融させて基板開口部底面の導体面に接合すること
により形成されている。
Further, on the substrate on which the semiconductor element 3 is mounted, the sealing resin 8 for protecting the semiconductor element 3, the gold wire 7, their joints, the conductor pattern 4, etc., over the entire surface. It is resin-sealed. Further, solder bumps 12 are formed in the substrate openings (through holes) formed on the opposite side. This solder bump 1
2 applies flux to the conductor surface at the bottom of the substrate opening,
It is formed by mounting a solder ball on it and heating the whole, melting the solder ball and joining it to the conductor surface of the bottom surface of the substrate opening.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、上述し
たような従来のチップサイズパッケージ構造を有する半
導体装置においては、外部接続用の半田バンプが必須で
あり、この半田バンプを形成するための工程が必要とな
るため、半導体の製造工程が煩雑になっていた。また、
半田ボールを溶融させるために、封止樹脂8の成型加工
後に半導体装置を再加熱するため、その加熱工程により
不良品が発生する恐れもあった。
However, in the semiconductor device having the conventional chip size package structure as described above, the solder bump for external connection is indispensable, and the step for forming the solder bump is necessary. Therefore, the semiconductor manufacturing process has been complicated. Also,
Since the semiconductor device is reheated after the molding process of the sealing resin 8 in order to melt the solder balls, a defective product may be generated due to the heating process.

【0006】本発明は、上述したような従来技術の問題
点を解消するために提案されたものであり、その目的
は、外部電極のための半田バンプの搭載を不要とし、簡
素で信頼性の高い半導体装置及び半導体装置の製造方法
を提供することにある。
The present invention has been proposed in order to solve the above-mentioned problems of the prior art, and an object thereof is to eliminate the mounting of solder bumps for external electrodes and to provide a simple and reliable structure. An object of the present invention is to provide a high semiconductor device and a method of manufacturing a semiconductor device.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するた
め、請求項1に記載の発明は、半導体素子を配置した基
板の表面に、前記半導体素子と電気的に接続される導体
パターンが形成され、前記半導体素子と導体パターンが
樹脂封止されてなる半導体装置において、前記基板には
貫通穴が形成され、この貫通穴内に前記導電パターンの
一部が、封止樹脂の成型時の圧力により基板の背面側に
突出していることを特徴とする。
In order to achieve the above object, the invention according to claim 1 is such that a conductor pattern electrically connected to the semiconductor element is formed on a surface of a substrate on which the semiconductor element is arranged. In the semiconductor device in which the semiconductor element and the conductor pattern are resin-sealed, a through hole is formed in the substrate, and a part of the conductive pattern is formed in the through hole by the pressure during molding of the sealing resin. It is characterized by protruding to the back side of.

【0008】請求項2に記載の発明は、請求項1に記載
の半導体装置において、前記導体パターンの突出量が、
前記基板の厚さと等しいことを特徴とするものである。
請求項3に記載の発明は、請求項1に記載の半導体装置
において、前記導体パターンの突出量が、前記基板の厚
さ以上であることを特徴とするものである。請求項4に
記載の発明は、請求項1乃至請求項3のいずれか一に記
載の半導体装置において、前記基板の背面側に突出した
導体パターンが、外部接続用の外部端子を構成している
ことを特徴とするものである。
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the protrusion amount of the conductor pattern is
The thickness is equal to the thickness of the substrate.
According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the protrusion amount of the conductor pattern is equal to or larger than the thickness of the substrate. According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, the conductor pattern protruding toward the back side of the substrate constitutes an external terminal for external connection. It is characterized by that.

【0009】上記のような構成を有する請求項1乃至請
求項4の発明によれば、外部接続のための貫通穴上の導
体パターンを基板の背面側に突出させることにより、半
田バンプなしに、直接外部接続端子として利用すること
ができる。
According to the first to fourth aspects of the present invention having the above-mentioned structure, the conductor pattern on the through hole for external connection is projected to the back side of the substrate, thereby eliminating the solder bump. It can be used directly as an external connection terminal.

【0010】請求項5に記載の発明は、貫通穴を形成し
た基板の表面に、半導体素子と電気的に結合される導体
パターンを形成し、前記基板上の所定の位置に半導体素
子を設置すると共に、前記半導体素子と導体パターンを
樹脂封止する半導体装置の製造方法において、前記貫通
穴上に位置する導体パターンを、樹脂封止の応力によっ
て前記基板の背面側に突出させることを特徴とする。
According to a fifth aspect of the present invention, a conductor pattern that is electrically coupled to a semiconductor element is formed on the surface of a substrate having a through hole, and the semiconductor element is installed at a predetermined position on the substrate. At the same time, in the method of manufacturing a semiconductor device in which the semiconductor element and the conductor pattern are resin-sealed, the conductor pattern located on the through hole is projected to the back surface side of the substrate by the stress of resin sealing. .

【0011】上記のような構成を有する請求項5の発明
によれば、基板上に形成されている導体パターンを外部
接続端子として利用することができるので、従来のよう
な外部接続用の半田バンプが不要となり、半田バンプを
形成するための工程が不要となるため、半導体の製造工
程が大幅に簡略化される。また、半田ボールを溶融させ
るために、封止樹脂の成型加工後に半導体装置を再加熱
する必要もなくなるため、加熱工程による不良品の発生
を防止することもできる。
According to the invention of claim 5 having the above-mentioned structure, since the conductor pattern formed on the substrate can be used as the external connection terminal, the conventional solder bump for external connection can be used. Is unnecessary, and the process for forming the solder bumps is not required, so that the semiconductor manufacturing process is greatly simplified. Further, since it is not necessary to reheat the semiconductor device after the molding process of the sealing resin to melt the solder balls, it is possible to prevent defective products due to the heating process.

【0012】請求項6に記載の発明は、請求項5に記載
の半導体装置の製造方法において、前記貫通穴上に位置
する導体パターンを、樹脂封止の前に、基板の背面側に
所定量突出させておくことを特徴とするものである。上
記のような構成を有する請求項6の発明によれば、予め
導体パターンを所定量だけ突出させておくという簡単な
処理を施すことにより、基板の背面側への導体パターン
の突出量をより大きくすることができるので、外部電極
としてより使い勝手のよい半導体装置を得ることができ
る。
According to a sixth aspect of the present invention, in the method of manufacturing a semiconductor device according to the fifth aspect, a predetermined amount of the conductor pattern located on the through hole is provided on the back surface side of the substrate before resin sealing. It is characterized in that it is projected. According to the invention of claim 6 having the above-mentioned configuration, the amount of protrusion of the conductor pattern to the back side of the substrate is further increased by performing a simple process of protruding the conductor pattern by a predetermined amount in advance. Therefore, it is possible to obtain a semiconductor device which is more convenient as an external electrode.

【0013】請求項7の発明は、半導体素子を配置した
基板の表面に、前記半導体素子と電気的に接続される導
体パターンが形成され、前記半導体素子と導体パターン
が樹脂封止されてなる半導体装置において、前記基板に
は貫通穴が形成され、前記基板の背面にはこの貫通穴を
塞ぐように導体パターンが形成され、この基板背面と前
記基板表面の導体パターンとが電気的に接続され、この
貫通穴に対向する基板背面の導電パターンの一部が、封
止樹脂の成型時の圧力により基板の背面側に突出してい
ることを特徴とする。請求項8の発明は、請求項7の発
明において、前記基板の背面側に突出した導体パターン
が、外部接続用の外部端子を構成していることを特徴と
する。上記のような構成を有する請求項7及び請求項8
の発明によれば、基板の背面側に形成した導体パターン
の一部が基板背面から突出しているので、これをそのま
ま外部接続のための端子として利用することが可能にな
る。特に、背面側の導体パターンを利用することで、基
板表面からの突出量を大きくすることができる。
According to a seventh aspect of the present invention, a semiconductor pattern in which a conductor pattern electrically connected to the semiconductor element is formed on a surface of a substrate on which the semiconductor element is arranged, and the semiconductor element and the conductor pattern are resin-sealed. In the device, a through hole is formed in the substrate, a conductor pattern is formed on the back surface of the substrate so as to close the through hole, and the substrate back surface and the conductor pattern on the substrate surface are electrically connected, It is characterized in that a part of the conductive pattern on the back surface of the substrate facing the through hole projects to the back surface side of the substrate due to the pressure during molding of the sealing resin. The invention of claim 8 is characterized in that, in the invention of claim 7, the conductor pattern projecting to the back surface side of the substrate constitutes an external terminal for external connection. Claim 7 and Claim 8 which have the above composition.
According to the invention, since a part of the conductor pattern formed on the back side of the substrate projects from the back side of the substrate, it can be used as it is as a terminal for external connection. In particular, the amount of protrusion from the substrate surface can be increased by using the conductor pattern on the back surface side.

【0014】請求項9の発明は、貫通穴を形成した基板
の表面に、半導体素子と電気的に結合される導体パター
ンを形成し、前記基板上の所定の位置に半導体素子を設
置すると共に、前記半導体素子と導体パターンを樹脂封
止する半導体装置の製造方法において、前記基板に貫通
穴を形成すると共に前記基板の背面にはこの貫通穴を塞
ぐように導体パターンを形成し、この基板背面と前記基
板表面の導体パターンとを電気的に接続し、この貫通穴
に対向する基板背面の導電パターンの一部を、封止樹脂
の成型時の圧力により基板の背面側に突出させることを
特徴とする。上記のような構成を有する請求項9の発明
によれば、基板の背面から導体パターンを突出させると
いう難しい作業を、樹脂封止時の圧力を利用することで
簡単に行うことができる。
According to a ninth aspect of the present invention, a conductor pattern electrically coupled to the semiconductor element is formed on the surface of the substrate having the through hole, and the semiconductor element is installed at a predetermined position on the substrate, In a method of manufacturing a semiconductor device in which a semiconductor element and a conductor pattern are resin-sealed, a through hole is formed in the substrate, and a conductor pattern is formed on a back surface of the substrate so as to close the through hole, and a back surface of the substrate is formed. The conductive pattern on the surface of the substrate is electrically connected, and a part of the conductive pattern on the back surface of the substrate facing the through hole is projected to the back surface side of the substrate by the pressure during molding of the sealing resin. To do. According to the invention of claim 9 having the above-mentioned configuration, the difficult work of protruding the conductor pattern from the back surface of the substrate can be easily performed by utilizing the pressure at the time of resin sealing.

【0015】[0015]

【発明の実施の形態】以下、本発明の実施の形態(以
下、実施形態という)を図面を参照して具体的に説明す
る。なお、図6に示した従来型と同一の部材には同一の
符号を付して説明は省略する。
BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention (hereinafter referred to as embodiments) will be specifically described below with reference to the drawings. The same members as those of the conventional type shown in FIG. 6 are designated by the same reference numerals and the description thereof will be omitted.

【0016】(1)第1実施形態 図1は、本発明に係る半導体装置の断面構造を示したも
のである。図1において、例えばポリイミド樹脂からな
る基板1上に配置される半導体素子3は、基板1に対し
て銀ペーストなどによって接着され、かつ前記半導体素
子3側のアルミボンディングパッド6と前記導体パター
ン4側の金メッキされたボンディングパッ5とは金ワイ
ヤ7で電気的に接続されている。
(1) First Embodiment FIG. 1 shows a sectional structure of a semiconductor device according to the present invention. In FIG. 1, a semiconductor element 3 arranged on a substrate 1 made of, for example, a polyimide resin is adhered to the substrate 1 with silver paste or the like, and the aluminum bonding pad 6 on the semiconductor element 3 side and the conductor pattern 4 side are attached. The gold-plated bonding pad 5 is electrically connected by a gold wire 7.

【0017】前記半導体素子3が搭載された基板1の片
側全面は、半導体素子3や金ワイヤ7を保護するために
封止樹脂8によって封止されている。また、基板1の表
面には、それぞれ銅配線から形成される導体パターン4
がメッキあるいは接着により形成されている。この基板
1における外部電極の形成位置には貫通穴2が形成さ
れ、前記基板表面の導体パターン4の一部は、この貫通
穴2を塞ぐように孔の開口面積よりも大きなものであ
り、前記貫通穴2内部に向けて湾曲して突出し、突出部
分の先端は基板1の背面近傍に露出している。すなわ
ち、導体パターン4の貫通穴2に対向した部分は、前記
封止樹脂8の圧縮成型時の圧力によって貫通穴2内に向
かって変形し、基板1の背面側に突出している。
The entire surface on one side of the substrate 1 on which the semiconductor element 3 is mounted is sealed with a sealing resin 8 in order to protect the semiconductor element 3 and the gold wire 7. In addition, on the surface of the substrate 1, a conductor pattern 4 formed of copper wiring, respectively.
Are formed by plating or adhesion. A through hole 2 is formed at a position where the external electrode is formed on the substrate 1, and a part of the conductor pattern 4 on the substrate surface is larger than the opening area of the hole so as to close the through hole 2. It curves and projects toward the inside of the through hole 2, and the tip of the projecting portion is exposed near the back surface of the substrate 1. That is, the portion of the conductor pattern 4 facing the through hole 2 is deformed toward the inside of the through hole 2 by the pressure during the compression molding of the sealing resin 8 and protrudes to the back side of the substrate 1.

【0018】このような構成を有する本実施形態の半導
体装置は、以下のようにして作製される。まず、図2
(a)に示したように、基板1の導体パターン4が形成
された側の中央部に半導体素子3が銀ペーストなどによ
って接着され、半導体素子3の表面に形成されたアルミ
パッド6と導体パターン4側の金メッキされたボンディ
ングパッド5が、ボールボンディングされた金ワイヤ7
で結線される。続いて、この基板を半導体装置を作成す
る上下金型9、10にセットし、半導体素子3が搭載さ
れた側の全面を、半導体素子3、金ワイヤ7、これらの
接合部及び導体パターン4を保護するために封止樹脂8
によって樹脂封止する。
The semiconductor device of this embodiment having such a structure is manufactured as follows. First, FIG.
As shown in (a), the semiconductor element 3 is adhered to the central portion of the side of the substrate 1 on which the conductor pattern 4 is formed by silver paste or the like, and the aluminum pad 6 formed on the surface of the semiconductor element 3 and the conductor pattern. The gold-plated bonding pad 5 on the 4 side is a ball-bonded gold wire 7
Is connected with. Subsequently, this substrate is set in upper and lower molds 9 and 10 for producing a semiconductor device, and the entire surface on the side on which the semiconductor element 3 is mounted is covered with the semiconductor element 3, the gold wire 7, their joints and the conductor pattern 4. Sealing resin 8 to protect
Resin sealing.

【0019】この場合、樹脂封止時の封止圧力を、銅箔
からなる導体パターン4を貫通穴2側に突出させるに必
要十分な圧力とする。これにより、図2(b)に示した
ように、樹脂封止と同時に基板上に形成されている導体
パターン4が貫通穴2側に押圧されて突出するので、そ
の先端の露出部分を外部接続端子として利用することが
できる。
In this case, the sealing pressure at the time of resin sealing is set to a pressure necessary and sufficient to cause the conductor pattern 4 made of copper foil to project to the side of the through hole 2. As a result, as shown in FIG. 2B, the conductor pattern 4 formed on the substrate is pressed toward the through hole 2 and protrudes at the same time as the resin sealing, so that the exposed portion of the tip is externally connected. It can be used as a terminal.

【0020】このように本実施形態によれば、基板上に
形成されている導体パターン4を外部接続端子として利
用することができるので、従来のような外部接続用の半
田バンプが不要となる。その結果、半田バンプを形成す
るための工程が不要となるため、半導体の製造工程が大
幅に簡略化される。また、半田ボールを溶融させるため
に、封止樹脂8の成型加工後に半導体装置を再加熱する
必要もなくなるため、加熱工程による不良品の発生を防
止することもできる。
As described above, according to this embodiment, since the conductor pattern 4 formed on the substrate can be used as the external connection terminal, the conventional solder bump for external connection is unnecessary. As a result, the process for forming the solder bumps is not required, and the semiconductor manufacturing process is greatly simplified. Further, since it is not necessary to reheat the semiconductor device after molding the sealing resin 8 in order to melt the solder balls, it is possible to prevent defective products from being generated due to the heating process.

【0021】(2)第2実施形態 続いて、本発明の第2実施形態を図3を参照して説明す
る。本実施形態は、上記第1実施形態の変形例であっ
て、図3に示したように、基板1の背面側への導体パタ
ーン4の突出量が、基板の背面側に設置される下型金型
20との接触面の高さより外側に突出するように構成さ
れている。
(2) Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIG. The present embodiment is a modified example of the first embodiment, and as shown in FIG. 3, the protrusion amount of the conductor pattern 4 to the back side of the substrate 1 is a lower mold installed on the back side of the substrate. It is configured to project outside the height of the contact surface with the mold 20.

【0022】このような構成を有する本実施形態の半導
体装置は、以下のようにして作成される。まず、本実施
形態においては、図3に示したように、半導体装置を作
成する上下金型9、20の内、下型金型20の表面に所
定の厚さを有する弾性体11が配設されている。そし
て、導体パターン4が形成された側に半導体素子3を配
設した基板1を上記上下金型9、20にセットし、半導
体素子3が搭載された片側全面を封止樹脂8によって樹
脂封止する。
The semiconductor device of this embodiment having such a structure is manufactured as follows. First, in the present embodiment, as shown in FIG. 3, an elastic body 11 having a predetermined thickness is provided on the surface of the lower mold 20 of the upper and lower molds 9 and 20 for manufacturing the semiconductor device. Has been done. Then, the substrate 1 on which the semiconductor element 3 is arranged on the side on which the conductor pattern 4 is formed is set in the upper and lower molds 9 and 20, and the entire one side on which the semiconductor element 3 is mounted is resin-sealed with the sealing resin 8. To do.

【0023】この場合、樹脂封止時の封止圧力を、銅箔
からなる導体パターン4を突出させるに必要十分な圧力
とすることにより、樹脂封止の際に、貫通穴2部分に位
置する導体パターン4が基板1の背面側に向けて押圧さ
れ、さらに下型金型20の表面に設けられた弾性体11
をも押圧して、基板の厚さ以上に導体パターン4を基板
の背面側に突出させることができる。その結果、樹脂封
止と同時に、外部電極としてより使い勝手のよい半導体
装置を形成することができる。
In this case, the sealing pressure at the time of resin sealing is set to a pressure sufficient for projecting the conductor pattern 4 made of copper foil, so that the through hole 2 portion is positioned at the time of resin sealing. The conductor pattern 4 is pressed toward the back surface side of the substrate 1, and the elastic body 11 provided on the surface of the lower mold 20 is further pressed.
Can also be pressed to cause the conductor pattern 4 to project to the back side of the substrate beyond the thickness of the substrate. As a result, it is possible to form a semiconductor device that is more convenient to use as an external electrode simultaneously with resin sealing.

【0024】このように本実施形態によれば、上記第1
実施形態と同様の作用・効果が得られるだけでなく、基
板1の背面側への導体パターン4の突出量が、第1実施
形態と比較して基板外側に設置される金型20との接触
面高さより外側に突出するように構成することができる
ので、外部電極としてより使い勝手のよい半導体装置を
製造することができる。
As described above, according to this embodiment, the first
Not only the same operation and effect as in the first embodiment can be obtained, but also the protrusion amount of the conductor pattern 4 to the back surface side of the substrate 1 is in contact with the mold 20 installed outside the substrate as compared with the first embodiment. Since it can be configured to project outward from the surface height, it is possible to manufacture a semiconductor device that is more convenient as an external electrode.

【0025】(3)第3実施形態 続いて、本発明の第3実施形態を図4を参照して説明す
る。本実施形態は、上記第1実施形態の変形例であっ
て、図4(a)に示したように、封止樹脂8によって樹
脂封止する前に、予め導体パターン4を、貫通穴2に対
応した所定の径を有するポンチ13等によって貫通穴2
側に押圧して、基板の背面側へ突出させておくものであ
る。
(3) Third Embodiment Next, a third embodiment of the present invention will be described with reference to FIG. This embodiment is a modification of the first embodiment, and as shown in FIG. 4A, the conductor pattern 4 is previously formed in the through hole 2 before resin sealing with the sealing resin 8. The through hole 2 is formed by a punch 13 or the like having a corresponding predetermined diameter.
It is pressed to the side and projected to the back side of the substrate.

【0026】このような構成を有する本実施形態の半導
体装置は、以下のようにして作成される。まず、本実施
形態においては、図4(a)に示したように、導体パタ
ーン4をポンチ13等を用いて貫通穴2側に押圧して基
板の背面側へ突出させておき、次に、図4(b)に示し
たように、この導体パターン4側の金メッキされたボン
ディングパット5と半導体素子3の表面に形成されたア
ルミボンディングパッド6とを金ワイヤ7で結線する。
その後、図4(c)に示したように、半導体素子3が搭
載された片側全面を封止樹脂8にて樹脂封止する。
The semiconductor device of this embodiment having such a structure is manufactured as follows. First, in the present embodiment, as shown in FIG. 4A, the conductor pattern 4 is pressed toward the through hole 2 side by using the punch 13 or the like so as to protrude toward the back surface side of the substrate, and then, As shown in FIG. 4B, the gold-plated bonding pad 5 on the conductor pattern 4 side and the aluminum bonding pad 6 formed on the surface of the semiconductor element 3 are connected by a gold wire 7.
Thereafter, as shown in FIG. 4C, the entire one side on which the semiconductor element 3 is mounted is resin-sealed with the sealing resin 8.

【0027】そして、樹脂封止時の封止圧力を銅箔から
なる導体パターン4を突出させるに必要十分な圧力とす
ることにより、すでに基板の背面側に向けて突出してい
る導体パターン4がさらに同方向に向けて押圧されるの
で、導体パターンを容易に基板の厚さ以上に突出させる
ことができる。その結果、樹脂封止と同時に、外部電極
としてより使い勝手のよい半導体装置を形成することが
できる。
Then, the sealing pressure at the time of resin sealing is set to a pressure necessary and sufficient for causing the conductor pattern 4 made of copper foil to protrude, so that the conductor pattern 4 already protruding toward the back side of the substrate is further increased. Since the conductor patterns are pressed in the same direction, it is possible to easily make the conductor pattern protrude more than the thickness of the substrate. As a result, it is possible to form a semiconductor device that is more convenient to use as an external electrode simultaneously with resin sealing.

【0028】このように本実施形態によれば、上記第1
実施形態と同様の作用・効果が得られるだけでなく、予
め導体パターン4を所定量だけ突出させておくという簡
単な処理を施すことにより、基板1の背面側への導体パ
ターン4の突出量を、第1実施形態より大きくすること
ができるので、外部電極としてより使い勝手のよい半導
体装置を製造することができる。
As described above, according to this embodiment, the first
Not only the same operation and effect as in the embodiment can be obtained, but the amount of protrusion of the conductor pattern 4 to the back side of the substrate 1 can be increased by performing a simple process of protruding the conductor pattern 4 by a predetermined amount in advance. Since the size can be made larger than that of the first embodiment, it is possible to manufacture a semiconductor device which is more convenient as an external electrode.

【0029】(4)第4実施形態 本発明の第4実施形態について、図5を参照して説明す
る。本実施形態は、基板1の背面側に形成した導体パタ
ーン4を圧縮成型時の圧力により突出させるものであ
る。すなわち、本実施形態では、図5に示すように、例
えばポリイミド樹脂からなる基板1の表面と背面に、そ
れぞれ銅配線から形成される導体パターン4a,4bが
メッキあるいは接着により形成され、これらの導体パタ
ーン4a,4bは、所定の部分で基板1を貫通するなど
して互いに電気的に接続されている。また、基板1にお
ける外部電極の形成位置には貫通穴2が形成され、前記
基板背面側の導体パターン4bは、この貫通穴2を塞ぐ
ように孔の開口面積よりも大きなものとなっている。
(4) Fourth Embodiment A fourth embodiment of the present invention will be described with reference to FIG. In this embodiment, the conductor pattern 4 formed on the back side of the substrate 1 is projected by the pressure during compression molding. That is, in the present embodiment, as shown in FIG. 5, conductor patterns 4a and 4b formed of copper wiring are formed by plating or bonding on the front surface and the back surface of the substrate 1 made of, for example, a polyimide resin. The patterns 4a and 4b are electrically connected to each other by penetrating the substrate 1 at predetermined portions. Further, a through hole 2 is formed at the position where the external electrode is formed on the substrate 1, and the conductor pattern 4b on the back surface side of the substrate is larger than the opening area of the hole so as to close the through hole 2.

【0030】基板1上に配置される半導体素子3は、基
板1に対して銀ペーストなどによって接着され、かつ前
記半導体素子3のボンディングパッドと前記基板表面側
の導体パターン4aとは金ワイヤ7で電気的に接続され
ている。前記半導体素子3が搭載された基板1の片側全
面は、半導体素子3や金ワイヤ7を保護するために封止
樹脂8によって封止されている。この封止樹脂8は、基
板1に形成された前記貫通穴2の部分から基板背面側の
導体パターン4b側に注入され、この注入時の圧力によ
って前記導体パターン4bは基板1の背面表面から湾曲
して突出している。
The semiconductor element 3 arranged on the substrate 1 is adhered to the substrate 1 by silver paste or the like, and the bonding pad of the semiconductor element 3 and the conductor pattern 4a on the substrate surface side are gold wires 7. It is electrically connected. The entire surface on one side of the substrate 1 on which the semiconductor element 3 is mounted is sealed with a sealing resin 8 in order to protect the semiconductor element 3 and the gold wire 7. The sealing resin 8 is injected into the conductor pattern 4b on the back side of the substrate from the portion of the through hole 2 formed in the substrate 1, and the conductor pattern 4b is curved from the back surface of the substrate 1 due to the pressure at the time of the injection. And is protruding.

【0031】このような構成を有する本実施形態の半導
体素子3を製造するには、前記各実施形態と同様に、表
面と背面の両面に導体パターン4を形成した基板1上に
半導体素子3を固定し、ワイヤボンディングを行った
後、圧縮成型用の金型内にセットし、封止樹脂8によっ
て全体を封止するものであるが、その際、成型時の圧力
により封止樹脂8の一部が貫通穴2内に入り込み、基板
1の背面側に配置された導体パターン4bをその内側か
ら押圧する。その結果、この押圧力により導体パターン
4bが変形し、基板1の背面から突出することになる。
なお、この場合、基板1背面から導体パターン4bが突
出するため、樹脂封止用の金型としては、導体パターン
4bの突出位置に合わせて、逃がし用の凹部を設けてお
くか、前記実施の形態でも説明したように、金型の内面
に弾性体(例えば、耐熱且つ弾力性を有するフッ素樹脂
など)を配設しておくと良い。
In order to manufacture the semiconductor element 3 of this embodiment having such a configuration, the semiconductor element 3 is placed on the substrate 1 on which the conductor patterns 4 are formed on both the front surface and the back surface, as in the above-described embodiments. After being fixed and wire-bonded, it is set in a mold for compression molding, and the whole is sealed with a sealing resin 8. At that time, one part of the sealing resin 8 is pressed by the pressure during molding. The portion enters the through hole 2 and presses the conductor pattern 4b arranged on the back side of the substrate 1 from the inside. As a result, the conductor pattern 4b is deformed by this pressing force and protrudes from the back surface of the substrate 1.
In this case, since the conductor pattern 4b protrudes from the back surface of the substrate 1, as a mold for resin encapsulation, a relief recess is provided in accordance with the protruding position of the conductor pattern 4b or the above-described embodiment is used. As described in the form, it is preferable to dispose an elastic body (for example, a fluororesin having heat resistance and elasticity) on the inner surface of the mold.

【0032】以上のように、本実施形態によれば、導体
パターンの一部を利用して外部電極を基板背面から突出
させることができるので、半導体装置の実装時における
半田フィレット形成が確実となり、実装時の信頼性が向
上する。また、外部電極を実装基板に直付けしているL
GAタイプの半導体装置に比較し、リフロー時の熱応力
を緩和することができる。特に、本実施形態では、導体
パターンを基板の背面側に配置し、これを封止樹脂の圧
力で基板背面から突出させるようにしたので、導体パタ
ーンの少ない変形量で大きな突出量を得ることができる
と共に、導体パターンの厚さが薄い場合でも変形時にお
ける亀裂などのおそれが無い利点もある。
As described above, according to the present embodiment, the external electrode can be projected from the back surface of the substrate by utilizing a part of the conductor pattern, so that the solder fillet is formed when the semiconductor device is mounted, Reliability during mounting is improved. In addition, the external electrode is directly attached to the mounting board.
The thermal stress at the time of reflow can be relaxed as compared with the GA type semiconductor device. In particular, in the present embodiment, the conductor pattern is arranged on the back side of the substrate, and the conductor pattern is projected from the back side of the substrate by the pressure of the sealing resin. Therefore, a large amount of protrusion can be obtained with a small amount of deformation of the conductor pattern. In addition, there is an advantage that even if the conductor pattern is thin, there is no fear of cracks during deformation.

【0033】(5)他の実施形態 本発明は、上述した実施形態に限定されるものではな
く、上記各実施形態で示した方法によって形成した電極
の突出部分に半田バンプを形成し、外部電極とすること
も可能である。また、半導体装置を作成する上下金型の
内、下型金型の表面の、基板に形成された貫通穴に対応
する位置に所定の大きさ及び深さを有する窪みを設け
て、導体パターン4の突出部が基板の背面側に突出でき
るように構成しても良い。
(5) Other Embodiments The present invention is not limited to the above-mentioned embodiments, and solder bumps are formed on the protruding portions of the electrodes formed by the methods shown in the above-mentioned respective embodiments, and external electrodes are formed. It is also possible to Further, among the upper and lower molds for forming the semiconductor device, a recess having a predetermined size and depth is provided on the surface of the lower mold to correspond to the through hole formed in the substrate, and the conductor pattern 4 is formed. The protrusion may be configured so as to protrude toward the back surface of the substrate.

【0034】[0034]

【発明の効果】以上述べたように、本発明によれば、外
部電極のための半田バンプの搭載を不要とし、簡素で信
頼性の高い半導体装置及び半導体装置の製造方法を提供
することができる。
As described above, according to the present invention, it is possible to provide a simple and highly reliable semiconductor device and a method of manufacturing a semiconductor device, which does not require mounting of solder bumps for external electrodes. .

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体装置の第1実施形態の構成
を示す断面図。
FIG. 1 is a sectional view showing a configuration of a first embodiment of a semiconductor device according to the present invention.

【図2】図1に示す半導体装置の製造過程を示す断面図
であって、(a)は樹脂封止前、(b)は樹脂封止後を
示す。
2A and 2B are cross-sectional views showing a manufacturing process of the semiconductor device shown in FIG. 1, in which FIG. 2A is before resin sealing and FIG. 2B is after resin sealing.

【図3】本発明に係る半導体装置の第2実施形態の構成
を示す断面図。
FIG. 3 is a sectional view showing a configuration of a second embodiment of a semiconductor device according to the present invention.

【図4】本発明に係る半導体装置の第3実施形態の製造
過程を示す断面図であって、(a)は導体パターンの押
圧前、(b)は樹脂封止前、(c)は樹脂封止後を示
す。
FIG. 4 is a cross-sectional view showing a manufacturing process of a third embodiment of a semiconductor device according to the present invention, where (a) is before pressing a conductor pattern, (b) is before resin sealing, and (c) is resin. Shown after sealing.

【図5】本発明に係る半導体装置の第4実施形態の構成
を示す断面図。
FIG. 5 is a sectional view showing a configuration of a fourth embodiment of a semiconductor device according to the present invention.

【図6】従来の半導体装置の構成を示す断面図。FIG. 6 is a cross-sectional view showing the configuration of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1…基板 2…貫通穴 3…半導体素子 4…導体パターン 5…導体パターン側のボンディングパッド 6…半導体素子側のボンディングパッド 7…金ワイヤ 8…封止樹脂 9…上型金型 10…下型金型 11…弾性体 12…半田バンプ 13…ポンチ 1 ... Substrate 2 ... Through hole 3 ... Semiconductor element 4 ... Conductor pattern 5 ... Bonding pad on conductor pattern side 6 ... Bonding pad on the semiconductor element side 7 ... Gold wire 8 ... Sealing resin 9 ... Upper mold 10 ... Lower mold 11 ... Elastic body 12 ... Solder bump 13 ... Punch

Claims (9)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子を配置した基板の表面に、前
記半導体素子と電気的に接続される導体パターンが形成
され、前記半導体素子と導体パターンが樹脂封止されて
なる半導体装置において、 前記基板には貫通穴が形成され、この貫通穴内に前記導
電パターンの一部が、封止樹脂の成型時の圧力により基
板の背面側に突出していることを特徴とする半導体装
置。
1. A semiconductor device in which a conductor pattern electrically connected to the semiconductor element is formed on a surface of a substrate on which a semiconductor element is arranged, and the semiconductor element and the conductor pattern are resin-sealed, wherein the substrate The semiconductor device is characterized in that a through hole is formed in the through hole, and a part of the conductive pattern is projected in the through hole to the back surface side of the substrate due to the pressure at the time of molding the sealing resin.
【請求項2】 前記導体パターンの突出量が、前記基板
の厚さと等しいことを特徴とする請求項1に記載の半導
体装置。
2. The semiconductor device according to claim 1, wherein the protrusion amount of the conductor pattern is equal to the thickness of the substrate.
【請求項3】 前記導体パターンの突出量が、前記基板
の厚さ以上であることを特徴とする請求項1に記載の半
導体装置。
3. The semiconductor device according to claim 1, wherein the protrusion amount of the conductor pattern is equal to or larger than the thickness of the substrate.
【請求項4】 前記基板の背面側に突出した導体パター
ンが、外部接続用の外部端子を構成していることを特徴
とする請求項1乃至請求項3のいずれか一に記載の半導
体装置。
4. The semiconductor device according to claim 1, wherein the conductor pattern protruding toward the back surface of the substrate constitutes an external terminal for external connection.
【請求項5】 貫通穴を形成した基板の表面に、半導体
素子と電気的に結合される導体パターンを形成し、前記
基板上の所定の位置に半導体素子を設置すると共に、前
記半導体素子と導体パターンを樹脂封止する半導体装置
の製造方法において、 前記貫通穴上に位置する導体パターンを、樹脂封止の応
力によって前記基板の背面側に突出させることを特徴と
する半導体装置の製造方法。
5. A conductor pattern electrically coupled to a semiconductor element is formed on the surface of a substrate having a through hole, the semiconductor element is installed at a predetermined position on the substrate, and the semiconductor element and the conductor are connected to each other. A method of manufacturing a semiconductor device in which a pattern is resin-sealed, wherein a conductor pattern located on the through hole is projected to the back surface side of the substrate by a stress of resin sealing.
【請求項6】 前記貫通穴上に位置する導体パターン
を、樹脂封止の前に、基板の背面側に所定量突出させて
おくことを特徴とする請求項5に記載の半導体装置の製
造方法。
6. The method of manufacturing a semiconductor device according to claim 5, wherein the conductor pattern located on the through hole is made to protrude by a predetermined amount on the back surface side of the substrate before resin sealing. .
【請求項7】 半導体素子を配置した基板の表面に、前
記半導体素子と電気的に接続される導体パターンが形成
され、前記半導体素子と導体パターンが樹脂封止されて
なる半導体装置において、 前記基板には貫通穴が形成され、前記基板の背面にはこ
の貫通穴を塞ぐように導体パターンが形成され、この基
板背面と前記基板表面の導体パターンとが電気的に接続
され、 この貫通穴に対向する基板背面の導電パターンの一部
が、封止樹脂の成型時の圧力により基板の背面側に突出
していることを特徴とする半導体装置。
7. A semiconductor device in which a conductor pattern electrically connected to the semiconductor element is formed on a surface of a substrate on which a semiconductor element is arranged, and the semiconductor element and the conductor pattern are resin-sealed, wherein the substrate A through hole is formed in the through hole, and a conductor pattern is formed on the back surface of the substrate so as to close the through hole. The back surface of the substrate and the conductor pattern on the substrate surface are electrically connected to each other, and the through hole is opposed to the through hole. A semiconductor device, wherein a part of the conductive pattern on the back surface of the substrate protrudes to the back surface side of the substrate due to the pressure at the time of molding the sealing resin.
【請求項8】 前記基板の背面側に突出した導体パター
ンが、外部接続用の外部端子を構成していることを特徴
とする請求項7に記載の半導体装置。
8. The semiconductor device according to claim 7, wherein the conductor pattern protruding toward the back side of the substrate constitutes an external terminal for external connection.
【請求項9】 貫通穴を形成した基板の表面に、半導体
素子と電気的に結合される導体パターンを形成し、前記
基板上の所定の位置に半導体素子を設置すると共に、前
記半導体素子と導体パターンを樹脂封止する半導体装置
の製造方法において、 前記基板に貫通穴を形成すると共に前記基板の背面には
この貫通穴を塞ぐように導体パターンを形成し、この基
板背面と前記基板表面の導体パターンとを電気的に接続
し、 この貫通穴に対向する基板背面の導電パターンの一部
を、封止樹脂の成型時の圧力により基板の背面側に突出
させることを特徴とする半導体装置の製造方法。
9. A conductor pattern electrically coupled to a semiconductor element is formed on a surface of a substrate having a through hole, the semiconductor element is installed at a predetermined position on the substrate, and the semiconductor element and the conductor are connected to each other. In a method of manufacturing a semiconductor device in which a pattern is resin-sealed, a through hole is formed in the substrate and a conductor pattern is formed on a back surface of the substrate so as to close the through hole, and a conductor on the back surface of the substrate and a conductor on the front surface of the substrate. Manufacture of a semiconductor device characterized in that a part of the conductive pattern on the back surface of the substrate facing the through hole is electrically connected to the pattern and is projected to the back surface side of the substrate by the pressure at the time of molding the sealing resin. Method.
JP2001370487A 2001-12-04 2001-12-04 Semiconductor device and manufacturing method therefor Pending JP2003174051A (en)

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Publications (1)

Publication Number Publication Date
JP2003174051A true JP2003174051A (en) 2003-06-20

Family

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