JP2003173291A - Memory controller - Google Patents

Abstract

(57) [Summary] [Object] To provide a memory control device capable of improving access efficiency and effectiveness of a prefetch buffer. In a memory control device connected to a plurality of masters and connected to a memory device via a memory bus on the other side and performing a write operation and a read operation on the memory device in response to a request from the plurality of masters, A prefetch buffer for performing a read operation and storing the result; means for designating an address range; and means for comparing a read request address with information held by the address range designating means. Only when the value is within the range specified by the specifying means, the result of the preceding read operation is controlled to be stored in the prefetch buffer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control device in a computer system.

[0002]

2. Description of the Related Art In recent years, CPU speeds have never stopped increasing, and they are improving at a pace of 1.5 times or more per year. Along with this, the amount of data transferred to and from the main storage device per unit time is also increasing at a similar pace. To mitigate this, use the locality of memory access,
In order to obtain high-speed storage access, the capacity of the cache provided in the CPU has been increased, or the cache has been hierarchized.

However, it is still difficult to solve the increase in the gap between the operating speed of the CPU and the access speed of the main memory year after year. To solve this fundamentally, it is necessary to greatly improve the access speed (memory bandwidth) of the main memory itself. Today, a dynamic RAM (DRAM) which is a semiconductor memory is usually used for a main memory such as a personal computer (PC). CP
Since the speed improvement of U exceeds the speed improvement due to the progress of the semiconductor device itself, this must be achieved also in the DRAM by devising the circuit configuration or method.

From such a background, various methods for improving the memory bandwidth in the past have been devised and put into practical use. Direct Rambus DRAM is one of the methods recently put into practical use and drawing attention. . Direct Rambus DRAM incorporates the concept of channel 1
High memory bandwidths of up to 1.6 GB per second per channel can be realized.

FIG. 1 shows an RS of a direct Rambus DRAM.
An example of a transfer protocol in the L channel is shown. In the direct Rambus, data is transferred at both rising and falling timings of a clock per one clock cycle, and one packet is formed by four clocks. In FIG. 1, first, in cycles 0 to 3, a row packet for activating a page designated by'x 'is issued. Here, 'x' represents a set of a device ID, a bank address, and a row address each having a specific number of bits.

Then, in cycles 7-10, 'x
A column packet instructing to read the data of the address designated by 0'is issued. Where'x
0'is a device ID consisting of a specific number of bits,
It represents a set of bank address and column address, and the device ID and bank address here are the same as those in'x '. The column address is 1 in the page
Specify one address.

Further, in cycles 11-14, the'x
A column packet instructing to read the data of the address designated by 1'is issued. Where'x
1'is a device ID consisting of a specific number of bits,
It represents a set of bank address and column address, and the device ID and bank address are the same as those in'x 'here as well. That is, reading from two addresses in the same device, the same bank, and the same page is executed by a set of these row packets and column packets.

In cycles 19-22, the first (x
The data corresponding to the read command of 0) is read from the DRAM and the second (x
Data corresponding to the read command 1) is read from the DRAM.

In the example shown in FIG. 1, reading from another bank is also performed in parallel with this series of read operations. That is, in cycles 8 to 11, row packets for activating the page designated by'y 'are issued. Here, 'y' refers to a page located in a different bank (a different device or a non-interfering bank of the same device) from the preceding'x '.

Then, in cycles 15-18, 'y
A column packet instructing to read the data of the address designated by 0'is issued. Where'y
The device ID and bank address at 0'are the same as those at'y '.

Further, in cycles 19 to 22, 'y
A column packet instructing to read the data of the address designated by 1'is issued. even here,
The device ID and bank address in "y1" are the same as those in "y". Cycle 27-30
, The data corresponding to the third (y0) read command is read from the DRAM, and the cycles 31 to 34
At, the data corresponding to the fourth (y1) read command is read from the DRAM.

Hereinafter, "z", "z0", "z1",
The same applies to "q", "q0", and "q1".
The activation of the bank'q 'that does not interfere with'x'and'y'and the activation of the bank'q' that does not interfere with'x ',' y 'and'z' are performed, and the fifth (z0),
The respective data is read in response to the issuance of the sixth (z1), seventh (q0), and eighth (q1) read commands. In this way, continuous commands perform pipeline operation for each phase of row packet, column packet, and data bucket. In this way, the direct Rambus DRAM has 32 pipelines with 4 stages.
Maximum bandwidth is obtained when accessed in bytes.

Therefore, the effective bandwidth is lowered in the access with the size smaller than 32 bytes. For example,
In the case where continuous 32 bytes of data are collectively read in 32 bytes at a time, or when 16 bytes are read in two times, the former is more efficient and ends in a shorter time.
If access in units smaller than 32 bytes occurs frequently, it is possible to improve access efficiency by providing a prefetch buffer in the memory controller.

FIG. 2 is a diagram for explaining a configuration example of a conventional example of a memory controller having a prefetch buffer.

In FIG. 2, reference numeral 200 denotes a memory controller, which is a CPU or a DMA via the system bus 210.
Bus masters 220, 2 such as controllers and bus bridges
DRAM (direct RDRAM in this example) 230, 231, connected to 21, 222, 223
232, 233. The bus master 220,
In order to avoid access contention on the system bus, the access of 221, 222, and 223 is arbitrated by an arbitration device (not shown), and only one master can access the memory controller 200 at the same time. 241 is a bidirectional data signal (DQA [8:
0], DQB [8: 0]) line, and transmits data from the memory controller to the DRAM at the time of writing, and from the DRAM to the memory controller at the time of reading. 242,2
Reference numerals 43 are row signal (ROW [2: 0]) and column signal (COL [4: 0]) lines, respectively, for transmitting row packets and column packets from the memory controller to the DRAM. 244 and 255 are clock signals (CTM, CFM) on the channels.

Reference numerals 201 to 205 are components of the memory controller 200. Reference numeral 203 denotes a system bus interface circuit for connecting to the system bus.
Reference numeral 204 is a buffer for temporarily storing the read / write command. Reference numeral 202 denotes a memory channel interface circuit for adapting the read / write command to the protocol on the memory channel and transmitting the read data to the channel, and for receiving read data from the channel. 20
A prefetch buffer 5 stores a part of read data and its address as necessary, and transfers the stored data to the system bus interface 203 as needed, and the address data held therein is effective. It has a valid flag (not shown) indicating whether it is invalid or invalid. A control device 201 controls the operation timing of each block of the memory controller.

Generally, access to the memory has locality, and when data is read from a certain address in the memory, it can be expected with a high probability that the data of the subsequent addresses will be read in a short time. When a 16-byte read access is generated from the bus master 220, the memory controller 200 stores the 32-byte data including the 16-byte data existing in the succeeding address together with the data of the designated address.
It is performed from any one of 31, 322, and 233. Then, the designated 16-byte data is transferred to the bus master 220 that requested the data via the system bus 210, and the remaining 16-byte data is stored and held in the prefetch buffer 205. After that, when an access request to the subsequent address is issued from any of the bus masters, the memory controller 200 causes the DRA
The read operation for M is not performed, and instead, the data held in the prefetch buffer 205 is transferred to the bus master that issued the access request via the system bus interface 203.

For example, it is assumed that there is a read access request from the bus master 220 for 16-byte data stored at addresses'h00120 ('h represents a hexadecimal number) to'h0012f. If these addresses are assigned to the DRAM 230, the memory controller 200 accepts this request, stores it in the buffer 204 once, and then, through the memory channel interface 202, the DRA.
The read command bucket for the address of M230 is transmitted. At this time, a column packet for reading the subsequent 16 bytes of the address is also transmitted. The DRAM 2
In response to these read commands, 30 sends out a total of 32 bytes of data stored in the continuous address to the channel sequentially after a predetermined delay time.

When the memory controller 200 receives the 32-byte data sent on the channel at the memory channel interface 202, the first 16 bytes of the data are transferred from the system bus interface 203 to the system bus 210 via the system bus 210. It transmits to the bus master 220.

On the other hand, the latter half 16 bytes are stored in the prefetch buffer 205 together with the start address'h00130 and a valid flag indicating that the content of the prefetch buffer 205 is valid is set. After that, when the bus master 220 again makes a read access request for the 16-byte data stored from the address'h00130 ('h represents a hexadecimal number) to the address'h0013f, the prefetch buffer 205 is immediately stored in the prefetch buffer 205. 16 bytes of data are transmitted from the system bus interface 203 to the bus master 220 via the system bus 210. In this way, the efficiency of memory access can be improved and the read latency can be significantly reduced.

If a read access occurs and data of an arbitrary address is stored in the prefetch buffer 205, and then a write access occurs to the same address, the memory controller 200 holds the contents of the prefetch buffer 205. Invalidate. In the above example, after storing continuous 16-byte data from address “h00130” to address “h0013f” in the prefetch buffer 205, the bus master 222 issues a write request for the same address range or an address range overlapping with this address range. In this case, the memory controller 200 immediately resets the valid flag in the prefetch buffer 205. In this way, old data can be prevented from being returned to the bus master and the data can be kept consistent.

[0022]

When the prefetch buffer is added to the memory controller as described above, the circuit scale increases if a large number of entries (address and data pairs to be stored in the buffer) are provided. for that reason,
In the above example, only one entry is provided. At this time, if there is only one bus master, and the master locally accesses the data, the prefetch buffer functions effectively, but if there are multiple bus masks, and they exist in different address ranges. When accessing the prefetch buffer, the contents of the prefetch buffer are frequently replaced before being referred to, and the effectiveness of the prefetch buffer is impaired.

As an example, FIG. 3 shows two bus masters 22.
0'and 222 'are from'h10020'to'h1'
The case where address ranges from 0fff and from'h8a50 'to'h8c7f' are read continuously every 16 bytes is shown. From the first cycle, the bus master 220 issues a read access request for 16-byte data from the address “h10020” to the address “h1002f”. As a result, in the fifth cycle, the prefetch buffer 205 stores 16-byte data from the address “h10030” to the address “h1003f”.

Next, in the sixth cycle, the bus master 223 sets 1 from the address'h8a40 to the address'h8a4f.
A read access request for 6-byte data is issued. As a result, in the tenth cycle, the prefetch buffer 205 is replaced with the 16-byte data from the address “h8a50” to the address “h8a5f” without referring to the previous data.

Then, in the 11th cycle, the bus master 22
0 follows the data that was read last time.
Issue a read access request for 16-byte data up to address'h1003f. Since the data corresponding to this address does not already exist in the prefetch buffer 205, it will be read again from the memory, and the first
In 5 cycles, the contents of the prefetch buffer 205 are replaced with 16-byte data from the subsequent address'h10040 'to'h1004f'.

In the 16th cycle, the bus master 22
Following the data that 3 read last time, 'h8a50 address ~
Issue a read access request for 16-byte data up to address h8a5f. The data corresponding to this address no longer exists in the prefetch buffer 205, so it must be read again from the memory. When a plurality of bus masters operate simultaneously in this way, the prefetch buffer having only a small number of entries cannot function effectively.

The present invention has been made in view of the above problems, and an object thereof is to provide a memory control device capable of improving access efficiency and effectiveness of a prefetch buffer.

[0028]

In order to achieve the above-mentioned object, the present invention connects to a plurality of masters and, on the other hand, to a memory device via a memory bus, and according to a request from the plurality of masters, In a memory control device that performs a read operation by writing to a memory device, a prefetch buffer that performs a preceding read operation and holds the result, a unit that specifies an address range, and a read request address and an address range specification unit that holds the result Means for comparing with information, and controlling to store the result of the preceding read operation in the prefetch buffer only when the read request address is within the range designated by the address range designating means. To do.

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIG.
~ It demonstrates based on FIG.

For the sake of comparison, the same components as those shown in FIG. 2 are indicated by adding'to the numbers.

FIG. 4 differs from FIG. 2 in that an address range designation register 207 and a comparator 208 are added. The address range designation register 207 is a register that holds one set or a plurality of sets of lower limit values and upper limit values of the designated address range. As shown in FIG. 6, the comparator 208 has a gate for ANDing two comparators and their outputs for the number of sheets in the address range designated by the address range designation register 207, and a gate for ORing their outputs. Composed of. In the present embodiment, the address at the time of the read operation is compared with the address range designated by the address range designation register 207 and the comparator 2.
08, it is possible to replace the contents of the prefetch buffer 205 ′ only if it is within that range.

Now, two bus masters 220 'and 222'
Respectively read the address ranges from'h10020 'to'h10ff'and'h8a50'to'h8c7f' in units of 16 bytes continuously, and one address range'h10000 continuous to the address range designation register 207. An example of operation on the system bus will be described with reference to FIG.

From the first cycle, the bus master 220 'issues a read access request for 16-byte data from the address "h10020" to the address "h1002f". The memory controller 200 'compares the address with the lower limit'h10000' and the upper limit'h20000 of the address range designated by the address range designation register 207 in the comparator 208, and based on the result of this read operation, the contents of the prefetch buffer 205 '. Control to replace. As a result, in the fifth cycle, the prefetch buffer 205 'starts from the address'h10020' requested to'h1 'in the read access.
'H10030' ~ 'h1003' following 002f
16 bytes of data up to address f are stored.

Next, from the sixth cycle, the bus master 22
3'is 16 from'h8a50 to'h8a5f
A read access request for byte data is issued. The memory controller 200 'compares this address with the lower limit'h10000' and the upper limit'h20000 of the address range designated by the address range designation register 207 in the comparator 208, and this time, this read operation causes the prefetch buffer 205 '. Controls not to replace the contents of. As a result, the contents of the prefetch buffer 205 'are not changed by this read access.

After that, the bus master 2 starts from the 11th cycle.
20 'issues a read access request for 16-byte data from'h10030'to'h1003f'following the previously read data. Unlike the conventional example, since the data corresponding to this address still exists in the prefetch buffer 205 ', its contents are immediately transferred to the bus master 220' through the system bus 210 'in the 12th cycle.

From the 14th cycle, the address "h10040" to "h" following the data previously read by the bus master 220 '.
A read access request for 16-byte data up to address 1004f is issued. As a result, in the eighteenth cycle, the prefetch buffer 205 ′ has a value of “h1005”.
It is replaced with 16-byte data from address 0 to'h1005f. Similarly, the bus master 22
Only the address range where 0'requires reading can replace the contents of the prefetch buffer, so that the bus master 220 'can effectively use the function of the prefetch buffer.

From the 19th cycle, the bus master 22
2'is from'h10040 'to'h1005f' 3
Writing 2 bytes of data. Since this write includes the address range currently held in the prefetch buffer, the memory controller 200 'is
By issuing a packet to write 2-byte data to a specified address to the memory channel and clearing the valid flag at the same time, the prefetch buffer 205 '
Invalidates the contents of.

From the 22nd cycle, the address "h10050" to "h" following the data read last time by the bus master 220 '.
A read access request for 16-byte data up to address 1005f is issued, but the prefetch buffer 2
Since the contents of 05 'have already been invalidated, this read access reads data from the DRAM. Therefore, old data will not be passed to the bus master 220 '.

As described above, in the present embodiment, the case where the prefetch buffer has one entry has been described.
Of course, it goes without saying that the present invention can be applied to an arbitrary number of entries.

Further, in the present embodiment, the data stored in the prefetch buffer is the data stored in the subsequent address of the address for which the read request is made by the bus mask, but the address for which the read request is made is made. Alternatively, each block of 32 bytes including the above data may be used. Further, in the present embodiment, the data of the address for which the read request is made is not stored in the prefetch buffer, but all the 32-byte data including this may be stored.

In the present embodiment, for simplicity of explanation, 32
Only the read / write access in units of bytes and 16 bytes is shown, but it goes without saying that the access may be performed in a smaller size. In that case, 32-byte data including the access data may be simultaneously read from the 32-byte boundary and stored in the prefetch buffer.

In this embodiment, the contents of the prefetch buffer are invalidated when a write occurs in an address range overlapping with the data held in the prefetch buffer. It may be replaced.

In the present embodiment, the case where a direct RDRAM is used as the DRAM is taken as an example, and 32
Although the case where the bandwidth is maximized at the time of byte transfer is shown, it goes without saying that the present invention can be applied to any other type of DRAM or storage device with any suitable transfer size.

In the present embodiment, the case where the address range in which the contents of the prefetch buffer can be replaced is set has been described, but it goes without saying that an address range in which replacement is not possible may be set. Further, it goes without saying that the present invention can be applied to a case where the address range is fixed instead of being set in the register.

[0045]

As is apparent from the above description, according to the present invention, a plurality of masters are connected, and on the other hand, a memory device is connected via a memory bus, and the above-mentioned masters are connected in response to requests from the plurality of masters. In a memory control device that performs a read operation by writing to a memory device, a prefetch buffer that performs a preceding read operation and holds the result, a unit that specifies an address range, and a read request address and an address range specification unit that holds the result A means for comparing information is provided, and the result of the preceding read operation is controlled to be stored in the prefetch buffer only when the read request address is within the range designated by the address range designating means. The effect that access efficiency and the effectiveness of the prefetch buffer can be improved It is obtained.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an example of a memory access protocol on a direct RAM bus channel.

FIG. 2 is a diagram illustrating a configuration of a memory controller in a conventional example and a system including the same.

FIG. 3 is a timing diagram for explaining a read / write access timing on a system bus and contents of a prefetch buffer in a conventional example.

FIG. 4 is a diagram for explaining an embodiment of the present invention.

FIG. 5 is a timing diagram illustrating a read / write access timing on a system bus and contents of a prefetch buffer according to the embodiment of the present invention.

6 is a configuration diagram of a comparator in FIG.

[Explanation of symbols]

200 memory control device 201 control circuit 202 memory channel interface circuit 203 system bus interface circuit 204 buffer 205 prefetch buffer 210 system bus 220-223 bus master 230-233 DRAM 241 data signal line 242 row signal line 243 column signal line 244, 245 clock signal line

Claims (7)

[Claims] 1. A memory control device which is connected to a plurality of masters and, on the other hand, is connected to a memory device via a memory bus, and performs a write operation and a read operation to the memory device in response to a request from the plurality of masters. , A prefetch buffer for performing a preceding read operation and holding the result, means for designating an address range, and means for comparing the read request address with the information held by the address range designating means are provided. A memory control device which controls to store the result of the preceding read operation in the prefetch buffer only when the result is within the range designated by the address range designating means. 2. The memory control device according to claim 1, wherein the address range designating unit is capable of designating a variable address range. 3. The memory control device according to claim 1, wherein the plurality of masters are connected via a shared bus. 4. The memory control device according to claim 1, wherein the read-ahead operation is performed simultaneously with a read operation from a memory device in response to a request from the master. 5. The memory control device according to claim 1, wherein the prefetch buffer stores one or more sets of information including data, an address of the data, and a valid flag. 6. When a read request is issued from the master, the address is compared with the address information and the valid flag of the data stored in the prefetch buffer, and if possible, the data stored in the prefetch buffer is read by the master. 6. The control according to claim 5, wherein the data is returned as data, and when it is impossible, the prefetch operation is performed and the data is stored in the prefetch buffer when it is within the address range designated by the address range designating means. Memory controller. 7. A write request from the master is compared with an address and address information of data stored in a prefetch buffer, and the valid flag is changed to an invalid state as necessary. 5. The memory control device according to 5.