JP2003163586A - Signal transmission circuit, solid state imaging apparatus, camera and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal transmission circuit as a shift register, which can operate in a stable fashion even if it is used with a high-speed circuit power supply. <P>SOLUTION: At a signal transmission circuit composed of a plurality of unit circuits, pulse voltage is outputted sequentially from unit circuits according to a driving pulse, and a common pulse voltage (OUT2) is applied at the gate of discharge transistors T13 and T14, which discharge electric charge at both ends of a bootstrap capacity C11 provided at the unit circuits. According to this arrangement, electric charge at both ends of a bootstrap capacity C11 can be simultaneously discharged in high-speed, and a shift register can operate at high speed. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit which is applied to a shift register for driving a MOS image sensor, a camera, a display, etc. and can be driven at a low voltage.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a configuration example of a conventional signal transmission circuit. In FIG. 4, for convenience of explanation,
Only the three-stage portion of the multi-stage configuration is shown. This signal transmission circuit includes output transistors T12 and T2 for the next stage.
2, T32 and bootstrap capacitors C11, C21,
C31, charging transistors T11, T21, T31 for charging the bootstrap capacitance, and discharging transistor T
13, T14, T23, T24, T33, and T34, and is supplied with the power supply voltage VDD, the drive pulses V1 and V2, and the start pulse VST.

Next, the operation of the conventional signal transmission circuit thus constructed will be described.

The start pulse VST is logic "High".
When the voltage reaches the level, the first-stage charging transistor T11 is turned on, and the bootstrap capacitance C11 changes to the power supply voltage VDD.
When the charge voltage of the bootstrap capacitor C11 exceeds the threshold voltage level of the output transistor T12, the output transistor T12 in the first stage is turned on.

After that, when the drive pulse V1 of logic "High" level is input to the drain of the output transistor T12, the voltage of the drive pulse V1 and the potential difference across the bootstrap capacitor C11 are added to the gate of the output transistor T12. When the gate potential of the output transistor T12 rises above the potential of the drive pulse V1, the drive pulse V1 is used as the output pulse OUT1 from the node N12.

At the same time, the voltage of the node N12 is applied to the gate of the second-stage charging transistor T21, the transistor T21 is turned on, the bootstrap capacitance C21 is charged to the power supply voltage VDD, and the bootstrap capacitance C21. When the charging voltage of the output transistor T22 exceeds the threshold voltage level of the output transistor T22, the output transistor T of the second stage
22 turns on.

After that, when the drive pulse V2 of the logic "High" level is input to the drain of the output transistor T22, the potential of the drive pulse V2 and the potential difference between both ends of the bootstrap capacitor C21 are added to the gate of the output transistor T22. When the gate potential of the output transistor T22 rises above the potential of the drive pulse V2, the drive pulse V2 is used as the output pulse OUT2 from the node N22.

At the same time, the voltage of the node N22 is applied to the gate of the charging transistor T31 of the third stage, the charging transistor T31 is turned on, the bootstrap capacitor C31 is charged to the power supply voltage VDD, and the bootstrap capacitor C31 is charged. The charging voltage of C31 is the output transistor T32
When the threshold voltage level is exceeded, the third stage output transistor T22 is turned on.

By repeating such an operation, the signal transmission circuit further sequentially outputs the output pulse OUT3 and thereafter.

[0010]

Problems of the above-mentioned conventional signal transmission circuit will be described with reference to FIG.

FIG. 5 is a timing chart showing the pulse voltage of each part in the conventional signal transmission circuit using only NMOS. This circuit is a 5V system circuit, and the voltage amplitudes of the drive pulses V1 and V2 and the power supply voltage VDD are 5V.
The case of V is shown.

In FIG. 5, when the start pulse VST rises to 5V at time t0, the first-stage charging transistor T11 is turned on, and the bootstrap capacitance C
11 is charged toward 5V which is the power supply voltage VDD, but when the charging transistor T11 is an enhancement type NMOS, the gate of the output transistor T12 is connected due to the influence of the threshold voltage Vt of the transistor T11. The voltage VN11 of the node N11 is lower than the power source voltage VDD of 5V by ΔH0 (5V−ΔH).
0), and the output transistor T12 is turned on in this state.

Next, at time t1, when a drive pulse V1 of 5V is input to the drain of the output transistor T12, the gate of the output transistor T12 (node N11).
Is applied with a voltage HB1 obtained by adding the voltage 5V of the drive pulse V1 and the potential difference (5V-ΔH0) across the bootstrap capacitor C11, and a pulse of amplitude H1 is output from the node N12.

At the same time, the pulse voltage of the amplitude H1 of the node N12 is applied to the gate of the second-stage charging transistor T21 to turn on the charging transistor T21, but due to the influence of the threshold voltage VT of the transistor T21,
The node N to which the gate of the output transistor T22 is connected
21 is lower than the voltage H1 by ΔH1 (H1
-ΔH1), and the bootstrap capacitance C21 is charged to the voltage (H1-ΔH1).

Similarly, at times t2 and t3 as well, at time t
The operation 1 is repeated.

Thus, in the case of the conventional signal transmission circuit,
Since a voltage of less than 5 V is applied to the gate of the charging transistor at the maximum, the bootstrap capacitance can be charged only to a voltage lower than 5 V which is the power supply voltage VDD. Therefore, the voltages of the nodes N21 and N31 gradually drop, and the signal transmission circuit cannot generate the output pulse in some stages.

In particular, the operation becomes more difficult when the voltage of the power supply system of the circuit is lowered, for example, in the case of a 3V system circuit.

The present invention has been made in view of the above problems, and an object of the present invention is to enable stable operation even when the circuit power supply is operated at a high speed or a low voltage, thereby achieving high speed or low power consumption. An object of the present invention is to provide a suitable signal transmission circuit, a solid-state imaging device to which the signal transmission circuit is applied, a camera equipped with the solid-state imaging device, and a display device to which the signal transmission circuit is applied.

[0019]

In order to achieve the above object, a first signal transmission circuit according to the present invention comprises a plurality of unit circuits, and pulse voltages are sequentially output from the unit circuits according to drive pulses. A common pulse voltage is applied to the gate of a discharge transistor for discharging electric charges at both ends of a bootstrap capacitor provided in the unit circuit.

According to this structure, the electric charges at both ends of the bootstrap capacitor can be discharged simultaneously at high speed, stable operation is possible even if the circuit power supply speed is increased, and a signal transmission circuit suitable for high speed is realized. can do.

In order to achieve the above-mentioned object, the second signal transmission circuit according to the present invention is a signal transmission circuit which is composed of a plurality of unit circuits and in which pulse voltages are sequentially output from the unit circuits according to drive pulses. , The unit circuit charges the output transistor that inputs the drive pulse to the drain and outputs it as the pulse voltage from the source, the bootstrap capacitance connected between the gate and the source of the output transistor, and the bootstrap capacitance. , The source is connected to the gate of the output transistor, the drain is connected to the power supply line or the ground line or the charging pulse line, and the drain is connected to the gate of the output transistor, the gate is the output transistor in another unit circuit Malfunction connected to the output driven by the source or source output of the Characterized in that a stop transistor.

According to this configuration, the voltage between the bootstrap capacitance of the unit circuit and the charging transistor can be set to around 0 V so that no pulse voltage is output from the output transistor of the unit circuit. This prevents malfunction even when the threshold voltage of the output transistor is low,
The threshold voltage range can be widened.

In order to achieve the above object, the third signal transmission circuit according to the present invention is a signal transmission circuit which is composed of a plurality of unit circuits and in which pulse voltages are sequentially output from the unit circuits according to drive pulses. The unit circuit includes a first output transistor that inputs a driving pulse to the drain and outputs the pulse as a pulse voltage from the source, and a first bootstrap connected between the gate and the source of the first output transistor. To charge the capacitor and the first bootstrap capacitor, the source is connected to the gate of the first output transistor and the drain is connected to the power supply line, the ground line, or the charging pulse line, and one end is charged. And a second bootstrap capacitor connected to the gate of the transistor.

In order to achieve the above-mentioned object, a fourth signal transmission circuit according to the present invention is a signal transmission circuit which is composed of a plurality of unit circuits and in which pulse voltages are sequentially output from the unit circuits according to drive pulses. The unit circuit has a first output transistor that inputs a driving pulse to the drain and outputs the driving pulse as a pulse voltage from the source, and a first bootstrap capacitor connected between the gate and the source of the first output transistor. And a source connected to the gate of the first output transistor and a drain connected to the power line or the ground line or the first line to charge the first bootstrap capacitance.
A first charging transistor connected to the charging pulse line of the first charging transistor, one end connected to the gate of the first charging transistor, and the other end connected to the source of the second output transistor or the output driven by the source output. A source is connected to one end of the second bootstrap capacitor and a drain is connected to a power supply line or a ground line or a second charging pulse line for charging the second bootstrap capacitor and the second bootstrap capacitor. And a second charging transistor whose gate is connected to the source of the third output transistor or the output driven by the source output.

According to this configuration, first, the source output of the third output transistor (for example, in the unit circuit of the previous stage before) is applied to the gate of the second charging transistor, so that the second bootstrap is performed. The capacitor is charged, one end of the second bootstrap capacitor is connected to the gate of the first charging transistor, and the output of the second (for example, in the preceding unit circuit) output transistor is added to the other end, A voltage higher than the conventional voltage is applied to the gate of the first charging transistor, and the gate potential of the first charging transistor can be higher than the power supply voltage VDD. As a result, the first bootstrap capacitor can be charged to the power supply voltage VDD, and a drop in the charging voltage to the first bootstrap capacitor can be prevented.
Therefore, it is possible to prevent the output pulse voltage from gradually decreasing and the output pulse from being stopped at some stages after the number of transmission stages increases.

The fourth signal transmission circuit includes a first discharging transistor whose drain is connected to the source of the first charging transistor and a second discharging transistor whose drain is connected to the source of the second charging transistor. Is preferably provided.

Further, the fourth signal transmission circuit includes a third boot transistor connected to a terminal different from a terminal connected to the first boot transistor of the first bootstrap capacitor, and a second boot strap. It is preferable to provide a fourth discharge transistor connected to a terminal different from the terminal to which the second discharge transistor of the capacitor is connected.

In this case, the third discharge transistor and the fourth discharge transistor
It is preferable that the discharge transistors of 1 are the same transistors.

A drive pulse is preferably input to the gates of the third and fourth discharge transistors. As a result, the discharge can be stably performed by directly applying the drive pulse.

Further, it is preferable that the gates of the second discharge transistor and the third discharge transistor of the preceding stage are supplied with the source voltage of the first output transistor or an output driven by the source voltage. Thereby, the second bootstrap capacitor and the first bootstrap capacitor in the preceding stage can be discharged at the same time.

As described above, the bootstrap capacitance can be discharged by adding only four discharge transistors, and the present invention can be applied to a small-scale circuit configuration in which there is no other external input pulse.

In the fourth signal transmission circuit, it is preferable that the second output transistor is an output transistor in the unit circuit of the preceding stage, and the third output transistor is an output transistor in the unit circuit of the preceding stage.

According to this structure, by using the output of the shift register, an extra pulse applied to the gate of the charging transistor can be omitted and the circuit scale can be reduced.

It is preferable that the third and fourth signal transmission circuits include a malfunction prevention transistor having a drain connected to the gate of the first output transistor.

According to this structure, malfunction can be prevented even when the threshold voltage of the output transistor is low, and the range of the threshold voltage can be widened.

Further, the third and fourth signal transmission circuits are
It is preferable to provide a malfunction prevention transistor whose drain is connected to the gate of the first output transistor and whose gate is connected to the source of the output transistor in the previous stage.

According to this structure, since the source of the output transistor in the previous stage is connected to the gate of the malfunction prevention transistor, it is suitable for a small-scale circuit structure without other external input pulses. The invention can be applied.

In the third and fourth signal transmission circuits,
While the pulse voltage is being output to the source of the output transistor of a certain stage, the power supply voltage pulse that enables the charging transistor of the next stage and disables the charging transistor of the next stage is supplied to the drain. Is preferred. For example, when the charging transistor is composed of an NMOS, a “High” level voltage is supplied to the drain of the charging transistor of the next stage as a power supply voltage pulse, and “Lo” is supplied.
The w "level voltage is supplied to the drain of the next-stage charging transistor. When the charging transistor is composed of a PMOS, a “Low” level voltage is supplied to the drain of the charging transistor of the next stage as a power supply voltage pulse, and “Hi” is supplied.
The gh "level voltage is supplied to the drain of the next-stage charging transistor.

According to this structure, the malfunction preventing transistor can be omitted, and the circuit scale can be reduced.

Alternatively, it is preferable that the conductance of the first charging transistor is smaller than the conductance of the malfunction prevention transistor.

According to this structure, the positive terminal side of the first bootstrap capacitor can be brought closer to 0 V, and malfunction can be prevented more reliably.

In the third and fourth signal transmission circuits,
If all the transistors are NMOS transistors,
The ground potential is supplied to at least one of the sources of the first to fourth discharge transistors and the source of the malfunction prevention transistor.

Alternatively, in the third and fourth signal transmission circuits, when all the transistors are NMOS transistors, at least one of the sources of the first to fourth discharge transistors and the source of the malfunction prevention transistor is A voltage lower than the threshold voltage of the first output transistor is supplied.

In the third and fourth signal transmission circuits,
If all the transistors are PMOS transistors,
The power supply voltage is supplied to at least one of the sources of the first to fourth discharge transistors and the source of the malfunction prevention transistor.

Alternatively, in the third and fourth signal transmission circuits, when all the transistors are PMOS transistors, at least one of the sources of the first to fourth discharge transistors and the source of the malfunction prevention transistor is A voltage higher than the threshold voltage of the first output transistor is supplied.

With the above structure, the charging transistor or the output transistor can be stably kept in the off state.

In order to achieve the above-mentioned object, the solid-state image pickup device according to the present invention comprises a third or fourth signal transmission circuit.

In order to achieve the above object, a camera according to the present invention is equipped with the solid-state image pickup device according to the present invention.

In order to achieve the above object, the display device according to the present invention is characterized by including a third or fourth signal transmission circuit.

According to the above configuration, a stable operation can be guaranteed even when the circuit power supply is lowered in voltage, and the solid-state image pickup device is applied to a portable device which requires low power consumption. The effect can be exhibited in a camera equipped with it and a liquid crystal display device.

[0051]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a circuit diagram showing a configuration example of a signal transmission circuit according to the embodiment of FIG. The present embodiment is different from the conventional example shown in FIG. 4 in that the gate of the discharge transistor in the previous stage is commonly connected to the source of the output transistor in the next stage, and a common output pulse voltage is applied. Other configurations are the same as those of the conventional example of FIG. 5, and are denoted by the same reference numerals in FIG.

In FIG. 1, when the start pulse VST becomes the logic "High" level, the first charging transistor T11 for charging the first bootstrap capacitor C11 in the first stage is turned on, and the first bootstrap capacitor C11 is turned on. When the first bootstrap capacitor C11 is charged by the power supply voltage VDD and the charging voltage of the first bootstrap capacitor C11 exceeds the threshold voltage level of the output transistor T12, the first-stage output transistor T12 is turned on.

After that, when the drive pulse V1 of the logic "High" level is input to the drain of the output transistor T12, the gate of the output transistor T12 receives the voltage of the drive pulse V1 and the potential difference across the first bootstrap capacitor C11. When the gate potential of the output transistor T12 rises above the potential of the drive pulse V1, the drive pulse V1 is applied to the output node N of the first stage.
It is used from 12 as an output pulse OUT1.

At the same time, the drive pulse V1 changes to the node N1.
When output to 2, the second charging transistor T21 of the second stage whose gate is connected to the node N12 is turned on,
When the first bootstrap capacitor C21 is charged by the power supply voltage VDD and the charging voltage of the first bootstrap capacitor C21 exceeds the threshold voltage level of the output transistor T22, the second stage output transistor T22 is turned on.

After that, when the drive pulse V2 of the logic "High" level is input to the drain of the output transistor T22, the potential of the drive pulse V2 and the potential difference between both ends of the first bootstrap capacitor C21 are input to the gate of the output transistor T22. When the gate potential of the output transistor T22 rises above the potential of the drive pulse V2, the drive pulse V2 is used as the output pulse OUT2 from the output node N22 of the second stage.

Since this output pulse OUT2 is commonly applied to the gates of the first discharge transistor T13 and the second discharge transistor T14 in the first stage, when the drive pulse V2 is output to the output node N22 of the second stage. , The charges on both ends of the first bootstrap capacitor C11 are discharged at high speed and at the same time.

Here, the advantage of the signal transmission circuit according to the present embodiment is that the charges at both ends of the first bootstrap capacitor C11 are discharged at high speed and at the same time, so that stable operation is possible even if the circuit power supply is speeded up. A signal transmission circuit suitable for high speed can be realized.

At the same time, the drive pulse V2 changes to the node N2.
When it is output to 2, the third charging transistor T31 of the third stage whose gate is connected to the node N22 is turned on,
When the first bootstrap capacitor C31 is charged by the power supply voltage VDD and the charging voltage of the first bootstrap capacitor C31 exceeds the threshold voltage level of the output transistor T32, the third stage output transistor T32 is turned on.

After that, when the drive pulse V1 of the logic "High" level is input to the drain of the output transistor T32, the potential of the drive pulse V1 and the potential difference between both ends of the first bootstrap capacitor C31 are input to the gate of the output transistor T32. When the gate potential of the output transistor T32 rises above the potential of the drive pulse V1, the drive pulse V1 is used as the output pulse OUT3 from the output node N32 of the third stage.

Since this output pulse OUT3 is commonly applied to the gates of the first discharge transistor T23 and the second discharge transistor T24 in the second stage, the drive pulse V1 is output to the output node N32 in the third stage. At this time, the charges at both ends of the first bootstrap capacitor C21 in the second stage are discharged at high speed and simultaneously.

By repeating such an operation, the signal transmission circuit sequentially outputs output pulses.

Although the sources of the first and second discharge transistors are set to the ground potential (0 V),
If each source voltage has a value smaller than the threshold voltage of the output transistor, the same effect can be obtained even if it is not 0V.

(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
3 is a circuit diagram showing a configuration example of a signal transmission circuit according to the embodiment of FIG. This embodiment is different from the first embodiment in that
In the unit circuits after the second stage, the second bootstrap capacitors (C22, C32) and the second charging transistors (T25, T3) that charge the second bootstrap capacitors.
5), and a third discharge transistor (T26, T36) for discharging the electric charge at both ends of the second bootstrap capacitor,
In the unit circuits of the third and subsequent stages, the drain is connected to the positive side terminal (node N31) of the first bootstrap capacitor (C31), the gate is connected to the output node (N12) of the previous stage, and the source is grounded. A malfunction preventing transistor (T38) is added, and the positive side terminal (node N25, N35) of the second bootstrap capacitor is connected to the gate of the first charging transistor (T21, T31) in its own stage. The negative side terminal (node N12, N22) of the second bootstrap capacitor is connected to the second terminal in the next stage.
Is connected to the gates of the charging transistors (T25, T35).

In FIG. 2, when the start pulse VST2 becomes the logic "High" level, the first charging transistor T11 for charging the first bootstrap capacitor C11 in the first stage is turned on, and the first bootstrap capacitor C11 is turned on. When the first bootstrap capacitor C11 is charged by the power supply voltage VDD and the charging voltage of the first bootstrap capacitor C11 exceeds the threshold voltage level of the output transistor T12, the first-stage output transistor T12 is turned on.

Further, the start pulse VST1 is logically "H".
Then, the second charging transistor T25 that charges the second bootstrap capacitor C22 in the second stage is turned on, and the second bootstrap capacitor C22 is turned on.
22 is charged by the power supply voltage VDD.

After that, when the drive pulse V1 of the logic "High" level is input to the drain of the output transistor T12, the gate of the output transistor T12 receives the voltage of the drive pulse V1 and the potential difference across the first bootstrap capacitor C11. When the gate potential of the output transistor T12 rises above the potential of the drive pulse V1, the drive pulse V1 is applied to the output node N of the first stage.
It is used from 12 as an output pulse OUT1.

Here, the advantage of the signal transmission circuit according to the present embodiment is that the charged second bootstrap capacitor C22 is used.
At the gate of the second charging transistor T21 of the second stage connected to the node N25 of the positive side terminal, the voltage of the drive pulse V1 output to the output node N12 and the potential difference across the second bootstrap capacitor C22 are Is added and applied, and the gate potential of the first charging transistor T21 rises above the power supply voltage VDD that is the drain potential, so the first bootstrap capacitance C2 of the second stage is added.
1 can be charged to the power supply voltage VDD.

As a result, even if the first charging transistor T21 for charging the first bootstrap capacitor C21 of the second stage is an enhancement type NMOS, the first bootstrap capacitor C21 is supplied with the power supply voltage V21.
DD can be reliably charged and the output transistor T22 can be turned on.

The drive pulse V1 is applied to the output node N12.
At the same time, the second charging transistor T35 of the third stage whose gate is connected to the output node N12 is turned on, and the second bootstrap capacitor C32 of the third stage is charged.

After that, when the drive pulse V2 of the logic "High" level is input to the drain of the output transistor T22, the potential of the drive pulse V2 and the potential difference between both ends of the first bootstrap capacitor C21 are input to the gate of the output transistor T22. When the gate potential of the output transistor T22 rises above the potential of the drive pulse V2, the drive pulse V2 is used as the output pulse OUT2 from the output node N22 of the second stage.

At the same time, at the gate of the first charging transistor T31 of the third stage connected to the node N35 which is the positive terminal of the second bootstrap capacitor C32,
The voltage of the drive pulse V2 output to the output node N22 and the potential difference across the second bootstrap capacitance C32 are added and applied, and the gate potential of the first charging transistor T31 is the drain potential. VD
Since it rises above D, the first bootstrap capacitance C31 of the third stage is reliably charged to the power supply voltage VDD, and the output transistor T32 is turned on.

By repeating such an operation, the signal transmission circuit further sequentially outputs the output pulse OUT3 and thereafter.

In this way, the first bootstrap capacitance is surely supplied to the power supply voltage VD in all signal transmission stages.
Since D can be charged, a signal transmission circuit that can generate a low-voltage output pulse with no voltage drop can be realized.

As means for discharging the voltage charged in the bootstrap capacitor, in order to reduce the number of transistors and power supply in the circuit, in the case of the first bootstrap capacitor C21 in the second stage, the first discharge transistor T2.
3 is connected to the positive side terminal of the first bootstrap capacitor C21, the drain of the second discharge transistor T24 is connected to the negative side terminal of the first bootstrap capacitor C21, and the first discharge transistor T23 and The output node N32 connected to the source of the output transistor T32 in the third stage, which is the next stage, is connected to the gate of the second discharge transistor T24. Accordingly, when the drive pulse V1 is output to the output node N32 of the third stage,
The first bootstrap capacitance C21 in the second stage is discharged.

On the other hand, in the case of the second bootstrap capacitance C22 in the second stage, the third discharge transistor T2
The drain of 6 is connected to the positive terminal of the second bootstrap capacitor C22, and the gate of the third discharge transistor T26 is connected to the output transistor T22 of the second stage, which is itself.
The output node N22 connected to the source of is connected. As a result, the drive pulse V2 is applied to the output node N22 of the second stage.
Is output, the second bootstrap capacitance C22 in the second stage is discharged.

With this configuration, the first and second bootstrap capacitances can be discharged by simply adding three discharge transistors, and the signal of this embodiment can be obtained even in a small-scale circuit configuration having no other external input pulse. A transmission circuit can be realized.

Further, the malfunction preventing transistor in which the drain is connected to the plus side terminal (node N31) of the first bootstrap capacitor C31 in the third stage, the gate is connected to the output node N12 in the first stage, and the source is grounded T38 is provided. When the second bootstrap capacitor C32 in the third stage is charged, the first charging transistor T31 is turned on to some extent by the potential of the node N35. Then, since the first bootstrap capacitor C31 is charged to some extent, when the threshold voltage of the output transistor T32 is low, the output transistor T32 is slightly turned on. At this time, the output node N1 of the first stage
When the drive pulse V1 is output to 2, the drive pulse V1 may be output to the output node N32 of the third stage at the same time.

In order to prevent the drive pulse V1 from being output to the output node N32, the malfunction prevention transistor T
38 is provided to drive the drive pulse V to the output node N12 of the first stage.
When 1 is output, malfunction prevention transistor T
38 is turned on to bring the node N31 to near 0 V so that the drive pulse V1 is not output to the output node N32 of the third stage.

At this time, the conductance of the first charging transistor T31 in the third stage is made smaller than the conductance of the malfunction preventing transistor T38, so that the positive terminal side of the first bootstrap capacitor C31 is brought closer to 0V. Therefore, malfunction can be prevented more reliably.

As described above, by providing the malfunction preventing transistors in each of the third and subsequent stages and applying the output pulse of the preceding stage to the gate of the malfunction preventing transistor, the threshold voltage of the output transistor is low. Even in this case, malfunction can be prevented and the threshold voltage range can be widened.

Further, since the source of the output transistor of the previous stage is connected to the gate of the malfunction preventing transistor, the present embodiment can be used even in the case of a small-scale circuit configuration having no other external input pulse. The signal transmission circuit can be realized.

The sources of the discharge transistor and the malfunction prevention transistor are at the ground potential (0 V).
However, if each source voltage has a value smaller than the threshold voltage of the output transistor, the same effect can be obtained even if it is not 0V.

Further, since a DC voltage is applied as the power supply voltage VDD to the drains of the first and second charging transistors, a malfunction may occur and it is necessary to incorporate a malfunction preventing transistor. By applying a pulse voltage as the power supply voltage VDD to the drain of the charging transistor, malfunction can be prevented. That is, while the output voltage is being generated at the source of the output transistor, the drain of the charging transistor at the next stage is set to “Hi
The malfunction preventing transistor can be omitted by setting the drain level of the charging transistor in the next stage to the “low” level.

FIG. 3 is a timing chart showing the pulse voltage of each part in the signal transmission circuit of FIG. 2 using only NMOS. This circuit is a 3V system circuit, and the voltage amplitudes of the drive pulses V1 and V2 and the power supply voltage VDD are 3V.
The case of V is shown. However, the voltage amplitude of the start pulse VST2 is 5V, and the voltage amplitude of the start pulse VST1 is 3V.
V. Here, only the voltage amplitude of the start pulse VST2 is set to 5 V, only in the case of the first-stage first charging transistor T11 to which the start pulse VST2 is input,
Since the high voltage from the previous stage cannot be supplied, only the start pulse VST2 is driven by the first charging transistor T11 at 5V which is higher than 3V which is the voltage amplitude of the driving pulses V1 and V2. Prevents the fall, and the first bootstrap capacitance C
This is because 11 can be charged to the power supply voltage VDD of 3V.

In FIG. 3, at time t0, the voltage of the start pulse VST2 rises to 5V, and the first charging transistor T which is an enhancement type NMOS is used.
Even if there is a threshold voltage Vt of 11, the transistor T
The first bootstrap capacitor C11 is charged to 3V which is the power supply voltage VDD via 11 and the output transistor T
12 turns on.

At the same time, the voltage of the start pulse VST1 rises to 3V, and the second bootstrap capacitor C22 is charged through the second charging transistor T25.

Next, at time t1, drive pulse V1
Rises to 3V and is input to the drain of the output transistor T12, a high voltage HB1 voltage obtained by adding the voltage 3V of the drive pulse V1 and the potential difference 3V across the bootstrap capacitor C11 is applied to the gate of the output transistor T12. Therefore, the drive pulse V1 having an amplitude of 3V is surely output from the output node N12 as the output pulse OUT1.

At the same time, the high voltage HB25 of the node N25 connected to the positive side terminal of the second bootstrap capacitor C22 is input to the gate of the first charging transistor T21, turning on the transistor T21 and turning on the first charging transistor T21. The bootstrap capacitance C21 is surely charged to the power supply voltage VDD of 3V.

At this time, the node N35 is charged with a voltage lower than 3V (3V-ΔH35), and the same voltage is applied to the gate of the first charging transistor T31. In this case, the potential of the node N31 connected to the source of the first charging transistor T31 is the first charging transistor T31.
It is possible to prevent the drive pulse V1 from being output to the node N32 at time t1 by turning on the malfunction prevention transistor T38 and bringing the node N31 closer to the ground potential direction so as not to exceed the threshold voltage of 31. .

Similarly, at times t2 and t3, the operation at time t1 is repeated.

As described above, according to this embodiment, the first
Since the positive side terminal voltage of the second bootstrap capacitor is always applied to the gate of the charging transistor of, the first bootstrap capacitor can be reliably charged to the power supply voltage of 3V, and a low voltage of 3V without voltage drop. It is possible to realize a signal transmission circuit capable of generating the output pulse of.

Further, in the present embodiment, the case of the NMOS transistor has been illustrated and described, but all the PMOs are used.
Similar effects can be obtained even in the case of an S transistor.

Further, in this embodiment, the source voltage of the output transistor can be increased by increasing the amplitude by using the drive circuit.

[0095]

As described above, according to the present invention,
The bootstrap capacitor in the next stage can be charged to the power supply voltage VDD, and a drop in the charging voltage to the bootstrap capacitor can be prevented. Therefore, it is possible to prevent the output pulse voltage from gradually decreasing and the output pulse from being stopped at some stages after the number of transmission stages increases. As a result, it is possible to realize a signal transmission circuit capable of stable low voltage driving.

In addition, the signal transmission circuit uses the signal transmission circuit as a shift register in accordance with a request for realizing low voltage driving of a liquid crystal display and a MOS type image pickup device.
It realizes low voltage and is extremely useful industrially.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration example of a signal transmission circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a signal transmission circuit according to a second embodiment of the present invention.

3 is a timing chart showing pulse voltages of respective parts in the signal transmission circuit of FIG.

FIG. 4 is a circuit diagram showing a configuration example of a conventional signal transmission circuit.

5 is a timing chart showing pulse voltages of respective parts in the signal transmission circuit of FIG.

[Explanation of symbols]

C11, C21, C31 First bootstrap capacitors C22, C32 Second bootstrap capacitors OUT1, OUT2, OUT3 Output pulse (scan pulse) T11, T21, T31 First charging transistor T25, T35 Second charging transistor T12 , T22, T32 output transistors T13, T23, T33 first discharge transistors T14, T24, T34 second discharge transistors T26, T36 third discharge transistor T38 malfunction prevention transistors V1, V2 drive pulse VDD power supply voltages VST, VST1 , VST2 start pulse

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5C024 CY42 GY31 HX35 HX40 HX55                 5C080 BB05 DD08 FF12 GG14 JJ03                       JJ04                 5J055 AX02 AX14 BX16 CX30 DX12                       DX42 DX56 DX73 EX02 EX07                       EY10 EY21 EZ18 FX18 GX01                       GX04

Claims (25)

[Claims] 1. A signal transmission circuit comprising a plurality of unit circuits, in which pulse voltages are sequentially output from the unit circuits in accordance with a drive pulse, and electric charges at both ends of a bootstrap capacitance provided in the unit circuits are discharged. A signal transmission circuit in which a common pulse voltage is applied to the gate of the discharge transistor. 2. A signal transmission circuit comprising a plurality of unit circuits, wherein a pulse voltage is sequentially output from the unit circuits according to a drive pulse, wherein the unit circuit inputs the drive pulse to a drain, An output transistor that outputs from the source as a pulse voltage, a bootstrap capacitance connected between the gate and the source of the output transistor, and a source connected to the gate of the output transistor to charge the bootstrap capacitance. And a drain connected to the gate of the output transistor,
A signal transmission circuit comprising a malfunction prevention transistor whose gate is connected to a source of an output transistor in another unit circuit or an output driven by a source output. 3. A signal transmission circuit comprising a plurality of unit circuits, wherein a pulse voltage is sequentially output from the unit circuits according to a drive pulse, wherein the unit circuit inputs the drive pulse to a drain, A first output transistor that outputs a pulse voltage from a source, a first bootstrap capacitor connected between the gate and the source of the first output transistor, and to charge the first bootstrap capacitor A source connected to the gate of the first output transistor and a drain connected to a power supply line, a ground line, or a charging pulse line; and a second end having one end connected to the gate of the charging transistor.
And a bootstrap capacitor for the signal transmission circuit. 4. A signal transmission circuit comprising a plurality of unit circuits, wherein a pulse voltage is sequentially output from the unit circuits according to a drive pulse, wherein the unit circuit inputs the drive pulse to a drain, A first output transistor that outputs a pulse voltage from a source, a first bootstrap capacitor connected between the gate and the source of the first output transistor, and to charge the first bootstrap capacitor A first charge transistor whose source is connected to the gate of the first output transistor and whose drain is connected to a power supply line, a ground line, or a first charge pulse line; and one end of the first charge transistor. A first output connected to the gate and the other end connected to the source of the second output transistor or the output driven by the source output. And a source connected to one end of the second bootstrap capacitor and a drain connected to a power supply line or a ground line or a second charging pulse line for charging the second bootstrap capacitor. And a second charging transistor having a gate connected to the source of the third output transistor or the output driven by the source output. 5. The signal transmission circuit includes: a first discharge transistor having a drain connected to a source of the first charging transistor; and a second discharge transistor having a drain connected to a source of the second charging transistor. The signal transmission circuit according to claim 4, further comprising a transistor. 6. The signal transmission circuit includes a third discharge transistor connected to a terminal different from a terminal connected to the first discharge transistor of the first bootstrap capacitor, and the second boot. The signal transmission circuit according to claim 5, further comprising a fourth discharge transistor connected to a terminal different from a terminal to which the second discharge transistor of the strap capacitor is connected. 7. The third discharge transistor and the fourth discharge transistor
7. The signal transmission circuit according to claim 6, wherein the discharge transistors are the same transistor. 8. The signal transmission circuit according to claim 6, wherein the drive pulse is input to the gates of the third and fourth discharge transistors. 9. The source of the first output transistor or the output driven by the source output of the first output transistor is supplied to the gates of the second discharge transistor and the third discharge transistor of the preceding stage. Item 9. The signal transmission circuit according to any one of items 6 to 8. 10. The second output transistor is an output transistor in a unit circuit of the preceding stage, and the third output transistor
10. The signal transmission circuit according to claim 4, wherein the output transistor is an output transistor in a unit circuit of the previous stage. 11. The signal transmission circuit according to claim 3, wherein the signal transmission circuit includes a malfunction prevention transistor having a drain connected to a gate of the first output transistor. Transmission circuit. 12. The signal transmission circuit has a drain connected to the gate of the first output transistor, and a gate connected to the source of the output transistor in the unit circuit of the previous stage or an output driven by the source output. The signal transmission circuit according to claim 3, further comprising a malfunction preventing transistor. 13. In one stage, while the pulse voltage is being output from the source of the first output transistor, the first charging transistor of the next stage is made operable, and the first charging of the next next stage is performed. 13. The signal transmission circuit according to claim 3, wherein a power supply voltage pulse for disabling a transistor is supplied to the drain of the first charging transistor. 14. The signal transmission circuit according to claim 11, wherein the conductance of the first charging transistor is smaller than the conductance of the malfunction prevention transistor. 15. The transistors are all NMOS transistors, a voltage lower than a threshold voltage of the first output transistor is supplied to a source of the first discharge transistor, and a source of the second discharge transistor is supplied to the source of the first discharge transistor. 15. The signal transmission circuit according to claim 5, wherein a voltage lower than a threshold voltage of the first charging transistor is supplied. 16. The transistors are all NMOS transistors, and the source of the fourth discharging transistor is supplied with a voltage lower than the threshold voltage of the second charging transistor of the next stage. 6 to 14
The signal transmission circuit according to claim 1. 17. The signal transmission circuit according to claim 11, wherein all the transistors are NMOS transistors, and a ground voltage is supplied to a source of the malfunction prevention transistor. 18. The transistor according to claim 10, wherein all the transistors are NMOS transistors, and a voltage lower than a threshold voltage of the first output transistor is supplied to a source of the malfunction prevention transistor. 11. The signal transmission circuit according to item 11. 19. The transistors are all PMOS transistors, a source of the first discharge transistor is supplied with a voltage higher than a threshold voltage of the first output transistor, and a source of the second discharge transistor is supplied. 15. The signal transmission circuit according to claim 5, wherein a voltage higher than a threshold voltage of the first charging transistor is supplied. 20. The transistors are all PMOS transistors, and the source of the fourth discharging transistor is supplied with a voltage higher than the threshold voltage of the second charging transistor of the next stage. 6 to 14
The signal transmission circuit according to claim 1. 21. The signal transmission circuit according to claim 11, wherein all the transistors are PMOS transistors, and a power supply voltage is supplied to a source of the malfunction prevention transistor. 22. The transistor is a PMOS transistor, and a voltage higher than a threshold voltage of the first output transistor is supplied to a source of the malfunction prevention transistor. 12. The signal transmission circuit according to item 12. 23. A solid-state image pickup device comprising the signal transmission circuit according to claim 3. 24. A camera equipped with the solid-state imaging device according to claim 23. 25. A display device comprising the signal transmission circuit according to claim 3 or 4.