JP2003162959A - Manufacturing method of field emission type electron source - Google Patents

Manufacturing method of field emission type electron source

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Publication number
JP2003162959A
JP2003162959A JP2001361616A JP2001361616A JP2003162959A JP 2003162959 A JP2003162959 A JP 2003162959A JP 2001361616 A JP2001361616 A JP 2001361616A JP 2001361616 A JP2001361616 A JP 2001361616A JP 2003162959 A JP2003162959 A JP 2003162959A
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JP
Japan
Prior art keywords
electrode
lower electrode
porous
polycrystalline silicon
electron source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001361616A
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Japanese (ja)
Other versions
JP3678193B2 (en
Inventor
Tsutomu Kunugibara
勉 櫟原
Takuya Komoda
卓哉 菰田
Nobuyoshi Koshida
信義 越田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
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Priority to JP2001361616A priority Critical patent/JP3678193B2/en
Publication of JP2003162959A publication Critical patent/JP2003162959A/en
Application granted granted Critical
Publication of JP3678193B2 publication Critical patent/JP3678193B2/en
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Expired - Fee Related legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a field emission type electron source, having longer life service than that of conventional ones. <P>SOLUTION: In this manufacturing method of a field emission type electron source, at first a polycrystalline silicon layer 3 is formed on a lower electrode 12 (Fig. 1 (a)), and then a porous polycrystalline silicon layer 4 is formed by carrying an anode oxidation treatment process which makes the polycrystalline silicon layer 3 porous (Fig. 1 (b)), and further, a strong field drift layer 6 is formed by oxidizing the porous polycrystalline silicon layer 4 (Fig. 1 (c)). In the anodic oxidation treatment process using a treatment vessel filled with electrolyte, a current is made to flow between an electrode 12 and a cathode, while light emitted from an light source irradiates a surface of the polycrystalline silicon layer 3. Here, a current flowing between the electrode 12 and the cathode is made to gradually increase its current density up to a prescribed value during a time elapsed after starting, and then the current density is maintained at the prescribed value for a prescribed time, to finish energizing. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、電界放射により電
子線を放射するようにした電界放射型電子源の製造方法
に関するものである。 【0002】 【従来の技術】従来から、下部電極と、下部電極に対向
する導電性薄膜よりなる表面電極と、下部電極と表面電
極との間に介在する酸化した多孔質半導体層(多孔質シ
リコン層、多孔質多結晶シリコン層)よりなる強電界ド
リフト層とを備えた電界放射型電子源が提案されている
この種の電界放射型電子源は、例えば、図10に示すよ
うに導電性基板としてのn形シリコン基板1の主表面
(一表面)側に酸化した多孔質多結晶シリコン層よりな
る強電界ドリフト層6が形成され、強電界ドリフト層6
上に金属薄膜(例えば、金薄膜)よりなる表面電極7が
形成されている。また、n形シリコン基板1の裏面には
オーミック電極2が形成されており、n形シリコン基板
1とオーミック電極2とで下部電極12を構成してい
る。なお、図10に示す例では、n形シリコン基板1と
強電界ドリフト層6との間にノンドープの多結晶シリコ
ン層3を介在させてあるが、多結晶シリコン層3を介在
させずにn形シリコン基板1の主表面上に強電界ドリフ
ト層6を形成した構成も提案されている。 【0003】図10に示す構成の電界放射型電子源1
0’から電子を放出させるには、表面電極7に対向配置
されたコレクタ電極21を設け、表面電極7とコレクタ
電極21との間を真空とした状態で、表面電極7が下部
電極12に対して高電位側となるように表面電極7と下
部電極12との間に直流電圧Vpsを印加するとともに、
コレクタ電極21が表面電極7に対して高電位側となる
ようにコレクタ電極21と表面電極7との間に直流電圧
Vcを印加する。各直流電圧Vps,Vcを適宜に設定す
れば、下部電極12から注入された電子が強電界ドリフ
ト層6をドリフトし表面電極7を通して放出される(図
10中の一点鎖線は表面電極7を通して放出された電子
-の流れを示す)。なお、表面電極7の厚さは10〜
15nm程度に設定されている。 【0004】ところで、上述の電界放射型電子源10’
では、n形シリコン基板1とオーミック電極2とで下部
電極12を構成しているが、図11に示すように、例え
ばガラス基板よりなる絶縁性基板11の一表面上に金属
材料よりなる下部電極12を形成した電界放射型電子源
10”も提案されている。ここに、上述の図10に示し
た電界放射型電子源10’と同様の構成要素には同一の
符号を付して説明を省略する。 【0005】図11に示す構成の電界放射型電子源1
0”から電子を放出させるには、表面電極7に対向配置
されたコレクタ電極21を設け、表面電極7とコレクタ
電極21との間を真空とした状態で、表面電極7が下部
電極12に対して高電位側となるように表面電極7と下
部電極12との間に直流電圧Vpsを印加するとともに、
コレクタ電極21が表面電極7に対して高電位側となる
ようにコレクタ電極21と表面電極7との間に直流電圧
Vcを印加する。各直流電圧Vps,Vcを適宜に設定す
れば、下部電極12から注入された電子が強電界ドリフ
ト層6をドリフトし表面電極7を通して放出される(図
11中の一点鎖線は表面電極7を通して放出された電子
-の流れを示す)。なお、強電界ドリフト層6の表面
に到達した電子はホットエレクトロンであると考えら
れ、表面電極7を容易にトンネルし真空中に放出され
る。 【0006】上述の各電界放射型電子源10’,10”
では、表面電極7と下部電極12との間に流れる電流を
ダイオード電流Ipsと呼び、コレクタ電極21と表面電
極7との間に流れる電流をエミッション電流(放出電子
電流)Ieと呼ぶことにすれば(図10および図11参
照)、ダイオード電流Ipsに対するエミッション電流I
eの比率(=Ie/Ips)が大きいほど電子放出効率
(=(Ie/Ips)×100〔%〕)が高くなる。な
お、上述の電界放射型電子源10’,10”では、表面
電極7と下部電極12との間に印加する直流電圧Vpsを
10〜20V程度の低電圧としても電子を放出させるこ
とができ、直流電圧Vpsが大きいほどエミッション電流
Ieが大きくなる。 【0007】上述の電界放射型電子源10’,10”の
製造プロセスにおいて強電界ドリフト層6を形成するに
あたっては、下部電極12上にノンドープの多結晶シリ
コン層を形成した後に、該多結晶シリコン層を陽極酸化
処理にて多孔質化することで多孔質多結晶シリコン層を
形成し、多孔質多結晶シリコン層を急速熱酸化法ないし
電気化学的な方法によって酸化することにより形成され
ている。ここに、陽極酸化処理では、電解液中で下部電
極12を陽極として陽極と陰極との間に規定の電流密度
の電流を流すことによって半導体層である多結晶シリコ
ン層を多孔質化して多孔質多結晶シリコン層を形成して
いる。 【0008】また、上述の図10に示した電界放射型電
子源10’では、n形シリコン基板1上に形成した半導
体層である多結晶シリコン層を電解液を用いた陽極酸化
処理にて多孔質化しているが、単結晶のn形シリコン基
板を半導体層としてn形シリコン基板のうち表面側の部
分を陽極酸化処理にて多孔質化してから酸化することで
n形シリコン基板の表面側に強電界ドリフト層を形成し
た電界放射型電子源も提案されている。 【0009】ところで、上述の陽極酸化処理では、陽極
と陰極との間に上記規定の電流密度の電流を所定時間だ
け流すことによって半導体層の多孔質化を行っており、
陽極と陰極との間の通電の開始時に陽極と陰極との間に
流れる電流の電流密度が即時に上記規定の電流密度にな
るようにしている。 【0010】 【発明が解決しようとする課題】しかしながら、上述の
製造プロセスを採用して製造した電界放射型電子源1
0’,10”では、工業的な利用を考えた場合に寿命が
短いという不具合があった。ここにおいて、上述の電界
放射型電子源10’,10”の寿命が短い原因として
は、多結晶シリコン層を上述の陽極酸化処理にて多孔質
化して形成した多孔質多結晶シリコン層の表面に多数の
微細な孔による微細な凹凸が形成され、結果的に、強電
界ドリフト層6の表面に微細な凹凸が形成されてしま
い、強電界ドリフト層6にかかる電界の分布が面内で不
均一になって、電界集中部で劣化が加速され寿命が短く
なってしまうことが考えられる。 【0011】本発明は上記事由に鑑みて為されたもので
あり、その目的は、従来に比べて長寿命化が可能な電界
放射型電子源の製造方法を提供することにある。 【0012】 【課題を解決するための手段】請求項1の発明は、下部
電極と、下部電極の一表面側に形成された酸化若しくは
窒化若しくは酸窒化した多孔質半導体層からなる強電界
ドリフト層と、強電界ドリフト層上に形成された表面電
極とを備え、表面電極と下部電極との間に電圧を印加す
ることにより下部電極から注入された電子が強電界ドリ
フト層をドリフトし表面電極を通して放出される電界放
射型電子源の製造方法であって、前記強電界ドリフト層
の形成にあたっては、電解液中で下部電極を陽極として
陽極と陰極との間に規定の電流密度の電流を流す陽極酸
化処理にて下部電極の前記一表面側の半導体層を多孔質
化して多孔質半導体層を形成する陽極酸化処理工程と、
多孔質半導体層を酸化若しくは窒化若しくは酸窒化する
工程とを備え、前記陽極酸化処理工程では、陽極と陰極
との間に電流が流れるように通電を開始し前記電流の電
流密度を前記規定の電流密度まで時間の経過とともに次
第に増加させることを特徴とし、前記陽極酸化処理工程
では、陽極と陰極との間に電流が流れるように通電を開
始し前記電流の電流密度を前記規定の電流密度まで時間
の経過とともに次第に増加させるので、前記陽極酸化処
理工程にて形成される多孔質半導体層の最表面近傍での
多孔度が低くなり前記陽極酸化処理工程による多孔質半
導体層の表面の微細な凹凸の形成を抑制することがで
き、結果的に強電界ドリフト層の表面ラフネスが従来に
比べて小さくなり、電子放出時に強電界ドリフト層の表
面の微細な凹凸に起因した電界集中を防止することがで
きるから、従来に比べて寿命の長い電界放射型電子源を
提供することができる。 【0013】 【発明の実施の形態】本実施形態で説明する電界放射型
電子源10では、導電性基板として抵抗率が導体の抵抗
率に比較的近い単結晶のn形シリコン基板(例えば、抵
抗率が略0.01Ωcm〜0.02Ωcmの(100)
基板)を用いている。 【0014】本実施形態の電界放射型電子源10は、図
3に示すように、導電性基板たるn形シリコン基板1の
主表面側に酸化した多孔質多結晶シリコン層よりなる強
電界ドリフト層6が形成され、強電界ドリフト層6上に
表面電極7が形成され、n形シリコン基板1の裏面にオ
ーミック電極2が形成されている。なお、本実施形態で
は、n形シリコン基板1とオーミック電極2とで下部電
極12を構成している。したがって、表面電極7は下部
電極12に対向しており、下部電極12と表面電極7と
の間に強電界ドリフト層6が介在している。また、多孔
質多結晶シリコン層が多孔質半導体層を構成している。 【0015】表面電極7の材料には仕事関数の小さな材
料が採用され、表面電極7の厚さは10nmに設定され
ているが、この厚さは特に限定されるものではなく、強
電界ドリフト層6を通ってきた電子がトンネルできる厚
さであればよく、表面電極7の厚さは10〜15nm程
度に設定すればよい。 【0016】図3に示す構成の電界放射型電子源10か
ら電子を放出させるには、図4に示すように、表面電極
7に対向配置されたコレクタ電極21を設け、表面電極
7とコレクタ電極21との間を真空とした状態で、表面
電極7が下部電極12に対して高電位側となるように表
面電極7と下部電極12との間に直流電圧Vpsを印加す
るとともに、コレクタ電極21が表面電極7に対して高
電位側となるようにコレクタ電極21と表面電極7との
間に直流電圧Vcを印加する。各直流電圧Vps,Vcを
適宜に設定すれば、下部電極12から注入された電子が
強電界ドリフト層6をドリフトし表面電極7を通して放
出される(図4中の一点鎖線は表面電極7を通して放出
された電子e-の流れを示す)。 【0017】本実施形態における電界放射型電子源10
では、表面電極7と下部電極12との間に流れる電流を
ダイオード電流Ipsと呼び、コレクタ電極21と表面電
極7との間に流れる電流をエミッション電流(放出電子
電流)Ieと呼ぶことにすれば(図4参照)、ダイオー
ド電流Ipsに対するエミッション電流Ieの比率(=I
e/Ips)が大きいほど電子放出効率(=(Ie/Ip
s)×100〔%〕)が高くなる。なお、本実施形態の
電界放射型電子源10では、表面電極7と下部電極12
との間に印加する直流電圧Vpsを10〜20V程度の低
電圧としても電子を放出させることができ、直流電圧V
psが大きいほどエミッション電流Ieが大きくなる。 【0018】ところで、本実施形態における強電界ドリ
フト層6は、図5に示すように、少なくとも、n形シリ
コン基板1の主表面側(つまり、下部電極12における
表面電極7側)に列設された柱状の多結晶シリコンのグ
レイン51と、グレイン51の表面に形成された薄いシ
リコン酸化膜52と、グレイン51間に介在する多数の
ナノメータオーダのシリコン微結晶63と、各シリコン
微結晶63の表面に形成され当該シリコン微結晶63の
結晶粒径よりも小さな膜厚の絶縁膜である多数のシリコ
ン酸化膜64とから構成されると考えられる。要する
に、強電界ドリフト層6は、多結晶シリコン層の各グレ
インの表面が多孔質化し各グレインの中心部分では結晶
状態が維持されている。なお、各グレイン51は、下部
電極12の厚み方向に延びている。 【0019】したがって、本実施形態の電界放射型電子
源10では、次のようなモデルで電子放出が起こると考
えられる。すなわち、表面電極7を真空中に配置し表面
電極7と下部電極12との間に表面電極7を高電位側と
して直流電圧Vpsを印加するとともに、コレクタ電極2
1と表面電極7との間にコレクタ電極21を高電位側と
して直流電圧Vcを印加することにより、直流電圧Vps
が所定値(臨界値)に達すると、下部電極12(n形シ
リコン基板1)から強電界ドリフト層6へ熱的励起によ
り電子e-が注入される。一方、強電界ドリフト層6に
印加された電界の大部分はシリコン酸化膜64にかかる
から、注入された電子e-はシリコン酸化膜64にかか
っている強電界により加速され、強電界ドリフト層6に
おけるグレイン51の間の領域を表面に向かって図5中
の矢印の向き(図5中の上向き)へドリフトし、表面電
極7をトンネルして真空中に放出される。しかして、強
電界ドリフト層6では下部電極12から注入された電子
がシリコン微結晶63でほとんど散乱されることなく、
シリコン酸化膜64にかかっている強電界で加速されて
ドリフトし表面電極7を通して放出され(弾道型電子放
出現象)、強電界ドリフト層6で発生した熱がグレイン
51を通して放熱されるから、電子放出時にポッピング
現象が発生せず、安定して電子を放出することができる
ものと考えられる。なお、強電界ドリフト層6の表面に
到達した電子はホットエレクトロンであると考えられ、
表面電極7を容易にトンネルし真空中に放出される。 【0020】以下、本実施形態の電界放射型電子源10
の製造方法について図1を参照しながら説明する。 【0021】まず、n形シリコン基板1の裏面にオーミ
ック電極2を形成した後、n形シリコン基板1の主表面
(一表面)上に半導体層としてノンドープの多結晶シリ
コン層3を形成する成膜工程を行うことにより、図1
(a)に示すような構造が得られる。なお、多結晶シリ
コン層3の成膜方法としては、例えば、CVD法(例え
ば、LPCVD法、プラズマCVD法、触媒CVD法な
ど)やスパッタ法やCGS(Continuous Grain Silic
on)法などを採用すればよい。 【0022】ノンドープの多結晶シリコン層3を形成し
た後、電解液を用いた陽極酸化処理にて陽極酸化の対象
となる半導体層である多結晶シリコン層3を多孔質化す
る陽極酸化処理工程を行うことにより、多孔質半導体層
たる多孔質多結晶シリコン層4が形成され、図1(b)
に示すような構造が得られる。ここにおいて、陽極酸化
処理工程により形成された多孔質多結晶シリコン層4
は、多数の多結晶シリコンのグレイン51(図5参照)
および多数のシリコン微結晶63(図5参照)を含んで
いる。また、陽極酸化処理工程では、55wt%のフッ
化水素水溶液とエタノールとを略1:1で混合した混合
液からなる電解液の入った処理槽を利用しており、50
0Wのタングステンランプからなる光源により多結晶シ
リコン層3の表面に光照射を行いながら下部電極12と
白金電極よりなる陰極との間に電流を流すことで多結晶
シリコン層3を主表面からn形シリコン基板1に達する
深さまで多孔質化している。ここで、下部電極12と陰
極との間に流す電流の電流密度は図2に示すように変化
させている。すなわち、下部電極12と陰極との間に電
流が流れるように通電を開始し電流密度を規定の電流密
度I1(例えば、25mA/cm2)まで時間の経過と
ともに次第に増加させ、規定の電流密度I1の電流を規
定時間T2(例えば、3秒)だけ維持して通電を終了し
ている。なお、通電開始から電流密度I1に達する時点
までの時間T1(図2参照)は例えば1秒程度に設定す
ればよい。 【0023】上述の陽極酸化処理工程の終了した後に、
エタノールによるリンスを行ってから、多孔質多結晶シ
リコン層4を酸化する酸化工程を行うことで多孔質多結
晶シリコン層4に含まれている半導体結晶(各グレイン
51および各シリコン微結晶63)の表面に上述のシリ
コン酸化膜52,64を形成することによって、上述の
グレイン51、シリコン微結晶63、各シリコン酸化膜
52,64を含む強電界ドリフト層6が形成され、酸化
工程の後に後述の熱処理工程を行うことによって、図1
(c)に示すような構造が得られる。ここにおいて、酸
化工程では、上述の多孔質化工程の終了後にエタノール
によるリンスを行ってから、所定濃度(例えば1mol
/l=1M)の硫酸水溶液の入った処理槽を利用し、下
部電極12と白金電極よりなる陰極との間に定電圧を印
加する電気化学的な方法により各グレイン51および各
シリコン微結晶63それぞれの表面にシリコン酸化膜5
2,64を形成する。熱処理工程では、シリコン酸化膜
52,64に含まれている水分が突沸しないで除去され
るように設定した第1の設定温度および昇温速度(例え
ば20℃/sec以下)で第1の熱処理を行い、その
後、第1の設定温度よりも高くシリコン酸化膜52,6
4の構造緩和が起こるように設定した第2の設定温度で
第2の熱処理を行っている。熱処理工程では、ランプア
ニール装置を用い、第1の熱処理は、酸素ガス雰囲気
(つまり、酸化種を含む雰囲気)中で行っており、第1
の設定温度を450℃、熱処理時間を1時間に設定して
ある。また、第2の熱処理は、酸素ガス雰囲気(つま
り、酸化種を含む雰囲気)中で行っており、第2の設定
温度を900℃、熱処理時間を20分に設定してある。
また、本実施形態では、第2の熱処理として急速熱処理
法を採用しており、第1の設定温度から第2の設定温度
まで基板温度を上昇させる昇温期間の昇温速度を150
℃/secに設定してある(なお、この昇温期間の昇温
速度は20℃/sec以上に設定すればよく、150℃
/sec以上に設定することが望ましい)。 【0024】強電界ドリフト層6を形成した後は、金属
材料(例えば、金)からなる表面電極7を蒸着法などに
よって形成することにより、図1(d)に示す構造の電
界放射型電子源10が得られる。なお、本実施形態で
は、表面電極7を蒸着法により形成しているが、表面電
極7の形成方法は蒸着法に限定されるものではなく、例
えばスパッタ法を用いてもよい。 【0025】しかして、上述の製造方法によれば、陽極
酸化処理工程において、陽極である下部電極12と陰極
との間に電流が流れるように通電を開始し電流の電流密
度を規定の電流密度I1(図2参照)まで時間の経過と
ともに次第に増加させるので、陽極酸化処理工程にて形
成される多孔質半導体層たる多孔質多結晶シリコン層4
の最表面近傍での多孔度が低くなり陽極酸化処理工程に
よる多孔質多結晶シリコン層4の表面の微細な凹凸の形
成を抑制することができ、結果的に強電界ドリフト層6
の表面ラフネスが従来に比べて小さくなり、電子放出時
に強電界ドリフト層6の表面の微細な凹凸に起因した電
界集中を防止することができるから、従来に比べて寿命
の長い電界放射型電子源10を提供することができる。 【0026】図6に上述の製造方法にて製造した電界放
射型電子源10の電子放出特性の経時変化を測定した結
果を示し、図7には陽極酸化処理工程にて通電開始時に
即時に上記規定の電流密度I1の電流を流して上記規定
時間だけ維持するようにして製造した比較例の電子放出
特性の経時変化を測定した結果を示す。電界放射型電子
源10および比較例の電界放射型電子源の電子放出特性
の測定は、真空チャンバ(図示せず)内に電界放射型電
子源10ないし比較例の電界放射型電子源を導入して、
上述の図4のように、表面電極7に対向してコレクタ電
極21を配置し、表面電極7を下部電極12に対して高
電位側として直流電圧Vpsを印加するとともに、コレク
タ電極21を表面電極7に対して高電位側として直流電
圧Vcを印加することによって行った。図6,7は上述
の直流電圧Vcを100V一定、上述の直流電圧Vpsを
16V一定とし、真空チャンバ内の真空度を5×10-5
Paとしたときの電子放出特性の測定結果を示したもの
であって、各図の横軸は通電開始からの経過時間、左側
の縦軸は電流密度、右側の縦軸は電子放出効率であり、
「イ」はダイオード電流Ipsの電流密度、「ロ」はエミ
ッション電流Ieの電流密度、「ハ」は電子放出効率を
示している。図6,7から、比較例の電界放射型電子源
に比べて本実施形態の電界放射型電子源10の方が絶縁
破壊に至るまでの経過時間が長く長寿命化を図れている
ことが分かる。 【0027】ところで、本実施形態では、n形シリコン
基板1とオーミック電極2とで下部電極12を構成して
いるが、絶縁性基板(例えば、ガラス基板、セラミック
基板など)の一表面側に金属材料や高濃度ドープされた
多結晶シリコン層からなる下部電極12を形成した構成
を採用するようにしてもよい。また、n形シリコン基板
1を半導体層としてn形シリコン基板の表面側の一部を
上述の陽極酸化処理工程にて多孔質化することで多孔質
半導体層たる多結晶シリコン層を形成し、該多孔質シリ
コン層を上述の酸化工程にて酸化するようにしてもよ
い。 【0028】また、本実施形態では、強電界ドリフト層
6を酸化した多孔質多結晶シリコン層により構成してい
るが、強電界ドリフト層6を窒化した多孔質多結晶シリ
コン層や酸窒化した多孔質多結晶シリコン層により構成
してもよいし、あるいはその他の酸化若しくは窒化若し
くは酸窒化した多孔質半導体層により構成してもよい。
なお、強電界ドリフト層6を窒化した多孔質多結晶シリ
コン層とした場合には多孔質化工程により形成した多孔
質多結晶シリコン層を酸化する酸化工程の代わりに多孔
質多結晶シリコン層を窒化する窒化工程を採用すればよ
く、図5にて説明した各シリコン酸化膜52,64がい
ずれもシリコン窒化膜となり、強電界ドリフト層6を酸
窒化した多孔質多結晶シリコン層とした場合には多孔質
化工程により形成した多孔質多結晶シリコン層を酸化す
る酸化工程の代わりに多孔質多結晶シリコン層を酸窒化
する酸窒化工程を採用すればよく、図5にて説明した各
シリコン酸化膜52,64がいずれもシリコン酸窒化膜
となる。 【0029】 【発明の効果】請求項1の発明は、下部電極と、下部電
極の一表面側に形成された酸化若しくは窒化若しくは酸
窒化した多孔質半導体層からなる強電界ドリフト層と、
強電界ドリフト層上に形成された表面電極とを備え、表
面電極と下部電極との間に電圧を印加することにより下
部電極から注入された電子が強電界ドリフト層をドリフ
トし表面電極を通して放出される電界放射型電子源の製
造方法であって、前記強電界ドリフト層の形成にあたっ
ては、電解液中で下部電極を陽極として陽極と陰極との
間に規定の電流密度の電流を流す陽極酸化処理にて下部
電極の前記一表面側の半導体層を多孔質化して多孔質半
導体層を形成する陽極酸化処理工程と、多孔質半導体層
を酸化若しくは窒化若しくは酸窒化する工程とを備え、
前記陽極酸化処理工程では、陽極と陰極との間に電流が
流れるように通電を開始し前記電流の電流密度を前記規
定の電流密度まで時間の経過とともに次第に増加させる
ことを特徴とし、前記陽極酸化処理工程では、陽極と陰
極との間に電流が流れるように通電を開始し前記電流の
電流密度を前記規定の電流密度まで時間の経過とともに
次第に増加させるので、前記陽極酸化処理工程にて形成
される多孔質半導体層の最表面近傍での多孔度が低くな
り前記陽極酸化処理工程による多孔質半導体層の表面の
微細な凹凸の形成を抑制することができ、結果的に強電
界ドリフト層の表面ラフネスが従来に比べて小さくな
り、電子放出時に強電界ドリフト層の表面の微細な凹凸
に起因した電界集中を防止することができるから、従来
に比べて寿命の長い電界放射型電子源を提供することが
できるという効果がある。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a field emission type electron source which emits an electron beam by field emission. 2. Description of the Related Art Conventionally, a lower electrode, a surface electrode made of a conductive thin film facing the lower electrode, and an oxidized porous semiconductor layer (porous silicon) interposed between the lower electrode and the surface electrode. A field emission type electron source having a strong electric field drift layer comprising a layer and a porous polycrystalline silicon layer) has been proposed. This type of field emission type electron source is, for example, as shown in FIG. A strong electric field drift layer 6 made of an oxidized porous polycrystalline silicon layer is formed on the main surface (one surface) side of an n-type silicon substrate 1 as a substrate.
A surface electrode 7 made of a metal thin film (for example, a gold thin film) is formed thereon. An ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1, and the n-type silicon substrate 1 and the ohmic electrode 2 constitute a lower electrode 12. In the example shown in FIG. 10, although the non-doped polycrystalline silicon layer 3 is interposed between the n-type silicon substrate 1 and the strong electric field drift layer 6, the n-type A configuration in which a strong electric field drift layer 6 is formed on the main surface of the silicon substrate 1 has also been proposed. A field emission type electron source 1 having a configuration shown in FIG.
In order to emit electrons from 0 ′, a collector electrode 21 disposed opposite to the surface electrode 7 is provided, and a vacuum is applied between the surface electrode 7 and the collector electrode 21. DC voltage Vps is applied between the surface electrode 7 and the lower electrode 12 so that
DC voltage Vc is applied between collector electrode 21 and surface electrode 7 so that collector electrode 21 is on the higher potential side with respect to surface electrode 7. If the DC voltages Vps and Vc are appropriately set, the electrons injected from the lower electrode 12 drift in the strong electric field drift layer 6 and are emitted through the surface electrode 7 (the dashed line in FIG. Shows the flow of electrons e ). The thickness of the surface electrode 7 is 10 to
It is set to about 15 nm. The above-mentioned field emission type electron source 10 '
In this embodiment, the lower electrode 12 is composed of the n-type silicon substrate 1 and the ohmic electrode 2. As shown in FIG. 11, for example, the lower electrode 12 made of a metal material is formed on one surface of an insulating substrate 11 made of a glass substrate. A field emission type electron source 10 ″ having a 12 is also proposed. Here, the same components as those of the field emission type electron source 10 ′ shown in FIG. [0005] The field emission type electron source 1 having the structure shown in FIG.
In order to emit electrons from 0 ", a collector electrode 21 disposed opposite to the surface electrode 7 is provided, and the surface electrode 7 is DC voltage Vps is applied between the surface electrode 7 and the lower electrode 12 so that
DC voltage Vc is applied between collector electrode 21 and surface electrode 7 so that collector electrode 21 is on the higher potential side with respect to surface electrode 7. If the DC voltages Vps and Vc are appropriately set, electrons injected from the lower electrode 12 drift in the strong electric field drift layer 6 and are emitted through the surface electrode 7 (the dashed line in FIG. Shows the flow of electrons e ). The electrons that have reached the surface of the strong electric field drift layer 6 are considered to be hot electrons and are easily tunneled through the surface electrode 7 and discharged into a vacuum. The above-mentioned field emission electron sources 10 ', 10 "
Then, the current flowing between the surface electrode 7 and the lower electrode 12 is called a diode current Ips, and the current flowing between the collector electrode 21 and the surface electrode 7 is called an emission current (emission electron current) Ie. (See FIGS. 10 and 11), the emission current I with respect to the diode current Ips
The larger the ratio of e (= Ie / Ips), the higher the electron emission efficiency (= (Ie / Ips) × 100 [%]). In the field emission electron sources 10 ′ and 10 ″ described above, electrons can be emitted even when the DC voltage Vps applied between the surface electrode 7 and the lower electrode 12 is as low as about 10 to 20 V. When the DC voltage Vps is higher, the emission current Ie is larger.In forming the strong electric field drift layer 6 in the above-described process of manufacturing the field emission electron sources 10 'and 10 ", a non-doped layer is formed on the lower electrode 12. After forming the polycrystalline silicon layer, the polycrystalline silicon layer is made porous by anodizing to form a porous polycrystalline silicon layer, and the porous polycrystalline silicon layer is subjected to a rapid thermal oxidation method or an electrochemical method. It is formed by oxidation by a conventional method. Here, in the anodic oxidation treatment, a polycrystalline silicon layer which is a semiconductor layer is made porous by flowing a current having a specified current density between the anode and the cathode using the lower electrode 12 as an anode in an electrolytic solution. A polycrystalline silicon layer is formed. In the field emission type electron source 10 ′ shown in FIG. 10, the polycrystalline silicon layer, which is a semiconductor layer formed on the n-type silicon substrate 1, is porous by anodizing using an electrolytic solution. However, the surface of the n-type silicon substrate is made porous by anodizing and then oxidized by using the single-crystal n-type silicon substrate as a semiconductor layer and oxidizing the surface of the n-type silicon substrate. A field emission electron source having a strong electric field drift layer has also been proposed. By the way, in the above-described anodic oxidation treatment, the semiconductor layer is made porous by flowing a current having the above specified current density for a predetermined time between the anode and the cathode.
The current density of the current flowing between the anode and the cathode at the start of energization between the anode and the cathode is immediately adjusted to the specified current density. [0010] However, the field emission type electron source 1 manufactured by employing the above-described manufacturing process.
In the case of 0 ′, 10 ″, there was a problem that the life was short when considering industrial use. Here, the cause of the short life of the field emission electron sources 10 ′, 10 ″ was polycrystalline. Fine irregularities due to a large number of fine holes are formed on the surface of the porous polycrystalline silicon layer formed by making the silicon layer porous by the above-described anodic oxidation treatment. As a result, the surface of the strong electric field drift layer 6 is formed. It is conceivable that fine irregularities are formed, the distribution of the electric field applied to the strong electric field drift layer 6 becomes non-uniform in the plane, and the deterioration is accelerated in the electric field concentrated portion, thereby shortening the life. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a field emission type electron source that can have a longer life than conventional ones. According to a first aspect of the present invention, there is provided a strong electric field drift layer comprising a lower electrode and an oxidized, nitrided or oxynitrided porous semiconductor layer formed on one surface of the lower electrode. And a surface electrode formed on the strong electric field drift layer, and electrons injected from the lower electrode drift through the strong electric field drift layer by applying a voltage between the surface electrode and the lower electrode, and pass through the surface electrode. A method for manufacturing a field emission electron source to be emitted, wherein in forming the strong electric field drift layer, an anode having a specified current density flowing between an anode and a cathode in an electrolyte with a lower electrode serving as an anode. Anodizing treatment step of forming a porous semiconductor layer by making the semiconductor layer on the one surface side of the lower electrode porous by oxidation treatment,
Oxidizing, nitriding, or oxynitriding the porous semiconductor layer. In the anodizing step, energization is started so that a current flows between the anode and the cathode, and the current density of the current is increased to the specified current. Characterized in that the density gradually increases with time, and in the anodizing treatment step, energization is started so that a current flows between the anode and the cathode, and the current density of the current is reduced until the specified current density. Gradually increases with the passage of time, so that the porosity near the outermost surface of the porous semiconductor layer formed in the anodic oxidation treatment step is reduced, and fine irregularities on the surface of the porous semiconductor layer due to the anodic oxidation treatment step are reduced. As a result, the surface roughness of the strong electric field drift layer becomes smaller than that of the conventional device, and the surface of the strong electric field drift layer is caused by fine irregularities during electron emission. Since the the electric field concentration can be prevented, it is possible to provide a long field emission electron source of life as compared with the prior art. DESCRIPTION OF THE PREFERRED EMBODIMENTS In a field emission type electron source 10 described in this embodiment, a single-crystal n-type silicon substrate (for example, a resistor) having a resistivity relatively close to that of a conductor is used as a conductive substrate. (100) with a rate of approximately 0.01 Ωcm to 0.02 Ωcm
Substrate). As shown in FIG. 3, a field emission type electron source 10 according to the present embodiment has a strong electric field drift layer made of an oxidized porous polycrystalline silicon layer on the main surface side of an n-type silicon substrate 1 as a conductive substrate. 6, a surface electrode 7 is formed on the strong electric field drift layer 6, and an ohmic electrode 2 is formed on the back surface of the n-type silicon substrate 1. In this embodiment, the lower electrode 12 is composed of the n-type silicon substrate 1 and the ohmic electrode 2. Therefore, the surface electrode 7 faces the lower electrode 12, and the strong electric field drift layer 6 is interposed between the lower electrode 12 and the surface electrode 7. Further, the porous polycrystalline silicon layer forms a porous semiconductor layer. A material having a small work function is adopted as the material of the surface electrode 7, and the thickness of the surface electrode 7 is set to 10 nm. However, the thickness is not particularly limited. The thickness of the surface electrode 7 may be set to about 10 to 15 nm as long as the electron passing through 6 can be tunneled. In order to emit electrons from the field emission type electron source 10 having the structure shown in FIG. 3, a collector electrode 21 disposed opposite to the surface electrode 7 is provided as shown in FIG. 21 and a DC voltage Vps is applied between the surface electrode 7 and the lower electrode 12 so that the surface electrode 7 is on the higher potential side with respect to the lower electrode 12. Is applied between the collector electrode 21 and the surface electrode 7 so that the voltage Vc is on the high potential side with respect to the surface electrode 7. If the DC voltages Vps and Vc are appropriately set, the electrons injected from the lower electrode 12 drift in the strong electric field drift layer 6 and are emitted through the surface electrode 7 (the dashed line in FIG. Shows the flow of electrons e ). The field emission type electron source 10 according to this embodiment
Then, the current flowing between the surface electrode 7 and the lower electrode 12 is called a diode current Ips, and the current flowing between the collector electrode 21 and the surface electrode 7 is called an emission current (emission electron current) Ie. (See FIG. 4), the ratio of the emission current Ie to the diode current Ips (= I
e / Ips), the electron emission efficiency (= (Ie / Ip)
s) × 100 [%]). In the field emission type electron source 10 of the present embodiment, the surface electrode 7 and the lower electrode 12
Can emit electrons even when the DC voltage Vps applied between them is as low as about 10 to 20 V.
The emission current Ie increases as ps increases. As shown in FIG. 5, the strong electric field drift layer 6 in this embodiment is arranged at least on the main surface side of the n-type silicon substrate 1 (ie, on the surface electrode 7 side of the lower electrode 12). Columnar polycrystalline silicon grains 51, a thin silicon oxide film 52 formed on the surfaces of the grains 51, a number of nanometer-order silicon microcrystals 63 interposed between the grains 51, and a surface of each silicon microcrystal 63. And a large number of silicon oxide films 64 which are insulating films having a thickness smaller than the crystal grain size of the silicon microcrystal 63. In short, in the strong electric field drift layer 6, the surface of each grain of the polycrystalline silicon layer is made porous, and the crystalline state is maintained at the center of each grain. Each of the grains 51 extends in the thickness direction of the lower electrode 12. Therefore, in the field emission type electron source 10 of the present embodiment, it is considered that electron emission occurs in the following model. That is, the surface electrode 7 is arranged in a vacuum, the DC voltage Vps is applied between the surface electrode 7 and the lower electrode 12 with the surface electrode 7 on the high potential side, and the collector electrode 2
By applying the DC voltage Vc between the first electrode 1 and the surface electrode 7 with the collector electrode 21 on the high potential side, the DC voltage Vps
Reaches a predetermined value (critical value), electrons e are injected from lower electrode 12 (n-type silicon substrate 1) into strong electric field drift layer 6 by thermal excitation. On the other hand, most of the electric field applied to the strong electric field drift layer 6 is applied to the silicon oxide film 64, so that the injected electrons e are accelerated by the strong electric field applied to the silicon oxide film 64, and 5 drifts toward the surface in the direction between the grains 51 in the direction of the arrow in FIG. 5 (upward in FIG. 5), and tunnels through the surface electrode 7 and is discharged into a vacuum. In the strong electric field drift layer 6, electrons injected from the lower electrode 12 are hardly scattered by the silicon microcrystal 63,
The electron is accelerated by the strong electric field applied to the silicon oxide film 64, drifts and is emitted through the surface electrode 7 (ballistic electron emission phenomenon), and the heat generated in the strong electric field drift layer 6 is radiated through the grains 51, so that electron emission is performed. It is considered that the popping phenomenon does not sometimes occur and electrons can be stably emitted. The electrons that have reached the surface of the strong electric field drift layer 6 are considered to be hot electrons.
The surface electrode 7 is easily tunneled and released into a vacuum. Hereinafter, the field emission type electron source 10 of this embodiment will be described.
Will be described with reference to FIG. First, an ohmic electrode 2 is formed on the back surface of an n-type silicon substrate 1, and then a non-doped polycrystalline silicon layer 3 is formed as a semiconductor layer on the main surface (one surface) of the n-type silicon substrate 1. By performing the process, FIG.
The structure as shown in FIG. As a method for forming the polycrystalline silicon layer 3, for example, a CVD method (for example, an LPCVD method, a plasma CVD method, a catalytic CVD method, etc.), a sputtering method, or a CGS (Continuous Grain Silicate) is used.
on) method or the like. After the non-doped polycrystalline silicon layer 3 is formed, an anodic oxidation step of making the polycrystalline silicon layer 3 which is a semiconductor layer to be anodized porous by anodizing using an electrolytic solution is performed. As a result, a porous polycrystalline silicon layer 4 as a porous semiconductor layer is formed.
The structure as shown in FIG. Here, the porous polycrystalline silicon layer 4 formed by the anodic oxidation process
Is a large number of polycrystalline silicon grains 51 (see FIG. 5).
And a number of silicon microcrystals 63 (see FIG. 5). In the anodizing step, a processing tank containing an electrolytic solution composed of a mixture of a 55 wt% aqueous solution of hydrogen fluoride and ethanol in a ratio of about 1: 1 is used.
A current is passed between the lower electrode 12 and the cathode composed of a platinum electrode while irradiating light to the surface of the polycrystalline silicon layer 3 with a light source composed of a 0 W tungsten lamp so that the polycrystalline silicon layer 3 is n-type from the main surface. It is made porous to a depth reaching the silicon substrate 1. Here, the current density of the current flowing between the lower electrode 12 and the cathode is changed as shown in FIG. That is, energization is started so that a current flows between the lower electrode 12 and the cathode, and the current density is gradually increased to a specified current density I1 (for example, 25 mA / cm 2 ) with the passage of time. Is maintained for the specified time T2 (for example, 3 seconds), and the energization is terminated. The time T1 (see FIG. 2) from the start of energization to the time when the current density reaches I1 may be set to, for example, about 1 second. After the above-described anodizing step is completed,
After rinsing with ethanol, an oxidation step of oxidizing the porous polycrystalline silicon layer 4 is performed, whereby semiconductor crystals (each grain 51 and each silicon microcrystal 63) included in the porous polycrystalline silicon layer 4 are removed. By forming the silicon oxide films 52 and 64 on the surface, the strong electric field drift layer 6 including the grains 51, the silicon microcrystals 63, and the silicon oxide films 52 and 64 is formed. By performing the heat treatment step, FIG.
The structure as shown in (c) is obtained. Here, in the oxidation step, after rinsing with ethanol after the completion of the above-described porous step, a predetermined concentration (for example, 1 mol
/ L = 1M) using a treatment tank containing an aqueous solution of sulfuric acid, and applying each of the grains 51 and each of the silicon microcrystals 63 by an electrochemical method of applying a constant voltage between the lower electrode 12 and the cathode made of a platinum electrode. Silicon oxide film 5 on each surface
2, 64 are formed. In the heat treatment step, the first heat treatment is performed at a first set temperature and a temperature increasing rate (for example, 20 ° C./sec or less) set so that moisture contained in the silicon oxide films 52 and 64 is removed without bumping. After that, the silicon oxide films 52 and 6 are heated to a temperature higher than the first set temperature.
The second heat treatment is performed at the second set temperature set so that the structural relaxation of No. 4 occurs. In the heat treatment step, the first heat treatment is performed in an oxygen gas atmosphere (that is, an atmosphere containing an oxidizing species) using a lamp annealing apparatus.
Is set at 450 ° C. and the heat treatment time is set at 1 hour. The second heat treatment is performed in an oxygen gas atmosphere (that is, an atmosphere containing an oxidizing species), the second set temperature is set to 900 ° C., and the heat treatment time is set to 20 minutes.
Further, in this embodiment, a rapid heat treatment method is employed as the second heat treatment, and the heating rate during the heating period in which the substrate temperature is increased from the first set temperature to the second set temperature is set to 150.
° C / sec (the heating rate during this heating period may be set to 20 ° C / sec or more;
/ Sec or more is desirable). After the strong electric field drift layer 6 is formed, a surface electrode 7 made of a metal material (for example, gold) is formed by a vapor deposition method or the like, so that the field emission type electron source having the structure shown in FIG. 10 is obtained. In the present embodiment, the surface electrode 7 is formed by a vapor deposition method, but the method of forming the surface electrode 7 is not limited to the vapor deposition method, and for example, a sputtering method may be used. According to the above-described manufacturing method, in the anodic oxidation step, energization is started so that a current flows between the lower electrode 12 serving as the anode and the cathode, and the current density of the current is adjusted to the specified current density. I1 (see FIG. 2) gradually increases with time, so that the porous polycrystalline silicon layer 4 as a porous semiconductor layer formed in the anodic oxidation step is formed.
Of the porous polycrystalline silicon layer 4 due to the anodic oxidation process can be suppressed, and as a result, the strong electric field drift layer 6 can be prevented.
Of the field emission type electron source having a longer life than the conventional one because the surface roughness of the electron source can be reduced as compared with the prior art, and the electric field concentration caused by the minute unevenness on the surface of the strong electric field drift layer 6 during electron emission can be prevented. 10 can be provided. FIG. 6 shows the results of measuring the change over time in the electron emission characteristics of the field emission electron source 10 manufactured by the above-described manufacturing method. FIG. 7 shows the results immediately after the start of energization in the anodizing step. The result of measuring the change over time of the electron emission characteristics of a comparative example manufactured by supplying a current of a specified current density I1 and maintaining the current for the specified time is shown. The electron emission characteristics of the field emission type electron source 10 and the field emission type electron source of the comparative example are measured by introducing the field emission type electron source 10 or the field emission type electron source of the comparison example into a vacuum chamber (not shown). hand,
As shown in FIG. 4 described above, the collector electrode 21 is arranged to face the surface electrode 7, the DC voltage Vps is applied while the surface electrode 7 is on the high potential side with respect to the lower electrode 12, and the collector electrode 21 is 7 was performed by applying a DC voltage Vc as the high potential side. 6 and 7 show that the above-mentioned DC voltage Vc is constant at 100 V, the above-mentioned DC voltage Vps is constant at 16 V, and the degree of vacuum in the vacuum chamber is 5 × 10 −5.
It shows the measurement results of the electron emission characteristics when Pa, the horizontal axis of each figure is the elapsed time from the start of energization, the left vertical axis is the current density, the right vertical axis is the electron emission efficiency. ,
“A” indicates the current density of the diode current Ips, “B” indicates the current density of the emission current Ie, and “C” indicates the electron emission efficiency. From FIGS. 6 and 7, it can be seen that the field emission electron source 10 of the present embodiment has a longer elapsed time until dielectric breakdown and a longer life than the field emission electron source of the comparative example. . In the present embodiment, the lower electrode 12 is composed of the n-type silicon substrate 1 and the ohmic electrode 2. However, a metal surface is provided on one surface side of an insulating substrate (eg, a glass substrate, a ceramic substrate, etc.). A configuration in which the lower electrode 12 made of a material or a highly doped polycrystalline silicon layer may be employed. Further, a part of the surface side of the n-type silicon substrate is made porous by using the n-type silicon substrate 1 as a semiconductor layer in the above-described anodic oxidation process to form a polycrystalline silicon layer as a porous semiconductor layer. The porous silicon layer may be oxidized in the above-described oxidation step. In this embodiment, the strong electric field drift layer 6 is constituted by an oxidized porous polycrystalline silicon layer. However, the strong electric field drift layer 6 is formed by nitriding the porous polycrystalline silicon layer or the oxynitrided porous polycrystalline silicon layer. It may be composed of a polycrystalline silicon layer, or may be composed of another oxidized, nitrided or oxynitrided porous semiconductor layer.
When the strong electric field drift layer 6 is a nitrided porous polycrystalline silicon layer, the porous polycrystalline silicon layer is nitrided instead of the oxidation step of oxidizing the porous polycrystalline silicon layer formed in the porous process. In the case where each of the silicon oxide films 52 and 64 described with reference to FIG. 5 is a silicon nitride film and the strong electric field drift layer 6 is a porous polycrystalline silicon layer oxynitrided, An oxynitriding step of oxynitriding the porous polycrystalline silicon layer may be employed instead of the oxidizing step of oxidizing the porous polycrystalline silicon layer formed in the porous forming step, and each silicon oxide film described with reference to FIG. Both 52 and 64 become silicon oxynitride films. According to the first aspect of the present invention, there is provided a lower electrode, a strong electric field drift layer formed of an oxidized, nitrided or oxynitrided porous semiconductor layer formed on one surface side of the lower electrode,
A surface electrode formed on the strong electric field drift layer, and by applying a voltage between the surface electrode and the lower electrode, electrons injected from the lower electrode drift in the strong electric field drift layer and are emitted through the surface electrode. A method of manufacturing a field emission type electron source, wherein the strong electric field drift layer is formed by anodizing treatment in which a current having a specified current density is passed between an anode and a cathode with a lower electrode serving as an anode in an electrolytic solution. An anodic oxidation step of forming a porous semiconductor layer by making the semiconductor layer on the one surface side of the lower electrode porous, and a step of oxidizing or nitriding or oxynitriding the porous semiconductor layer,
In the anodic oxidation step, current is started so that a current flows between the anode and the cathode, and the current density of the current is gradually increased with the passage of time to the specified current density. In the processing step, current is started so that a current flows between the anode and the cathode, and the current density of the current is gradually increased with the passage of time to the specified current density. The porosity in the vicinity of the outermost surface of the porous semiconductor layer becomes low, and the formation of fine irregularities on the surface of the porous semiconductor layer due to the anodic oxidation step can be suppressed. As a result, the surface of the strong electric field drift layer Roughness is smaller than before, and it is possible to prevent electric field concentration due to fine irregularities on the surface of the strong electric field drift layer during electron emission, so that the life is longer than before. There is an effect that it is possible to provide a field emission electron source.

【図面の簡単な説明】 【図1】実施形態の電界放射型電子源の製造方法を説明
するための主要工程断面図である。 【図2】同上の製造方法の説明図である。 【図3】同上の電界放射型電子源の概略断面図である。 【図4】同上の動作説明図である。 【図5】同上の動作説明図である。 【図6】同上の電界放射型電子源の電子放出特性図であ
る。 【図7】同上の比較例を示す電界放射型電子源の電子放
出特性図である。 【図8】従来例を示す電界放射型電子源の動作説明図で
ある。 【図9】他の従来例を示す電界放射型電子源の動作説明
図である。 【符号の説明】 1 n形シリコン基板 2 オーミック電極 3 多結晶シリコン層 4 多孔質多結晶シリコン層 6 強電界ドリフト層 7 表面電極 10 電界放射型電子源 12 下部電極
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a main process sectional view for describing a method of manufacturing a field emission electron source according to an embodiment. FIG. 2 is an explanatory diagram of a manufacturing method according to the embodiment. FIG. 3 is a schematic cross-sectional view of the field emission electron source according to the first embodiment. FIG. 4 is an operation explanatory diagram of the above. FIG. 5 is an operation explanatory view of the above. FIG. 6 is an electron emission characteristic diagram of the field emission electron source of the above. FIG. 7 is an electron emission characteristic diagram of the field emission type electron source showing the comparative example. FIG. 8 is an operation explanatory diagram of a field emission type electron source showing a conventional example. FIG. 9 is an operation explanatory view of a field emission type electron source showing another conventional example. [Description of Signs] 1 n-type silicon substrate 2 ohmic electrode 3 polycrystalline silicon layer 4 porous polycrystalline silicon layer 6 strong electric field drift layer 7 surface electrode 10 field emission electron source 12 lower electrode

フロントページの続き (72)発明者 越田 信義 東京都小平市上水本町6−5−10−203Continuation of front page    (72) Inventor Nobuyoshi Koshida             6-5-10-203, Josuihoncho, Kodaira-shi, Tokyo

Claims (1)

【特許請求の範囲】 【請求項1】 下部電極と、下部電極の一表面側に形成
された酸化若しくは窒化若しくは酸窒化した多孔質半導
体層からなる強電界ドリフト層と、強電界ドリフト層上
に形成された表面電極とを備え、表面電極と下部電極と
の間に電圧を印加することにより下部電極から注入され
た電子が強電界ドリフト層をドリフトし表面電極を通し
て放出される電界放射型電子源の製造方法であって、前
記強電界ドリフト層の形成にあたっては、電解液中で下
部電極を陽極として陽極と陰極との間に規定の電流密度
の電流を流す陽極酸化処理にて下部電極の前記一表面側
の半導体層を多孔質化して多孔質半導体層を形成する陽
極酸化処理工程と、多孔質半導体層を酸化若しくは窒化
若しくは酸窒化する工程とを備え、前記陽極酸化処理工
程では、陽極と陰極との間に電流が流れるように通電を
開始し前記電流の電流密度を前記規定の電流密度まで時
間の経過とともに次第に増加させることを特徴とする電
界放射型電子源の製造方法。
Claims: 1. A lower electrode, a strong electric field drift layer formed of an oxidized, nitrided, or oxynitrided porous semiconductor layer formed on one surface side of the lower electrode; A field emission type electron source comprising a formed surface electrode, and by applying a voltage between the surface electrode and the lower electrode, electrons injected from the lower electrode drift in the strong electric field drift layer and are emitted through the surface electrode. In the method of forming the strong electric field drift layer, the lower electrode is formed by anodizing treatment in which a current having a specified current density is passed between the anode and the cathode using the lower electrode as an anode in an electrolytic solution. An anodic oxidation step of forming a porous semiconductor layer by making the semiconductor layer on one surface porous, and a step of oxidizing, nitriding, or oxynitriding the porous semiconductor layer; Producing a field emission type electron source, wherein current is started so that a current flows between the anode and the cathode, and the current density of the current is gradually increased to the specified current density with the passage of time. Method.
JP2001361616A 2001-11-27 2001-11-27 Manufacturing method of field emission electron source Expired - Fee Related JP3678193B2 (en)

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JP3678193B2 JP3678193B2 (en) 2005-08-03

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