JP2003158157A - Method of ic-mounting for semiconductor device - Google Patents

Method of ic-mounting for semiconductor device

Info

Publication number
JP2003158157A
JP2003158157A JP2001359001A JP2001359001A JP2003158157A JP 2003158157 A JP2003158157 A JP 2003158157A JP 2001359001 A JP2001359001 A JP 2001359001A JP 2001359001 A JP2001359001 A JP 2001359001A JP 2003158157 A JP2003158157 A JP 2003158157A
Authority
JP
Japan
Prior art keywords
resin
circuit board
mounting
semiconductor device
tab tape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001359001A
Other languages
Japanese (ja)
Inventor
Tadahiro Higaki
忠宏 桧垣
Fuminori Mihashi
史典 三橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindo Denshi Kogyo KK
Original Assignee
Shindo Denshi Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindo Denshi Kogyo KK filed Critical Shindo Denshi Kogyo KK
Priority to JP2001359001A priority Critical patent/JP2003158157A/en
Priority to TW091121898A priority patent/TW557485B/en
Priority to KR1020020064760A priority patent/KR20030043624A/en
Publication of JP2003158157A publication Critical patent/JP2003158157A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26122—Auxiliary members for layer connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/26145—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/2901—Shape
    • H01L2224/29012—Shape in top view
    • H01L2224/29015—Shape in top view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PROBLEM TO BE SOLVED: To provide a method of IC-mounting in a semiconductor device, which stabilizes the coating amount of resin to eliminate flowing to the backside and to form a good fillet shape, reduces the coating time, and suppresses generation of air bubbles by preventing inflow of air. SOLUTION: After protective resin 17 is collectively applied to a TAB tape 10 (a circuit substrate) by printing, an IC 15 is attached on each applied position to flip-chip-bond the IC to the TAB tape. It is preferable to form a step at the circumference of the IC, and to flip-chip-bond the IC to the TAB tape so that the step faces the TAB tape, wherein the depth of the step is 1/2 to 2/3 the thickness of the IC. The protective resin is coated on the circuit substrate by, for example, screen printing.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】この発明は、半導体装置にお
いて、回路基板上にＩＣをフリップチップ接合するＩＣ
実装方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which an IC is flip-chip bonded onto a circuit board.
Regarding the implementation method.

【０００２】[0002]

【従来の技術】従来、半導体装置では、例えば図５
（Ａ）に示すように回路基板１上に形成した回路パター
ン２の配線電極３にＩＣ４表面の金属電極５を熱圧着に
より接合し、空気圧により不図示のピストンを移動して
（Ｂ）に示すようにディスペンサ６内の樹脂７を滴下
し、回路基板１とＩＣ４間に樹脂７を複数回に分けて充
填して後、充填した樹脂７を硬化して（Ｃ）に示すよう
に富士山の裾野のごとく接触角をほとんど持たないフィ
レット形状としていた。2. Description of the Related Art Conventionally, in a semiconductor device, for example, FIG.
As shown in (A), the metal electrode 5 on the surface of the IC 4 is bonded to the wiring electrode 3 of the circuit pattern 2 formed on the circuit board 1 by thermocompression bonding, and a piston (not shown) is moved by air pressure to show it in (B). In this way, the resin 7 in the dispenser 6 is dropped, and the resin 7 is filled between the circuit board 1 and the IC 4 in plural times, and the filled resin 7 is cured, as shown in (C). The fillet shape has almost no contact angle.

【０００３】そして、これにより回路基板１とＩＣ４間
の応力を緩和するとともに、パッケージを保護し、また
電気的に確実に絶縁していた。Thus, the stress between the circuit board 1 and the IC 4 is relieved, the package is protected, and the electrical insulation is ensured.

【０００４】[0004]

【発明が解決しようとする課題】ところが、このような
半導体装置では、回路基板１とＩＣ４間に確実に流し込
むようにすることから、保護樹脂７としては比較的粘性
の低い材料を用い、しかも空気が入らないようにしなけ
ればならないことから、注入方法も工夫しなければなら
ず、樹脂７を適量に充填することが非常に難しく、充填
量が安定しなかった。However, in such a semiconductor device, since the resin is surely poured between the circuit board 1 and the IC 4, a material having a relatively low viscosity is used as the protective resin 7 and air is used. Since it must be prevented from entering, the injection method also had to be devised, and it was very difficult to fill the resin 7 in an appropriate amount, and the filling amount was not stable.

【０００５】そして、充填量が少なすぎると、例えば図
６に示すように良好なフィレット形状を形成することが
できず、応力を十分に緩和できなかったり、パッケージ
の保護が不十分となったり、最悪の場合には絶縁が不十
分となったりする問題があった。他方、多くなりすぎる
と、例えば図７に示すように、保護樹脂７がＩＣ４の裏
側にまで周り込む、いわゆる裏周りｐを生ずる問題があ
った。If the filling amount is too small, for example, a good fillet shape cannot be formed as shown in FIG. 6, the stress cannot be sufficiently relieved, or the package is not sufficiently protected. In the worst case, there was a problem of insufficient insulation. On the other hand, if the number is too large, for example, as shown in FIG. 7, there is a problem in that the protective resin 7 wraps around to the back side of the IC 4, so-called back side p.

【０００６】ディスペンサではじめに回路基板1上に樹
脂７を塗布してから、ＩＣ４を取り付けることもできる
が、このような場合に樹脂７の塗布量が多くなると、そ
の後ＩＣ４を取り付けたときに裏周りを生じて、例えば
図８に示すようにボンディングツール８を用いて熱圧着
するときそのボンディングツール８に樹脂７が付着し、
装置の駆動を一時的に止めてその付着した樹脂７を砥石
等を用いて除去しなければならない面倒があった。Although it is possible to first apply the resin 7 onto the circuit board 1 with a dispenser and then attach the IC 4, if the resin 7 is applied in such a large amount in such a case, the back surface of the IC 4 is attached when the IC 4 is attached. Occurs, for example, when thermocompression bonding is performed using the bonding tool 8 as shown in FIG. 8, the resin 7 adheres to the bonding tool 8,
There has been a trouble that the driving of the apparatus should be temporarily stopped and the resin 7 attached thereto should be removed by using a grindstone or the like.

【０００７】特にＩＣ４の厚さが４００μｍ以下の場
合、裏周りの発生を避けるため、樹脂７の塗布量を少な
くすると、フィレットが十分に形成されない傾向にあっ
た。Particularly, when the thickness of the IC 4 is 400 μm or less, the fillet tends to be insufficiently formed if the coating amount of the resin 7 is reduced in order to avoid the occurrence of the back side.

【０００８】加えて、図５に示すような従来のＩＣ実装
方法では、ディスペンサ６で樹脂７を複数回に分けて塗
布するから、塗布時間がかかるとともに、特に樹脂７の
粘性が高いときには空気が入り易い問題があった。In addition, in the conventional IC mounting method as shown in FIG. 5, since the dispenser 6 applies the resin 7 in a plurality of divided operations, it takes a long time to apply the resin, and when the viscosity of the resin 7 is high, the air will not flow. There was a problem that it was easy to enter.

【０００９】そこで、この発明の目的は、半導体装置の
ＩＣ実装方法において、樹脂の塗布量を安定して裏周り
の発生を解消するとともに良好なフィレット形状を形成
し、また塗布時間を短縮する一方、空気の流入を防いで
気泡の発生を抑制することにある。Therefore, an object of the present invention is, in an IC mounting method for a semiconductor device, to stabilize the amount of resin applied, eliminate the occurrence of the backing area, form a good fillet shape, and shorten the application time. The purpose is to prevent the inflow of air and suppress the generation of bubbles.

【００１０】[0010]

【課題を解決するための手段】そこで、この発明は、か
かる目的を達成すべく、半導体装置のＩＣ実装方法にあ
って、回路基板上に保護樹脂を印刷により一括塗布して
後、その塗布位置にＩＣを取り付けてそのＩＣを回路基
板上にフリップチップ接合してなる、ことを特徴とす
る。In order to achieve the above object, the present invention provides an IC mounting method for a semiconductor device, wherein a protective resin is collectively applied by printing on a circuit board, and then the application position is applied. It is characterized in that an IC is attached to and the IC is flip-chip bonded onto a circuit board.

【００１１】ＩＣは、外周に段部を形成し、その段部が
回路基板と対向する向きとなるように回路基板上にフリ
ップチップ接合するとよく、そのとき段部の深さは、Ｉ
Ｃの厚さの１／２〜２／３とするとよい。また、保護樹
脂は、回路基板上に例えばスクリーン印刷で塗布する。The IC is preferably flip-chip bonded on the circuit board such that a step portion is formed on the outer periphery and the step portion faces the circuit board. At this time, the depth of the step portion is I.
It is good to set it to 1/2 to 2/3 of the thickness of C. The protective resin is applied on the circuit board by screen printing, for example.

【００１２】[0012]

【発明の実施の形態】以下、図面を参照しつつ、この発
明の実施の形態につき説明する。図１にはこの発明によ
る半導体装置におけるＩＣ実装方法を示し、（Ａ）はＩ
Ｃ実装前、（Ｂ）はＩＣ実装後である。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an IC mounting method in a semiconductor device according to the present invention.
Before C mounting, (B) is after IC mounting.

【００１３】図中符号１０は、回路基板であるＴＡＢテ
ープで、ポリイミド樹脂等の絶縁フィルム基材１１の表
面に、銅箔等をエッチングして形成した回路パターン１
２を設ける。そのような回路パターン１２の配線電極１
３上には、保護樹脂１７をスクリーン印刷で一括塗布
し、図１（Ａ）および図２に示す状態とする。In the figure, reference numeral 10 is a TAB tape which is a circuit board, and a circuit pattern 1 formed by etching a copper foil or the like on the surface of an insulating film base material 11 such as a polyimide resin.
2 is provided. The wiring electrode 1 of such a circuit pattern 12
Protective resin 17 is collectively applied onto 3 by screen printing to obtain the state shown in FIGS.

【００１４】その後、図１（Ｂ）に示すように、保護樹
脂１７の塗布位置にＩＣ１５を取り付けて回路パターン
１２の配線電極１３に表面の金属電極１４を熱圧着によ
り接合し、ＴＡＢテープ１０上にＩＣ１５をフリップチ
ップ接合する。接合は、通常と同様に、金とすずや、金
と金はんだなどによる金属接合を行う。Thereafter, as shown in FIG. 1 (B), the IC 15 is attached to the position where the protective resin 17 is applied, and the metal electrode 14 on the surface is bonded to the wiring electrode 13 of the circuit pattern 12 by thermocompression bonding. The IC 15 is flip-chip bonded to. The joining is performed by metal joining with gold and tin, gold and gold solder, or the like, as usual.

【００１５】このように、ＴＡＢテープ１０上に保護樹
脂１７を印刷により一括塗布して後、その塗布位置にＩ
Ｃ１５を取り付けてＴＡＢテープ１０上にフリップチッ
プ接合すると、保護樹脂１７の塗布を高精度にかつ安定
して行うことができ、裏周りの発生を解消するととも
に、良好なフィレット形状を形成することができる。加
えて、一括塗布することから、塗布時間を短縮する一
方、空気の流入を防いで気泡の発生を抑制することがで
きる。As described above, after the protective resin 17 is collectively applied on the TAB tape 10 by printing, I is applied to the applied position.
When C15 is attached and flip-chip bonding is performed on the TAB tape 10, the protective resin 17 can be applied with high accuracy and stability, the occurrence of the back circumference can be eliminated, and a good fillet shape can be formed. it can. In addition, since the coating is performed all at once, it is possible to reduce the coating time, prevent the inflow of air, and suppress the generation of bubbles.

【００１６】ところで、図３（Ａ）に示すように、ＩＣ
１５には外周に段部１６を形成し、その段部１６がＴＡ
Ｂテープ１０と対向する向きとなるようにＴＡＢテープ
１０上にフリップチップ接合するとよい。そして、
（Ｂ）に示すように、その段部１６下に入り込むよう
に、ＴＡＢテープ１０とＩＣ１５間に樹脂１７を入れて
後、加熱や光照射等でエネルギを加えて樹脂１７を硬化
し、フィレット形状を形成して、ＴＡＢテープ１０上に
ＩＣ１５をフリップチップ接合する。By the way, as shown in FIG.
A step portion 16 is formed on the outer periphery of 15 and the step portion 16 is TA
Flip chip bonding may be performed on the TAB tape 10 so as to face the B tape 10. And
As shown in (B), after the resin 17 is inserted between the TAB tape 10 and the IC 15 so as to enter under the step portion 16, energy is applied by heating or light irradiation to cure the resin 17 and fillet shape. Then, the IC 15 is flip-chip bonded onto the TAB tape 10.

【００１７】ＩＣ１５は、例えば図４（Ａ）に示すよう
に、円形のウェハ２０をはじめ横方向にａ〜ｅの順に切
り落とし、次いで縦方向にｆ〜ｊの順に切り落とし、１
つのウェハ２０から複数形成する。具体的にはそれぞれ
まず（Ｂ）に示すように厚い円形ブレード２１を回転し
ながら一方向に移動して直線溝２２を形成し、次いで
（Ｃ）に示すように薄い円形のブレード２３を回転しな
がら一方向に移動してまっすぐに切り落とし、段部１６
を有する矩形形状に形成してなる。段部１６の深さｔ
は、ＩＣ１５の厚さＴの１／２〜２／３とする。For example, as shown in FIG. 4A, the IC 15 is cut off from a circular wafer 20 in the horizontal direction in the order of a to e, and then in the vertical direction in the order of f to j.
A plurality of wafers 20 are formed. Specifically, first, as shown in (B), a thick circular blade 21 is rotated to move in one direction to form a linear groove 22, and then, as shown in (C), a thin circular blade 23 is rotated. While moving in one direction and cutting off straight, step 16
It is formed in a rectangular shape having. Depth t of step 16
Is 1/2 to 2/3 of the thickness T of the IC 15.

【００１８】このように、ＩＣ１５の外周に、ＴＡＢテ
ープ１０と対向する向きの段部１６を形成すると、その
段部１６で樹脂１７の上昇を防いで樹脂１７を多少多め
に塗布しても樹脂１７がＩＣ１５周囲を周り込むことを
防ぎ、樹脂１７のいわゆる裏周りの発生を防止すること
ができる。As described above, when the step portion 16 facing the TAB tape 10 is formed on the outer periphery of the IC 15, the resin 17 is prevented from rising at the step portion 16 and even if a large amount of the resin 17 is applied, It is possible to prevent the resin 17 from getting around the periphery of the IC 15 and prevent the so-called backside of the resin 17 from being generated.

【００１９】これにより、樹脂１７の適量塗布範囲を広
げて塗布を容易とし、樹脂１７を多少多めに付けること
で、樹脂１７により形成されるフィレット形状を安定さ
せて一定の品質を保ち、ＴＡＢテープ１０とＩＣ１５間
の応力緩和を図るとともに、パッケージを保護して信頼
性を高め、さらには電気的な絶縁を完全にし、また裏周
りした樹脂１７がボンディングツールに付着することに
起因してその付着した樹脂１７を除去しなければならな
かったが、そのような清掃のための待機状態をなくし
て、生産性を向上することができる。Thus, the application range of the appropriate amount of the resin 17 is widened to facilitate the application, and by adding a little more resin 17, the shape of the fillet formed by the resin 17 is stabilized to maintain a certain quality, and the TAB tape is used. The stress between the IC 10 and the IC 15 is mitigated, the package is protected to improve reliability, the electrical insulation is perfected, and the resin 17 around the back of the IC adheres to the bonding tool. The resin 17 had to be removed, but the standby state for such cleaning can be eliminated and the productivity can be improved.

【００２０】[0020]

【発明の効果】以上説明したように、この発明によれ
ば、回路基板上に保護樹脂をスクリーン印刷等の印刷に
より一括塗布して後、その塗布位置にＩＣを取り付けて
ＴＡＢテープ１０上にフリップチップ接合するから、保
護樹脂の塗布を高精度にかつ安定して行うことができ、
裏周りの発生を解消するとともに、良好なフィレット形
状を形成することができる。加えて、一括塗布すること
から、塗布時間を短縮する一方、空気の流入を防いで気
泡の発生を抑制することができる。As described above, according to the present invention, after the protective resin is collectively applied on the circuit board by printing such as screen printing, the IC is attached to the application position and flipped on the TAB tape 10. Since the chips are joined, the protective resin can be applied with high accuracy and stability,
It is possible to eliminate the occurrence of the back circumference and form a good fillet shape. In addition, since the coating is performed all at once, it is possible to reduce the coating time, prevent the inflow of air, and suppress the generation of bubbles.

【００２１】請求項２に係る発明によれば、ＩＣの外周
に段部を形成し、その段部が回路基板と対向する向きと
なるようにＩＣを回路基板上にフリップチップ接合する
から、段部で樹脂の上昇を防いで樹脂を多少多めに塗布
しても樹脂がＩＣ周囲を周り込むことを防ぎ、樹脂のい
わゆる裏周りの発生を防止することができる。According to the second aspect of the invention, the step is formed on the outer periphery of the IC, and the IC is flip-chip bonded on the circuit board so that the step faces the circuit board. It is possible to prevent the resin from rising around the IC and prevent the so-called backside of the resin from being generated even if the resin is applied in a slightly larger amount by preventing the resin from rising in the portion.

【００２２】これにより、樹脂の適量塗布範囲を広げて
塗布を容易とし、樹脂を多少多めに付けることで、樹脂
により形成されるフィレット形状を安定させて一定の品
質を保ち、ＴＡＢテープとＩＣ間の応力を緩和してＩＣ
接合部の破壊を防止するとともに、パッケージを保護し
て信頼性を高め、さらには電気的な絶縁を完全にし、ま
たボンディングツールに付着した樹脂を除去する間、駆
動を停止する従来の清掃待機状態をなくして生産性を向
上することができる。This makes it possible to spread the appropriate amount of resin to make the application easier, and to add a little more resin to stabilize the shape of the fillet formed by the resin and maintain a certain quality. The stress of IC
Prevents damage to the joint, protects the package for higher reliability, completes electrical insulation, and stops the drive while removing the resin adhering to the bonding tool. Can be improved and productivity can be improved.

【００２３】請求項３に係る発明によれば、段部の深さ
を、ＩＣの厚さの１／２〜２／３とするから、深さが浅
過ぎて樹脂の収容量が少なくなり、樹脂の適量塗布範囲
を十分に広げることができなかったり、深さが深過ぎて
残りのＩＣ部分の強度が不足したりする問題をなくすこ
とができる。According to the invention of claim 3, since the depth of the step portion is set to 1/2 to 2/3 of the thickness of the IC, the depth is too shallow and the amount of resin accommodated decreases. It is possible to eliminate the problems that the appropriate amount application range of the resin cannot be sufficiently widened, and that the depth is too deep and the strength of the remaining IC portion is insufficient.

【図面の簡単な説明】[Brief description of drawings]

【図１】この発明による半導体装置におけるＩＣ実装方
法を示し、（Ａ）はＩＣ実装前、（Ｂ）はＩＣ実装後で
ある。FIG. 1 shows an IC mounting method in a semiconductor device according to the present invention, where (A) is before IC mounting and (B) is after IC mounting.

【図２】そのＩＣ実装前に回路基板上に保護樹脂を塗布
した状態を示す説明平面図である。FIG. 2 is an explanatory plan view showing a state in which a protective resin is applied on a circuit board before mounting the IC.

【図３】外周に段部を有するＩＣのＩＣ実装方法を示
し、（Ａ）はＩＣ実装前、（Ｂ）はＩＣ実装後である。3A and 3B show an IC mounting method of an IC having a step portion on the outer periphery, where FIG. 3A is before IC mounting and FIG. 3B is after IC mounting.

【図４】そのＩＣの段部加工を説明するもので、（Ａ）
は切削位置説明図、（Ｂ）は厚いブレードによる切削状
態図、（Ｃ）は薄いブレードによる切削状態図である。FIG. 4 is a diagram for explaining the step processing of the IC, (A)
Is a cutting position diagram, (B) is a cutting state diagram with a thick blade, and (C) is a cutting state diagram with a thin blade.

【図５】（Ａ）〜（Ｃ）は、従来のＩＣ実装工程図であ
る。5A to 5C are conventional IC mounting process diagrams.

【図６】樹脂が少な過ぎた場合のＩＣ実装部の縦断面図
である。FIG. 6 is a vertical cross-sectional view of an IC mounting portion when the amount of resin is too small.

【図７】樹脂が多過ぎた場合のＩＣ実装部の縦断面図で
ある。FIG. 7 is a vertical cross-sectional view of an IC mounting portion when there is too much resin.

【図８】ＩＣを接合するときのＩＣ実装部の縦断面図で
ある。FIG. 8 is a vertical cross-sectional view of an IC mounting portion when bonding ICs.

【符号の説明】[Explanation of symbols]

１０ ＴＡＢテープ（回路基板） １１ 絶縁フィルム基材 １２ 回路パターン １３ 配線電極 １４ 金属電極 １５ ＩＣ １６ 段部 １７ 保護樹脂 Ｔ ＩＣの厚さ ｔ 段部の深さ 10 TAB tape (circuit board) 11 Insulating film base material 12 circuit patterns 13 wiring electrodes 14 metal electrodes 15 IC 16 steps 17 Protective resin Thickness of T IC t step depth

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 回路基板上に保護樹脂を印刷により一括
塗布して後、その塗布位置にＩＣを取り付けてそのＩＣ
を前記回路基板上にフリップチップ接合してなる、半導
体装置のＩＣ実装方法。1. A protective resin is collectively applied on a circuit board by printing, and an IC is attached to the application position to attach the IC.
A method for mounting an IC on a semiconductor device, the method comprising flip-chip bonding onto the circuit board. 【請求項２】 前記ＩＣの外周に段部を形成し、その段
部が前記回路基板と対向する向きとなるように前記ＩＣ
を前記回路基板上にフリップチップ接合してなる、請求
項１に記載の半導体装置のＩＣ実装方法。2. A step portion is formed on the outer periphery of the IC, and the IC portion is oriented so that the step portion faces the circuit board.
The IC mounting method for a semiconductor device according to claim 1, wherein the IC chip is flip-chip bonded onto the circuit board. 【請求項３】 前記段部の深さを、前記ＩＣの厚さの１
／２〜２／３としてなる、請求項２に記載の半導体装置
のＩＣ実装方法。3. The depth of the step is set to be 1 of the thickness of the IC.
The IC mounting method for a semiconductor device according to claim 2, wherein the IC mounting method is / 2 to 2/3. 【請求項４】 前記回路基板上に前記保護樹脂をスクリ
ーン印刷により塗布してなる、請求項１に記載の半導体
装置のＩＣ実装方法。4. The IC mounting method for a semiconductor device according to claim 1, wherein the protective resin is applied onto the circuit board by screen printing.
JP2001359001A 2001-11-26 2001-11-26 Method of ic-mounting for semiconductor device Pending JP2003158157A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2001359001A JP2003158157A (en) 2001-11-26 2001-11-26 Method of ic-mounting for semiconductor device
TW091121898A TW557485B (en) 2001-11-26 2002-09-24 Semiconductor device and method of IC-mounting for semiconductor device
KR1020020064760A KR20030043624A (en) 2001-11-26 2002-10-23 Semiconductor device and method for mounting ic on semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001359001A JP2003158157A (en) 2001-11-26 2001-11-26 Method of ic-mounting for semiconductor device

Publications (1)

Publication Number Publication Date
JP2003158157A true JP2003158157A (en) 2003-05-30

Family

ID=19170080

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001359001A Pending JP2003158157A (en) 2001-11-26 2001-11-26 Method of ic-mounting for semiconductor device

Country Status (1)

Country Link
JP (1) JP2003158157A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040052050A (en) * 2002-12-13 2004-06-19 엘지전자 주식회사 bare IC mounting method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040052050A (en) * 2002-12-13 2004-06-19 엘지전자 주식회사 bare IC mounting method

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