JP2003157698A - Semiconductor memory and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time required for testing self-refresh-operation of a semiconductor memory having a plurality of self-refresh modes of which refresh- regions are different. SOLUTION: First, the prescribed data is written in all memory regions. Next, after a self-mode is set, a self-refresh signal/TSRC for test is made 'L' and an internal row control signal IPAS is made 'H', then, a column control signal/TCAS for test is made 'L' and the prescribed data is written in a memory cell selected by a refresh-count address CNT and a column address TCADR for test in a period in which a connection enable-signal of a data line and a sense amplifier is 'H'. Such operation as the above is repeated in accordance with a refresh-count address. Next, data of all memory regions are read, and it is checked that write is performed only in a set region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device including a memory cell that needs refreshing for storing data, and more particularly to a DRAM (Dynamic Random Access Memory) and a method for inspecting its self-refresh operation. .

[0002]

2. Description of the Related Art In a DRAM in which memory cells are formed by capacitors, after a certain period of time, data held in the memory cells as electric charges is lost due to a leak current. Therefore, it is necessary to perform the refresh operation in order to rewrite and maintain the data held in the memory cell. The refresh operation in a DRAM is an operation in which, in a memory cell array in which a plurality of memory cells are arranged in a matrix, a row of word lines is selected, and then all the memory cells on the word lines are read, amplified, and rewritten. Is sequentially performed for all word lines.

The refresh operation of the DRAM includes a refresh operation interrupted during a random access operation such as reading / writing data from / to a memory cell, and a period during which the DRAM is in the data holding mode instead of the random access operation, for example, a microcomputer. There is a refresh operation called self-refresh that is performed during standby (sleep mode or the like). During the latter self-refresh, the DRAM gives an external control signal by refreshing the output signal of the built-in refresh address counter as a row address in response to a refresh request signal automatically generated by an internal timer. Even if not, the refresh operation is continuously performed at a constant cycle.

Depending on the system using the DRAM,
In some cases, the memory area that needs to hold data at the time of self-refresh is not the entire area but only a part of the area.
Even in such a case, the current consumption increases when the entire area is refreshed. Therefore, there is a DRAM in which the refresh area for self refresh can be changed to a partial area other than the entire area by external setting. A conventional method for testing the self-refresh operation of such a DRAM will be described below.

FIG. 9 shows two test external mode signals T.
With SM0 and TSM1, the refresh area is the entire memory area, 1/2 of the entire memory area, and 1 of the entire memory area.
4 is a timing chart of signals of respective parts in a test of self-refresh operation of 1/2 of all memory areas in a DRAM which can be switched to four modes which are 1/8 of all memory areas.

In FIG. 9, first, the DRAM test signal DT is set to the logic "H" to set the test mode, and predetermined data is written in a half area of the entire memory.

Next, the test self-refresh control signal / TSRC is set to logic "L" to refresh only a half area of the entire memory for the memory data holding time (= t) or longer. The self refresh operation at this time will be described with reference to FIGS. 8 and 10. FIG. 8 is a circuit diagram of the self-refresh control circuit 50 ', and FIG.
10 is a timing chart of signals of respective parts of FIG. 8 in the self-refresh operation of FIG. 9.

First, the test external mode signal TSM0 is set to logic "H" and the test external mode signal TSM1 is set to logic "L", and the refresh area at the time of self-refresh is set to a half area of the entire memory area. Then, when the test self-refresh control signal / TSRC is changed from the logic "H" to the logic "L", the test self-refresh control signal / TSRC is inverted and delayed to obtain the delayed signal RSLF.
When D becomes logic “H”, the oscillation circuit 51 starts oscillation.

Since the test external mode signal TSM1 is logic "L", the output signal OSC of the oscillation circuit 51 is changed to
The signal OSC2 divided by 2 in the frequency dividing circuit 52 is supplied to the selector 5
4 is selected and input to the short pulse generation circuit 55. The short pulse generation circuit 55 detects the rising edge of OSC2, generates the self-refresh set signal SRS which is a short pulse, and sets the set / reset circuit 56. At this time, the self-refresh flag SRF, which is the output signal of the set / reset circuit 56, becomes logic “H”, so that the internal row control signal IRAS is set to logic “H”, the refresh address is selected as the row address, and the sense amplifier is selected. The data in the memory cell selected by the word line is amplified by the bit line, output, and rewritten in the memory cell.

After that, the self-refresh flag SRF
The self-refresh reset signal SRR, which is a signal delayed by the delay circuit 57, resets the set-reset circuit 56 and sets the self-refresh flag SRF to the logic "L". Therefore, the internal row control signal IRAS is set to the logic "L". Then, the word line is deselected and the bit line is precharged.

Such an operation is repeated at each rising edge of OSC2, and while the test self-refresh control signal / TSRC is logic "L", 1 / of the total memory is reached.
Area 2 is refreshed.

Immediately after that, as shown in FIG. 9, the data of the first half area of the entire memory which has been written is read to check whether the refresh operation is normal and the data is not destroyed.

A test similar to the above is performed in a mode in which the refresh area is the entire memory area,
The mode of 4 and the mode of 1/8 of the entire memory area are set and repeated.

[0014]

Such a conventional DRAM
In the inspection method of No. 3, since the inspection of the self-refresh operation is performed for a long time longer than the data retention time of the memory cell and four times in total in each self-refresh mode in order to detect a defect when the refresh is not performed properly. ,
There is a problem that it takes a lot of inspection time.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor memory device and a testing method thereof in which the time required for testing a self-refresh operation in different refresh regions is shortened. is there.

[0016]

In order to achieve the above object, a first semiconductor memory device inspection method according to the present invention comprises:
A method for inspecting a semiconductor memory device having a plurality of self-refresh modes, each of which includes a memory cell that needs to be refreshed to store data and has a different refresh area, the method using a refresh count address generated in the self-refresh mode. Whether or not only the specific area set in each mode is refreshed by writing the specified data in the memory cell and checking whether the specific data is written only in the specific area set in each mode. It is characterized by inspecting.

According to this configuration, in the self-refresh mode inspection other than the entire memory area, it is not necessary to perform the write test operation for the data retention time of the memory cells or more, and the inspection is performed in each mode. Since it is sufficient to inspect the write test operation only for a specific area, the inspection time can be shortened.

In order to achieve the above object, a second semiconductor memory device inspection method according to the present invention includes a plurality of self-refresh modes including memory cells that need refreshing to store data and have different refresh areas. A method of inspecting a semiconductor memory device having: a predetermined data is read from a memory cell by using a refresh count address generated in a self-refresh mode, and a predetermined data is read only from a specific area set in each mode. Is checked to see if only the specific area set in each mode is refreshed.

According to this structure, in the self-refresh mode inspection other than the entire memory area, it is not necessary to perform the read test operation for the data retention time of the memory cells or longer, and the inspection is performed in each mode. Since the read test operation only needs to be inspected for a specific area, the inspection time can be shortened.

In order to achieve the above-mentioned object, the first semiconductor memory device according to the present invention has a plurality of memory cells that need refreshing to store data, and the memory cells and the data line via a transistor. A semiconductor memory device having a plurality of self-refresh modes, each of which includes a connected sense amplifier and has different refresh regions,
At the time of self-refresh, the row control signal (IRAS) is activated (to logic “H”) to start row control every internal refresh, and then the row control signal is deactivated (to logic “L”). The process of terminating the row control is performed after a certain time delay from the start of the row control during the normal operation, and the connection enable signal (TGEN) is deactivated (to the logic “L”) during the write in the test mode. The self-refresh control circuit is provided after a predetermined time after the writing from the data line to the sense amplifier is completed and the connection between the sense amplifier and the data line is released by the transistor.

Conventionally, data could not be written to a memory cell during self-refresh, but the first
According to the configuration of the semiconductor memory device, the predetermined address can be written in the memory by using the refresh address generated in the self-refresh mode, and the refresh address can be written more than the number of times the data is written in the entire memory area in the self-refresh. It has become possible to perform continuous writing to the memory and check that data is written only in a specific limited area.

By performing this inspection, it is possible to inspect whether only a limited area is refreshed at the time of self-refreshing, without performing self-refreshing for more than the data retention time of the memory cell. The inspection time can be shortened.

In order to achieve the above object, a second semiconductor memory device according to the present invention includes a plurality of memory cells that need refreshing to store data, and the memory cells and the data line via a transistor. A semiconductor memory device having a plurality of self-refresh modes, each of which includes a connected sense amplifier and has different refresh regions,
At the time of self-refresh, the row control signal (IRAS) is activated (to logic “H”) to start row control every internal refresh, and then the row control signal is deactivated (to logic “L”). The process of terminating the row control is performed after a fixed time delay from the start of the row control during the normal operation, and the connection enable signal (TGEN) is deactivated (to the logic “L”) during the reading in the test mode. The self-refresh control circuit is provided after a lapse of a predetermined time after the reading from the sense amplifier to the data line is completed and the connection between the sense amplifier and the data line is released by the transistor.

Conventionally, the data in the memory cell could not be read during the self-refresh, but according to the configuration of the second semiconductor memory device described above, the data in the memory can be read using the refresh address generated in the self-refresh mode. It can be read, and more than the number of times necessary to read the data in all memory areas during self refresh,
It becomes possible to perform a continuous read operation to a memory at a refresh address and perform an inspection to check that only data in a specific limited area is read.

By performing this inspection, it is possible to inspect whether only a limited area is refreshed at the time of self-refreshing, without performing self-refreshing for more than the data retention time of the memory cell. The inspection time can be shortened.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, a DRAM in which the refresh area at the time of self-refresh can be set to the entire memory area, 1/2 of the entire area, and 1/4 of the entire area by an external setting will be described as an example. The inspection method at the time of refresh will be described.

FIG. 1 shows a DRA according to an embodiment of the present invention.
6 is a circuit block diagram showing a configuration example of an inspection circuit using M and a microcomputer (μCOM). FIG.

First, a method of testing the self-refresh operation in the mode in which the refresh area of the DRAM 900 of FIG. 1 is the entire memory area will be described.

First, as shown in the timing chart of FIG. 4, the DRAM test signal DT is set to the logic "H" level, the test signal is selected, and predetermined data is written in the entire memory area.

Next, the test external mode signal TSM0 is set to logic "H", the test external mode signal TSM1 is set to logic "L", and the test self-refresh control signal / TSRC is set to logic "L". The entire memory area is refreshed for the memory data holding time (= t) or more.
At this time, the self-refresh flag SRF from the self-refresh control circuit 50 shown in FIG.
While the internal row control signal IRAS is generated and the self refresh mode signal SRMODE is logic "H", the word line is selected by the refresh counter 17 of FIG.
The entire memory area is refreshed for time t or more.

Secondly, a first embodiment of the inspection method in the case where the refresh area is 1/4 of the entire memory area will be described.

First, the data "1" is written in the entire memory area. The operation will be described with reference to FIGS. 1, 2, 3, and 5. FIG. 2 shows the memory core unit 80 of FIG.
5 is a circuit block diagram showing an internal configuration of 0, and FIG. 5 is a timing chart of signals of respective parts during a normal write test operation.

DRAM test signal DT is set to the logic "H" level to put DRAM 900 in the test mode.

At time t0, test reset signal TRS is logic "H", so that DRAM 900 is in the initial state.

At time t1, the test reset signal TRS has the logic "L", so that the normal write test is activated.

At time t2, the test row control signal / TRAS of logic "L" level is latched by the latch circuit 13, the internal row control signal IRAS is set to logic "H" level, and the latch 11 tests the test row. Address TR
The ADR "0" is latched. IRAS is logical "H"
At the level, the row predecoder 14 and the row decoder 100 of FIG. 2 latch the row address (= 0).
Is decoded, the word line WL0 of the first memory cell block 200 is selected, and becomes the logic "H" level.

At time t3, the test column address TCADR of "0" is latched by the latch 16. At the rising edge of the test clock TCLK, the test column control signal / TCAS is logic "L" and the test write control signal / TWE is logic "L". Therefore, the output signal WE0 of the column control circuit 15 is logic "H". After
Since the connection enable signal TGEN of the bit line and the data line becomes the logic “H” and the latched row address is “0”, the first sense amplifier column 204 is selected and the NMOS for connecting the bit line and the data line is selected. The gate signal TG0 of the transistor becomes logic “H”, the NMOS transistor is turned on, and the test input data TDIN (7: 0) latched by the input data latch 101 is connected to the data lines DL7 to DL0. The sense amplifier writes data to the memory cell selected by the word line WL0 via the bit lines BL7 to BL0.

At time t4, the connection enable signal T
GEN becomes logic “L”, and data lines DL7 to DL0,
When the connection between the inverted data lines / DL7 to / DL0 and the sense amplifier is released, the IRAS reset signal IRASRS becomes logic "H", the latch 13 is reset, and the internal row control signal IRAS becomes logic "L". When IRAS becomes logic "L", the word line becomes unselected (WL0 = "L"), bit lines BL7 to BL0, inverted bit line / BL7.
~ / BL0 is precharged to the reference potential.

At time t5, the operation is the same as at time t2 except that the test row address TRADR becomes "1".

The write operation of such data "1" is repeated, and the first memory cell block 200, the second memory cell block 201, the third memory cell block 202,
Data “1” is written in all the memory cell areas of the fourth memory cell block 203.

Next, the operation of writing "0" data to the memory using the refresh address generated during the self refresh will be described with reference to the timing chart of FIG.

First, the self refresh test signal SR
T is set to the logic "H", the test external mode signal TSM0 is set to the logic "L", and the test external mode signal TSM1 is set to the logic "H", and the mode of the refresh area at the time of self-refreshing is 1/4 of the entire area. (4th memory cell block 203).

At time t0, the test reset signal is set to logic "H" to reset the refresh counter 17.

At time t2, the test self-refresh control signal is changed from logic "H" to "L", and the self-refresh mode signal SRMODE from the self-refresh control circuit 50 becomes logic "H". Value (higher 2 bits) CNT
(S + 2: s + 1) is fixed to logic “H” (counter value = “3”), the self-refresh flag SRF is logic “H”, and therefore the internal row control signal IRAS is logic “H”.
Then, the refresh address is selected as the row address, and the word line W of the fourth memory cell block 203 is selected by the row predecoder 14 and the row decoder 100 of FIG.
L0 is selected and becomes logic "H".

At time t3, "0" of the test column address TCADR is latched by the latch circuit 16. At the rising edge of the test clock TCLK, the test column control signal / TCAS is logic "L" and the test write control signal / TWE is logic "L". Therefore, the output signal WE0 of the column control circuit 15 is logic "H". , The connection enable signal TGE between the bit line and the data line
Since N becomes logic “H” and the upper 2 bits of the row address are logic “H”, the fourth sense amplifier row 207 is selected and the gate signal TG3 of the NMOS transistor for connecting the bit line and the data line is logic “H”. H ", and this NMO
The S transistor is turned on, and the test input data TDIN (7: 0) latched by the input data latch 101.
(All “0”) is written in the memory cell selected by the word line WL0 via the bit lines BL7 to BL0 by the sense amplifier connected to the data lines DL7 to DL0.

At time t4, the connection enable signal T
When G becomes logic "L" and the connection between the data lines DL7 to DL0 and the inversion data lines / DL7 to / DL0 and the sense amplifier is released, the IRAS reset signal IRASRS becomes logic "H". Here, the IRAS reset signal IRASRS is selected and input to the reset input terminal (R) of the set / reset circuit 56 in the self-refresh control circuit 50 by the selector 58 during the self-refresh test. The reset circuit 56 is reset, and the self-refresh flag SRF, which is the output signal of the set / reset circuit 56, has a logic "L".
Therefore, the internal row control signal IRAS becomes logic "L".
become. When IRAS becomes logic "L", the word line becomes non-selected (WL0 = "L"), and bit lines BL7 to BL
0, the inverted bit lines / BL7 to / BL0 are precharged to the reference potential.

At time t5, the operation is the same as that at time t2 except that the lower 1 bit CNT (s: 0) of the counter value of the refresh counter 17 becomes "1" and the word line WL1 is selected.

The write operation of the data "0" is repeated, and the data "0" is written only in the memory cell area of the fourth memory cell block 203.

Next, in order to check whether the data “0” is written only in the memory cell area of the fourth memory cell block 203, the fourth memory cell block 203
Data “0” is read from the memory cell of the first memory cell block 200 to the third memory cell block 20.
From 2, it is checked that the data "1" is read (normal read test operation).

At time t0r, the word line W of the first memory cell block 200 is operated by the same operation as at time t2 in FIG.
L0 is selected and becomes logic "H".

At time t1r, "0" of the test column address TCADR is latched by the latch 16.
Since the test column control signal / TCAS is logic "L" and the test write control signal / TWE is logic "H" at the rising of the test clock TCLK, the connection enable signal TGEN which is the output signal of the column control circuit 15 is generated.
Becomes a logic "H", the latched row address is "0", and the first sense amplifier row 204 is selected. Therefore, the gate signal TG0 of the NMOS transistor for connecting the bit line and the data line is logic "H". And this NMO
Turn on the S transistor. Therefore, the read data of the memory cell selected by the word line WL0 is amplified by the sense amplifier and output to the data lines DL7 to DL0, the data is amplified by the read amplifier 300, latched by the output data latch 400, and tested. Output data TDOU
It becomes T (7: 0).

At t2r, the connection enable signal TG
When EN becomes logic “L” and the connection between the data lines DL7 to DL0 and the inverted data lines / DL7 to / DL0 and the sense amplifier is released, the IRAS reset signal IRASRS becomes logic “H” and the latch circuit 13 Are reset and the internal row control signal IRAS becomes logic "L". IRAS
Becomes logic "L", the word line is not selected (WL0 =
"L"), and the bit lines BL7 to BL0 and the inverted bit lines / BL7 to / BL0 are precharged to the reference potential.

At time t3r, the operation is the same as at time t1r, except that the test row address TRADR becomes "1".

Such a read operation is repeated and the fourth
Data “0” is read from the memory cell of the memory cell block 203, and the first memory cell block 200 to
It can be checked that the data “1” is read from the third memory cell block 202.

The second embodiment of the inspection method in the case where the refresh area is ¼ of the entire memory area will be described below.

First, at the same timing as in FIG. 5, the first memory cell block 200 to the third memory cell block 20.
The data “1” is written in 2 and the data “0” is written in the fourth memory cell block 203.

Next, the operation of reading the memory data using the refresh address generated during the self refresh will be described with reference to FIG. FIG. 7 is a timing chart of signals at various parts in the read test operation in the self-refresh mode.

First, the self refresh test signal SR
T is set to the logic "H", the test external mode signal TSM0 is set to the logic "L", and the test external mode signal TSM1 is set to the logic "H". Memory cell block 203)
Set to.

At time t0, the test reset signal TRS is set to logic "H", and the refresh counter 17 is set.
To reset.

At time t2, the test self-refresh control signal / TSRC is changed from logic "H" to "L", and the self-refresh mode signal SRMODE from the self-refresh control circuit 50 becomes logic "H". Refresh counter 1
7 counter value (upper 2 bits) CNT (s + 2: s +
1) is fixed to logic “H” (counter value = “3”),
The self-refresh flag SRF becomes logic “H”, the internal row control signal IRAS becomes logic “H”, the refresh address is selected as the row address, and the row predecoder 14 and the row decoder 100 in FIG.
The word line WL0 of the memory cell block 203 is selected and becomes the logic "H".

At time t3, "0" of the test column address TCADR is latched by the latch circuit 16. At the rising edge of the test clock TCLK, the test column control signal / TCAS is logic "L" and the test write control signal / TWE is logic "L". Therefore, the output signal WE0 of the column control circuit 15 is logic "H". , The connection enable signal TGE between the bit line and the data line
Since N becomes logic “H” and the upper 2 bits of the row address are logic “H”, the fourth sense amplifier row 207 is selected and the gate signal TG3 of the NMOS transistor for connecting the bit line and the data line is logic “H”. H ", and this NMO
The S transistor turns on. Therefore, the word line WL0
The read data of the memory cell selected by is amplified by the sense amplifier and output to the data lines DL7 to DL0,
The data is amplified by the read amplifier 300 and latched by the output data latch 400, and the test output data D
It becomes OUT (7: 0).

At time t4, the connection enable signal T
GEN becomes logic “L”, and data lines DL7 to DL0,
When the connection between the inverted data lines / DL7 to / DL0 and the sense amplifier is released, the IRAS reset signal IRASRS
Becomes a logic "H". Self refresh control circuit 50
Input terminal (R) of the set / reset circuit 56 in
In the test, IRAS reset signal IRASR
Since S is selected by the selector 58 and input, the set / reset circuit 56 is reset at this time, and the self-refresh flag SRF becomes logic "L", so that the internal row control signal IRAS becomes logic "L". . IRAS
Becomes logic "L", the word line is not selected (WL0 =
"L"), and the bit lines BL7 to BL0 and the inverted bit lines / BL7 to / BL0 are precharged to the reference potential.

At time t5, the operation is the same as at time t2 except that the lower 1 bit CNT (s: 0) of the counter value of the refresh counter 17 becomes "1" and the word line WL1 is selected.

Such a read operation is repeated, and the fourth
Data “0” in only the memory cell area of the memory cell block 203 is read.

The refresh area is 1/2 of the total area.
Also in the self-refresh operation inspection method in the case of
This is the same as the inspection method of the self-refresh operation in the case of 4.

[0066]

As described above, according to the present invention,
In a semiconductor memory device having a plurality of self-refresh modes having different refresh areas, it is possible to shorten the time required for the self-refresh operation inspection (write test and read test in the self-refresh mode). Play.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing a configuration example of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit block diagram showing an internal configuration of a memory core section 800 of FIG.

FIG. 3 is a circuit diagram showing an internal configuration of a self-refresh control circuit 50 shown in FIG.

FIG. 4 is a timing chart of signals at various parts in the self-refresh mode inspection of all areas.

FIG. 5 is a timing chart of signals at various parts in a normal write test operation.

FIG. 6 is a timing chart of signals of respective parts in a write test operation in a self refresh mode in which a refresh area is ¼ of the entire area and a subsequent normal read test operation.

FIG. 7 is a timing chart of signals at various parts in a read test operation in a self-refresh mode in which the refresh area is 1/4 of the entire area.

FIG. 8 is a circuit diagram showing an internal configuration of a self-refresh control circuit 50 ′ in a conventional semiconductor memory device.

FIG. 9 is a timing chart of signals of respective parts in a conventional self-refresh operation inspection of 1/2 of the entire memory area.

FIG. 10 is a timing chart of a self-refresh operation during a conventional normal test.

[Explanation of symbols]

1-10, 12, 54, 58 Selector 11, 13, 16 Latch circuit 14 Row predecoder 15 Column control circuit 17 Refresh counter 50 Self-refresh control circuit 51 oscillator circuit 52, 53 frequency divider 55 Short pulse generator 56 set reset circuit 57 Delay circuit 100 row decoder 101 Input data latch 200 First memory cell block 201 Second memory cell block 202 third memory cell block 203 Fourth memory cell block 204 first sense amplifier row 205 Second sense amplifier row 206 Third Sense Amplifier Row 207 Fourth sense amplifier row 300 read amplifier 400 output data latch 800 memory core section 900 DRAM

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 11/34 371A F term (reference) 2G132 AA00 AA08 AB01 AC03 AD06 AE08 AE14 AE22 AH04 AK09 AK11 AK12 AK13 AK15 AK18 AK21 AL09 5L106 AA01 DD12 EE06 FF02 GG05 5M024 AA91 BB22 BB40 EE05 EE29 EE30 GG01 GG05 GG06 MM06 PP01 PP02 PP03 PP07

Claims (4)

[Claims] 1. A method of inspecting a semiconductor memory device having a plurality of self-refresh modes, each of which includes a memory cell that needs to be refreshed to store data and has different refresh regions, the refresh being generated in the self-refresh mode. Write predetermined data to the memory cell using a count address, only in the area set in each mode,
A method for inspecting a semiconductor memory device, comprising: checking whether or not only the area set in each mode is refreshed by checking whether or not the predetermined data is written. 2. A method for inspecting a semiconductor memory device having a plurality of self-refresh modes, each of which includes a memory cell that needs to be refreshed to store data and has different refresh areas, the refresh being generated in the self-refresh mode. Areas set in each mode are read by reading predetermined data from the memory cell using a count address and checking whether the predetermined data is read only from the areas set in each mode. A method for inspecting a semiconductor memory device, which comprises inspecting whether or not only the memory is refreshed. 3. A plurality of self-refresh modes, each of which includes a plurality of memory cells that need to be refreshed for storing data and a sense amplifier connected to the memory cells and a data line through a transistor, and has different refresh regions. In a semiconductor memory device having: a row control signal is activated and row control is started at each internal refresh performed during self-refresh, and then the row control signal is deactivated to terminate row control. Processing is performed after a certain time delay from the start of row control during normal operation, and when writing in the test mode, writing from the data line to the sense amplifier is completed, and the transistor causes the sense amplifier and the data line to be connected to each other. It is equipped with a self-refresh control circuit that activates after a fixed time after disconnection. The semiconductor memory device according to claim. 4. A plurality of self-refresh modes, each of which includes a plurality of memory cells that need to be refreshed for storing data and a sense amplifier connected to the memory cells and a data line through a transistor, and has different refresh regions. In a semiconductor memory device having: a row control signal is activated and row control is started at each internal refresh performed during self-refresh, and then the row control signal is deactivated to terminate row control. Processing is performed after a certain time delay from the start of row control during normal operation, and when reading in the test mode, reading from the sense amplifier to the data line is completed, and the transistor causes the sense amplifier and the data line to be connected to each other. It is equipped with a self-refresh control circuit that activates after a fixed time after disconnection. The semiconductor memory device according to claim.