JPH09153283A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the yield of products and to prevent the destruction of stored data by the erroneous input of a command signal during precharge operations and refresh operations. SOLUTION: This device is provided with a refresh control circuit 3, internal control circuit 4 and internal refresh counter 12 which execute and control prescribed times of the refresh operations and precharge operations in response with the generation of one time of the refresh signal REF. This internal refresh counter 12 is provided with a function to generate a refresh operation period signal RFE which attains a high level during the execution of prescribed times of the refresh operations and the precharge operations. A command decoder 2 stops the generation of all the control signals (REF, ACT, PRE) while the refresh operation period signal RFE is at the high level.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a synchronous semiconductor memory device that performs a refresh operation in accordance with a refresh command input in synchronization with a clock signal.

[0002]

2. Description of the Related Art In recent years, a command of an external signal is input in synchronization with a clock signal, the command is decoded, various internal control signals are generated, and each part is activated to execute a write / read operation and a refresh operation. In addition, a synchronous semiconductor memory device such as a synchronous DRAM for precharging a bit line has appeared on the market.

FIG. 3 shows an example (first example) of such a semiconductor memory device.

The semiconductor memory device includes a plurality of memory cells MC arranged in a row direction and a column direction, and a memory cell MC of a corresponding row provided at a selected level and provided corresponding to each row of the plurality of memory cells MC Word lines (WL1, WL2, etc.) for selecting memory cells and a plurality of memory cells M
The data of the selected memory cells provided in correspondence with the odd-numbered memory cells and the even-numbered memory cells of each column of C (in FIG. 3, the odd-numbered memory cells and the even-numbered memory cells are shifted) are transmitted. Memory cell array 1 having a plurality of paired first and second bit lines (BL1, BL2, etc., hereinafter referred to as a bit line pair), and an external command input in synchronization with a clock signal CK. Signal CM
A command decoder 2x that decodes D to generate various control signals including a refresh signal REF, a RAS system activation signal ACT, and a precharge signal PRE, and a refresh start signal RF that receives the refresh signal REF.
A refresh control circuit 3x for generating a SET and an internal address control signal ACBR, receiving a refresh end timing signal RTO and generating a precharge start control signal PRR, and receiving one of a refresh start signal RESET and a RAS activation signal ACT. Becomes active level (low level) and the precharge start control signal DRR
RAS-related operation control signal RASB at an inactive level (high level) in response to one of the precharge signal PRE and the refresh start signal RFSET.
The internal control circuit 4x generates a refresh end timing signal RTO after a predetermined time, and the internal address generation circuit 5 generates an internal address signal ADI whose address value is updated in synchronization with the internal address control signal ACBR.
, An address buffer circuit 6 for inputting an external address signal ADE, and a refresh signal REF for RA.
When the S-system operation control signal RASB is at the active level, the RAS-system activation signal ACT is used as the internal address signal ADI.
When the RAS operation control signal RASB is at an active level, the plurality of word lines (WL1, WL
2), and a plurality of bit line pairs of the memory cell array 1 are set to a predetermined level when the RAS operation control signal RASB is at an inactive level. And a precharge circuit 8 for precharging and balancing the data, amplifying the data of the selected row of the memory cell array 1 through each bit line (BL1, BL2, etc.) by reactivating at a predetermined timing, and rewriting the row, and A sense amplifier / multiplexer 9 for writing data from the outside to a selected row, a column selecting circuit 10 for selecting one of a plurality of bit line pairs according to an address signal from an address buffer circuit 6, a selected row, , A data input / output buffer for reading data from a memory cell in a column to the outside and transmitting the data from the outside to a selected memory cell It has a configuration and a road 11.

Next, the refresh operation of this semiconductor memory device will be described with reference to the timing chart of the signals of the respective parts shown in FIG.

First, when a refresh command REFC based on a command signal CMD is input in synchronization with the clock signal CK, the command decoder 2x decodes this and generates a refresh signal REF. Upon receiving the refresh signal REF, the refresh control circuit 3x generates a refresh start signal RFSET and an internal address control signal ACBR, and the internal address generation circuit 5 outputs an internal address signal ADI having a predetermined address value.

On the other hand, the internal control circuit 4x receives the refresh activation signal RFSET and receives the RAS operation control signal RA.
SB is set to the active level, and as a result, the row selection circuit 7
Sets one word line (for example, WL1) to a selection level according to the internal address signal ADI and selects a corresponding row of the memory cell array 1.

The data of the memory cells in the selected row is amplified by the sense amplifier / multiplexer 9 through each bit line pair (BL1, BL2, etc.), and the amplified data is stored in the memory of the row selected through each bit line pair. The cell is rewritten.

The internal control circuit 4x generates a refresh end timing signal RTO after a lapse of a predetermined time after receiving the refresh start signal RFSET, that is, after the rewriting level has reached a sufficient level. 3x receives this and generates a precharge start control signal PRR. Internal control circuit 4x receives precharge start control signal PRR and receives RAS operation control signal RRR.
Set ASB to inactive level.

As a result, the row selection circuit 7 stops selecting a predetermined row (WL1 concave) of the memory cell array 1, and the precharge circuit 8 executes a precharge and balance operation for each bit line pair. Thus, one refresh cycle by one refresh command REFC is completed.

In the case of a 16 Mbit DRAM,
Usually, after about 16 μs, the next refresh command REF
C is input, and at this time, the address value of the internal address signal ADI is updated, for example, the word line WL2 is set to the selected level, and the data in the corresponding row is refreshed.

Normal write, read and precharge operations are designated by an external address signal ADE in accordance with a RAS system activation signal ACT generated by decoding an external RAS system activation command (ACTC). Writing and reading are performed on the addressed address, and each bit line pair is precharged according to a precharge signal PRE generated by decoding a precharge command (PREC) input subsequently.

Here, in the case of a 16 Mbit DRAM,
Normally, 4k bits are refreshed in one refresh cycle, and 4k refresh cycles are executed to complete the refresh of all bits.
Accordingly, the refresh period in which the refresh of all bits is completed is 64 ms, provided that the time of one refresh cycle is 16 μs.

As described above, when the memory capacity (the number of bits) increases, the refresh period becomes longer, and some data holding time is shorter than the refresh period. In this case, the stored data cannot be held. It is discarded as defective in time, and the product yield decreases.

Therefore, even if the data retention time does not satisfy the refresh period, the semiconductor device can retain the stored data without changing the refresh cycle time and can increase the product yield without being discarded. A memory device was proposed (for example,
No. 300178). In this semiconductor memory device, a plurality of refresh operations and a plurality of precharge operations are performed for different row addresses by generating one refresh signal REF.

FIG. 5 shows an example (second example) in which the technology of such a semiconductor memory device is applied to the above-described semiconductor memory device.

The semiconductor memory device of the second example is different from the semiconductor memory device of the first example shown in FIG. 3 in that the refresh operation and the precharge executed by one generation of the refresh signal REF are performed. The number of operations is selected and set. If the number of times of receiving the precharge end timing signal PXE after the generation of the refresh signal REF upon receiving the precharge end timing signal PXE is smaller than the above set number, the refresh request is made. An internal refresh counter 12x for generating a signal RFE is provided, and a refresh request signal RFE
In this case, a refresh start signal RFSET and a function of generating an internal address control signal ACBR are added to the refresh control circuit 3 and the internal control circuit 4x
After receiving a precharge start control signal PRR, a predetermined time (a time required for the precharge potential of the bit line to reach a sufficient level) elapses, the precharge end timing signal
In addition to providing the function of generating an E, the internal control circuit 4 sets the generation timing of each signal so that the refresh operation and the precharge operation can be performed a set number of times until the next refresh signal REF is generated. The number of refresh operations and the number of precharge operations that can be executed by the generation of the refresh signal REF can be selected and set.

FIG. 6 is a timing chart of the signals of each section when the number of times set as described above is plural.

The operation until the refresh operation of one row (corresponding to the word line WL1) of the memory cell array 1 after the refresh signal REF is generated and the precharge operation of the bit line is started is shown in FIGS. The semiconductor memory device shown in FIG. 6 is similar (however, the generation timing of the refresh end timing signal RTO is different).

After the generation of the precharge start control signal PRR, the internal control circuit 4 generates a precharge end timing signal PXE when a predetermined time has elapsed, and the internal refresh counter 12x receives and receives the precharge end timing signal PXE. Number of times (refresh signal RE
If F is less than the set number, the refresh request signal RFE is generated.

The refresh control circuit 3 receives the refresh request signal RFA and receives a refresh start signal RFSE.
T and the internal address control signal ACBR are generated, and the second refresh operation and precharge operation are executed by changing the address value of the internal address signal ADI.

Thereafter, similarly, the refresh operation and the precharge operation are executed the set number of times.

Thus, one refresh signal REF is performed according to the data holding time of the memory cell array 1.
The number of rows (the number of rows) of the refresh operation and the precharge operation that can be executed due to the occurrence of data can be selected and set, so that the number of items discarded due to data retention time failure can be reduced without changing the input timing of the command signal CMD from outside Can increase the product yield.

[0024]

In the above-mentioned conventional semiconductor memory device, in the first example, the refresh period becomes longer as the memory capacity increases, and the data retention time of the memory cell array 1 is shorter than the refresh period. There is a problem that the product yield is lowered because some of them are generated and discarded as data retention failure. In the second example,
Since the number of refresh operations and precharge operations (number of rows) to be executed by one generation of the refresh signal REF can be selected and set, the number of data retention time defects is reduced and the product yield is increased. The command signal CMD can be decoded from the outside even during the refresh operation and the precharge operation, and during this period, the RAS system activation signal ACT and the precharge signal PRE by the decoding of the command signal CMD due to a malfunction or an erroneous operation.
Occurs (see the broken line in FIG. 6), the precharge operation and the refresh operation are interrupted, and the precharge and rewrite levels do not reach a sufficient level, resulting in the destruction of stored data including those caused by erroneous reading. There is a risk of doing so. This is the same for the first example.

An object of the present invention is to increase the product yield without changing the input timing of an external command signal, and to cause storage data destruction due to erroneous input of a command signal during a precharge operation and a refresh operation. It is an object of the present invention to provide a semiconductor memory device which can prevent the occurrence of the problem.

[0026]

A semiconductor memory device of the present invention decodes a command signal from the outside to generate various control signals including a refresh signal, a row activation signal, and a precharge signal, and a memory A semiconductor memory device that performs a data refresh operation, a write / read operation on a cell array, and a bit line precharge operation. The semiconductor memory device performs a predetermined number of refresh operations and precharge operations by generating the refresh signal once. During the predetermined number of times of the refresh operation and the precharge operation, the generation of the various control signals by the decoding of the command signal from the outside is stopped, and the operation is performed by generating the refresh signal once. Select and set the number of refresh and precharge operations Configured to so that.

When the refresh operation period signal is at the first level, the external command signal is decoded to generate various control signals including the refresh signal, the row activation signal and the precharge signal, and the second control signal is generated. A command decoder that stops the generation of the various control signals when it is at a level, and an active level when one of the refresh signal, the row activation signal, and the refresh request signal is generated, and a predetermined period elapses and the precharge is performed. A row-related operation control signal that becomes an inactive level according to one of the signal generation is generated, and an internal address control signal is generated in response to the generation of one of the refresh signal and the refresh request signal, and the row-related operation control is performed. Precharge end timing after a predetermined time has passed since the signal became inactive level A control circuit for generating a ring signal,
The number of refresh operations and precharge operations executed by one generation of the refresh signal is selected and set, and the precharge end timing signal is generated after the generation of the refresh signal in response to the precharge end timing signal. If the number of times of reception is less than the set number of times, the refresh request signal is generated and a second level is generated in response to the generation of the refresh signal. An internal refresh counter that generates the refresh operation period signal that becomes a first level when the number of times the charge end timing signal is received becomes the same as the set number, and an address value in synchronization with the internal address control signal. To generate an internal address signal that is updated An address generation circuit, a row selection circuit that selects a predetermined row of the memory cell array in accordance with the internal address signal while the row-related operation control signal is at the active level, and a row selection circuit when the row-related operation control signal is at the inactive level. It comprises a precharge circuit for precharging each bit line of the memory cell array to a predetermined level, and a data refresh means for refreshing data of a selected row of the memory cell array through each bit line of the memory cell array. R.

Further, during a predetermined number of refresh operations and precharge operations executed by one generation of the refresh signal, the generation of a control signal of various control signals that induces the destruction of the data stored in the memory cell array is generated. Of the various control signals, the control signal that induces the destruction of the stored data in the memory cell array is configured as at least the refresh signal, the row activation signal, and the precharge signal.

[0029]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

This embodiment is different from the conventional semiconductor memory device shown in FIG. 5 in that the internal refresh counter 12x has a high level in response to the generation of the refresh signal REF, and the precharge after the generation of the refresh signal REF. In response to the precharge end timing signal PXE when the number of times the charge end timing signal PXE is received is equal to the set number of refresh operations and precharge operations executed by generation of one refresh signal REF, a low level is provided. A function of generating a refresh operation period signal PFE is added to form an internal refresh counter 12,
Instead of the command decoder 2x, the command signal CMD is decoded during a period when the refresh operation period signal RFE is at a low level, and various control signals (REF, ACT, PRE) are decoded.
And the like, and the command decoder 2 for stopping the generation of these various control signals during the high-level period is provided.

FIG. 2 is a timing chart of signals at various parts for explaining the operation of this embodiment.

In this embodiment, the process in which the refresh signal REF is generated by one decoding of the refresh command REFC and the refresh operation and the precharge operation are executed a predetermined number of times is shown in FIGS. This is the same as a conventional semiconductor memory device.

However, in this embodiment, when the refresh signal REF is generated, the level becomes high, and the precharge end timing of the same number of times as the set number of the refresh operation and the precharge operation when one refresh signal REF is generated. Upon receiving the signal PXE, a refresh operation period signal RFE which becomes low level is generated. During the high level period of the refresh operation period signal RFE, the command decoder 2 controls various control signals (REF, ACT,
PRE etc.) are stopped. Therefore, even if the RAS activation command ACTC or the precharge command PREC is input due to a malfunction or a malfunction (see FIG. 2).
Shows an example in which the precharge command PREC is erroneously input), the refresh operation and the precharge operation for the set number of times are normally executed without being influenced by these erroneously input commands, and the erroneous reading is performed. Therefore, it is possible to prevent the destruction of data including those caused by the above.

Further, since the number of times (the number of rows) of the refresh operation and the precharge operation executed by one generation of the refresh signal REF can be selected and set, the input timing of the command signal CMD from the outside is changed. Thus, the number of data retention time defects can be reduced and the product yield can be increased.

In this embodiment, while the refresh operation period signal RFE is at a high level, all the control signals (REF, AC
T, PRE) are stopped, but among these control signals, only control signals that cause destruction of data stored in the memory cell array 1, for example,
RAS system activation signal ACT, precharge signal PRE,
The generation of the refresh signal REF may be stopped.

[0037]

As described above, according to the present invention, the number of times of the refresh operation and the precharge operation executed by one generation of the refresh signal is selected and set, and these operations are executed. While these operations are being executed a number of times, generation of a control signal that causes destruction of data stored in the memory cell array among various control signals by decoding the command signal is stopped. The number of data retention time defects can be reduced and the product yield can be increased without changing the input timing of the command signal, and during a predetermined number of refresh operations and precharge operations associated with one refresh operation This prevents the stored data from being destroyed due to erroneous input of the command signal. .

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation and effect of the embodiment shown in FIG. 1;

FIG. 3 is a block diagram showing a first example of a conventional semiconductor memory device.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the semiconductor memory device shown in FIG. 3;

FIG. 5 is a block diagram showing a second example of a conventional semiconductor memory device.

6 is a timing chart of signals of respective parts for explaining the operation and problems of the semiconductor memory device shown in FIG. 5;

[Explanation of symbols]

 Reference Signs List 1 memory cell array 2, 2x command decoder 3, 3x refresh control circuit 4, 4x internal control circuit 5 internal address generation circuit 6 address buffer circuit 7 row selection circuit 8 precharge circuit 9 sense amplifier / multiplexer 10 column selection circuit 11 data input / output Buffer circuit 12, 12x Internal refresh counter BL1, BL2 Bit line MC Memory cell WL1, WL2 Word line

Claims (5)

[Claims] 1. An external command signal is decoded to generate various control signals including a refresh signal, a row-related activation signal, and a precharge signal, and a data refresh operation for a memory cell array, a write / read operation, and A semiconductor memory device for performing a precharge operation of a bit line, wherein a refresh operation and a precharge operation are performed a predetermined number of times by generating the refresh signal once, and a refresh operation and a precharge operation of the predetermined number of times are performed. During the period, the semiconductor memory device is characterized in that generation of the various control signals by decoding of the command signal from the outside is stopped. 2. The semiconductor memory device according to claim 1, wherein the number of refresh operations and precharge operations executed by one generation of the refresh signal can be selected and set. 3. When the refresh operation period signal is at the first level, an external command signal is decoded to generate various control signals including a refresh signal, a row activation signal and a precharge signal, and a second control signal is generated. A command decoder that stops the generation of the various control signals when it is at a level, and an active level when one of the refresh signal, the row activation signal, and the refresh request signal is generated, and a predetermined period elapses and the precharge is performed. A row-related operation control signal that becomes an inactive level according to one of the signal generation is generated, and an internal address control signal is generated in response to the generation of one of the refresh signal and the refresh request signal, and the row-related operation control is performed. Precharge end timing after a predetermined time has passed since the signal became inactive level A control circuit for generating a signal and the number of refresh operations and precharge operations executed by one generation of the refresh signal are selected and set, and the refresh signal is generated in response to the precharge end timing signal. If the number of times the precharge end timing signal is received is less than the set number of times, the refresh request signal is generated and a second level, the precharge end timing signal is received in response to the generation of the refresh signal. An internal refresh counter for generating the refresh operation period signal which is at a first level when the number of times the precharge end timing signal is received after the generation of the refresh signal becomes equal to the set number of times; The address value is updated in synchronization with the control signal An internal address generation circuit that generates an address signal, a row selection circuit that selects a predetermined row of the memory cell array according to the internal address signal while the row related operation control signal is at an active level, and the row related operation control signal A precharge circuit for precharging each bit line of the memory cell array to a predetermined level during an active level period, and a data refresh means for refreshing data of a selected row of the memory cell array through each bit line of the memory cell array The semiconductor memory device according to claim 1, further comprising: 4. A control signal for inducing destruction of stored data of a memory cell array among various control signals is generated during a predetermined number of refresh operations and precharge operations executed by generating a refresh signal once. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is stopped. 5. The semiconductor memory device according to claim 4, wherein among the various control signals, the control signal for inducing the destruction of the stored data in the memory cell array is at least a refresh signal, a row activation signal and a precharge signal.