JP2003150410A - Watchdog timer device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a watchdog timer capable of specifying a mode for combination of clock frequency and overflow control value in accordance with a program of application executed by a CPU and improving the prevention property so that mode change unintended by a user does not occur due to runaway of control of the CPU. SOLUTION: This watchdog timer 2 is constituted in such a way that it can specify a mode for combination of clock frequency and overflow control value by providing a mode register 11. Moreover, it is provided with an access number detection circuit 21 detecting access number to the mode register 11 so that it determines that, when there is the second access to the mode register 11, it is illegal access and the CPU runs away of control to output runaway-of- control detection interruption INT to the outside.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer device, and more particularly to a watchdog timer device with improved reliability of CPU runaway detection.

[0002]

2. Description of the Related Art A watchdog timer is generally used as a means for detecting runaway programs being executed by a CPU. FIG. 9A is a block diagram showing a computer system including a watchdog timer. The computer system includes a CPU 1, a watchdog timer 2a, an interrupt controller 3 and a memory 5 on a system bus 4.
Are connected and configured.

The CPU 1 executes a program stored in the memory 5. The program is divided into individual processing units that can be processed in a time shorter than a predetermined time Tovf when the timer counter overflows, and the CP is divided for each processing unit.
An access instruction from U1 to the watchdog timer 2a is embedded. The watchdog timer 2a is the CPU 1
When starts executing the program, the internal timer counter counts clock pulses. If there is an access instruction from the CPU 1 before the count value of the timer counter overflows and the write data accompanying the instruction matches the key bit held in advance in the watchdog timer, the processing is executed normally. If the timer counter is once cleared, the clock pulse counting is started again. The CPU 1 executes the next process in the program.

On the other hand, when the CPU 1 does not access the watchdog timer 2a and the count value of the timer counter overflows, or C
When the PU1 has accessed the watchdog timer 2a but the write data does not match the key bit, the watchdog timer 2a determines that the CPU 1 has gone into a runaway state due to an abnormality in program execution. Runaway detection interrupt INT is output. Interrupt controller 3
Is the runaway detection interrupt IN from the watchdog timer 2a.
When T is input, the CPU reset signal CPURST changes to C
Send to PU1 to reset CPU1.

FIG. 9B is a diagram showing an outline of the operation of the conventional watchdog timer 2a. The count value of the timer counter increases with time, and the timer counter is cleared and restarts counting from 0 each time there is access from the CPU 1 and the write data from the CPU 1 matches the key bit. There is no access from the CPU 1 and the count value of the timer counter is the overflow judgment value (OV
When it reaches the F value, the watchdog timer makes a runaway decision.

In the conventional watchdog timer, since the key bit preset in the watchdog timer is 1 bit, if the write data from the CPU is inverted for some reason, the CPU in the runaway state is normally operated. There is a risk that it will be judged that there is a problem with the reliability of normal access certification.

On the other hand, Japanese Unexamined Patent Publication No. 2-208748 discloses a watchdog timer in which the key data is composed of a plurality of bits to improve the reliability of match detection between the write data and the key data. In addition, JP-A-1-
Japanese Patent No. 147643 discloses a watchdog timer in which the count value of an increment counter that is incremented by 1 each time the timer counter is cleared is used as key data to improve the reliability of match detection. With these improved technologies, the probability that the write data consisting of multiple bits from the runaway CPU coincidentally coincides with the key data can be made extremely small, and the reliability of normal access authorization can be dramatically improved. It becomes possible.

[0008]

On the other hand, there is a strong demand for the setting of the combination of the clock frequency and the overflow judgment value to be changed according to the program of the application executed by the CPU. However,
If the setting can be changed, the clock frequency and the overflow determination value are changed from those appropriately set due to a program error during the program execution, a CPU runaway, or the like. For example, if the overflow determination value has been changed to a large value, it will be erroneously determined to be a normal operation even in the state where an overflow should occur and a runaway detection interrupt should be output. Similarly, when the clock is changed to select a clock with a high clock frequency, the runaway state is also erroneously determined to be normal operation.

According to the improved technique disclosed in Japanese Patent Laid-Open No. 2-208748 and the improved technique described in Japanese Laid-Open Patent Publication No. 1-147643, the reliability of matching of key data and write data can be improved. It was useless for rewriting due to an unexpected mistake in the dog timer clock frequency and overflow judgment value.

It is an object of the present invention to specify a mode such as a combination of a clock frequency and an overflow judgment value in accordance with an application program executed by the CPU, and to prevent a mode change not intended by the user due to a runaway of the CPU. To provide a watchdog timer with improved protection.

[0011]

A watchdog timer device according to the present invention includes a clock selection circuit for inputting a plurality of clocks from the outside and selecting and outputting a count clock from the clocks according to mode information, and a clear signal. A count value is cleared based on the above, and a timer counter that inputs the count clock and counts the number of pulses, and an overflow determination value is set according to the mode information, monitors the count value of the timer counter, and the count value overflows. An overflow detection circuit that detects that the threshold value is exceeded and outputs an overflow signal, a mode register that inputs and stores mode data and outputs the mode information based on the mode data, and an access from the CPU is detected. The access is to the mode register When the access is the first access, the data from the CPU is written to the mode register, and when the second access is the first runaway detection signal is output, and when the access from the CPU is not the access to the mode register In addition, comparing the data from the CPU with the key data from a plurality of bits, the clear signal is output if they match, and the second runaway detection signal is output if they do not match; the overflow signal, the first signal. And a runaway detection interrupt generation circuit for transmitting a runaway detection interrupt to the outside when at least one of the runaway detection signal and the second runaway detection signal is input.

Further, the unauthorized access determination unit is a CPU
Access from the CPU is detected, and when the access is to the mode register, if the access is the first time, the data from the CPU is written to the mode register, and if the access is the second time, the first runaway detection signal is output. The access count detection circuit and C when the access from the CPU is not an access to the mode register
A counter control register for storing data from the PU,
The key data setting circuit in which key data consisting of a plurality of bits is set is compared with the data stored in the counter control register and the key data, and if they match, the clear signal is output, and if they do not match, the second signal is output. And a comparator circuit that outputs a runaway detection signal.

[0013]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail with reference to the drawings. A computer system including the watchdog timer 2 of the present invention corresponds to a computer system including the watchdog timer 2a in the block diagram of the conventional computer system of FIG. Mode data M
DAT is written in the watchdog timer 2 by the CPU 1. FIG. 1 is a block diagram of an embodiment of a watchdog timer 2 of the present invention.

The watchdog timer 2 includes a mode register 11, a clock selection circuit 12, a count operation control circuit 13, a timer counter 14, and an overflow detection circuit 1.
5, runaway detection interrupt 16 and unauthorized access determination unit 17
It is configured with.

The mode register 11 uses the mode data MDAT transmitted from the CPU 1 to determine the unauthorized access determination unit 17.
It is input and stored via the control unit and the mode information MODE including the combination information of the count clock selection and the overflow determination value is output based on the stored mode data MDAT.

The clock selection circuit 12 inputs a plurality of clocks CK1, CK2, CK3 from the outside, selects the count clock CKC from the input clocks according to the mode information MODE, and outputs it.

When the count operation control circuit 13 receives the mode information from the mode register 11, the timer counter 1
The clear signal CCLR is output to 4 and then the count clock CKC input from the clock selection circuit 12 is output as it is. Further, the count operation control circuit 13 outputs the clear signal CCLR to the timer counter 14 when receiving the clear signal CLR from the unauthorized access determination unit 17.

The count value of the timer counter 14 is cleared by the clear signal CCLR from the count operation control circuit 13, and the count clock CKC is input from the count operation control circuit 13 to count the pulses of the count clock.

In the overflow detection circuit 15, the overflow judgment value is set by the mode information MODE from the mode register 11. Further, the overflow detection circuit 15 monitors the count value of the timer counter 14,
When it is detected that the count value has exceeded the overflow determination value, the overflow signal OVF is output.

The unauthorized access judging section 17 detects an access from the CPU 1, and the access is detected by the mode register 1
When it is an access to 1, it is detected whether it is the first access or the second access after the CPU 1 is started up. CP for the first access
The mode data MDAT from U1 is written in the mode register, and if it is the second access, the first runaway detection signal RAa is output. When the access from the CPU 1 is not the access to the mode register 11, the CPU
The write data WDAT from 1 is compared with the key data set inside, and if they match, a clear signal CLR is output. If they do not match, the second runaway detection signal RAb is output.

The runaway detection interrupt generation circuit 16 receives the overflow signal OVF from the overflow detection circuit 15, receives the first runaway detection signal RAa from the unauthorized access determination unit 17, and from the unauthorized access determination unit 17. When at least one of the cases where the second runaway detection signal RAb is received actually occurs, the runaway detection interrupt INT is transmitted to the external interrupt controller 3.

The unauthorized access determination section 17 is further provided with an access count detection circuit 21, a key data setting circuit 22, a counter control register 23 and a comparison circuit 24.

The access number detection circuit detects an access from the CPU 1, and the access is detected by the mode register 11
If it is the first access, the mode data MDAT from the CPU 1 is written in the mode register 11 if it is the first access, and if it is the second access, it is an unauthorized access and the first runaway detection signal RAa Is output.

Key data having a plurality of bits is set in the key data setting circuit 22. The counter control register 23 is accessed by the CPU 1 in the mode register 1
If it is not an access to 1, the write data WDAT from the CPU 1 is stored. The comparison circuit 24 compares the write data stored in the counter control register 23 with the key data set in the key data setting circuit 22, outputs a clear signal CLR if they match, and outputs a second runaway if they do not match. The detection signal RAb is output.

FIG. 2 is a circuit diagram of a comparison portion of write data and key data in the first embodiment. In the present embodiment, as the key data setting circuit 22 of FIG. 1, a key data setting circuit 22a in which fixed data of 8 bits (for example, data ACH; H at the end indicates that it is a hexadecimal representation) is used. The same fixed data (AC
H) is set and fixed data is sent from the CPU 1 to the watchdog timer 2 as write data and stored in the counter control register 23 every time the processing in the program is normally executed. The fixed data (ACH) of the key data setting circuit 22a and the 8-bit write data WDAT stored in the counter control register 23 are the same (A
CH), the comparison circuit 24 outputs the clear signal CL.
Output R. When the write data WDAT is data other than (ACH), it indicates that the process in the CPU 1 has not been normally executed, and therefore the comparator circuit 24 outputs the second runaway detection signal RAb as the runaway state.

The key data setting circuit 22a may be configured by a logic gate so as to output fixed data (ACH), or may be realized by fixedly storing the key data (ACH) in a register.

FIG. 3 is an operation flow chart of the watchdog timer of this embodiment. The operation of this embodiment will be described with reference to FIGS. 1, 2, and 3.

First, after powering on the CPU 1 or the CPU
After the reset of 1, the mode register 1
1 and the access count detection circuit 21 are cleared by a signal from the outside (for example, from the CPU 1).

Until there is an access from the CPU 1, the answer is NO in step S2, and the answer is NO in step S8 to wait. When there is an access from the CPU 1 in step S2, the process proceeds to step S3, and it is determined whether the access is to the mode register 11. The first access from the CPU 1 is the mode data MD in the mode register 11.
Since the access should be for writing the AT, the process proceeds to step S4.

In step S4, since the mode register 11 is accessed for the first time, the access count value of the access count detection circuit 21 is 0, and the flow advances to step S5. In step S5, the mode data MD including the combination information of the count clock selection information and the overflow determination value is included.
AT is written in the mode register, and the access count value of the access count detection circuit 21 is set to 1. Next, in step 6, the timer counter is cleared by the mode information MODE from the mode register 11, and the clock selection circuit 1
In 2, the count clock CKC is selected from a plurality of clocks input from the outside, and the overflow determination value is set in the overflow detection circuit 15. Next, in step S7, the timer counter 14 starts counting.

While the timer counter 14 is counting, it is always determined in step S2 whether there is an access from the CPU 1, and if there is no access, it is determined in step S8 whether an overflow has occurred. When the overflow signal OVF is output from the overflow detection circuit 15 because the count value of the timer counter 14 has reached the overflow determination value in step S8, the runaway detection interrupt generation circuit 16 detects the runaway of the CPU 1 and outputs the runaway detection interrupt INT. Output to the external interrupt controller 3. Upon receiving the runaway detection interrupt INT, the interrupt controller 3 sends a CPU reset signal CPURST to the CPU 1 to reset the CPU 1.

While the timer counter 14 is counting, the CPU
If there is an access from 1, the process proceeds from step S2 to step S3, and it is determined whether or not it is an access to the mode register 11. In the case of access to the mode register, the access count value of the access count detection circuit 21 has already become 1, so that the determination in step S4 is NO, and the access count detection circuit 21 outputs the first runaway detection signal R.
Output Aa. In response to the first runaway detection signal RAa, the runaway detection interrupt generation circuit 16 outputs a runaway detection interrupt INT to the interrupt controller 3, and the interrupt controller 3 resets the CPU 1.

While the timer counter 14 is counting, the CPU
If it is determined that the mode register 11 is not accessed in step S3, the process proceeds to step S9 and the write data WDAT from the CPU 1 is accessed.
It is determined whether or not the key data set in the key data setting circuit 22 match. If the comparison circuit 24 determines that they match, the process proceeds to step S10 to clear the count value of the timer counter 14 once, and then moves to step S7 to restart the counting of the timer counter 14. If the comparison circuit 24 determines in step S9 that the write data and the key data do not match, the comparison circuit 24 determines that the second runaway detection signal RAb has occurred.
Is output. In response to the second runaway detection signal RAb, the runaway detection interrupt generation circuit 16 outputs a runaway detection interrupt INT to the interrupt controller 3, and the interrupt controller 3 sends CP.
Reset U1.

That is, when the CPU 1 is executing the program normally, the watchdog timer 2 operates from step S2 to step S3, step S9 and step S9.
10. The loop that returns to step S2 again through step S7 is repeated to operate. When there is no access from the CPU 1 and the count value of the timer counter 14 reaches the overflow value (YES in step S8), and when the mode register is accessed for the second time (N in step S4).
O) and the write data and the key data do not match (NO in step S9), the watchdog timer 2 determines that the CPU 1 is in the runaway state when at least one of the three cases occurs. .

As described above, in the watchdog timer of this embodiment, the mode register 11 is provided so that the combination of the clock frequency and the overflow determination value can be designated as the mode, and the mode can be set in the unauthorized access detection unit 17. A mechanism (access count detection circuit 21) for detecting the number of accesses to the register 11 is provided, and when the mode register is accessed for the second time, it is an illegal access and the CPU 1 is out of control, and a runaway detection interrupt INT is output to the outside. Is configured as follows. As a result, it is possible to select a combination of the clock frequency and the overflow determination value according to the application program executed by the CPU, and it is possible to remarkably improve the protection against access for mode change not intended by the user. Further, since the key data has a plurality of bits, the same reliability as that of the conventional example disclosed in Japanese Patent Application Laid-Open No. 2-208748 is guaranteed in the coincidence recognition of the key data and the write data.

Next, a second embodiment of the present invention will be described. FIG. 4 is a circuit diagram of a comparison part of write data and key data in the second embodiment.

The second embodiment is different only in that a key data setting circuit 22b is provided in place of the key data setting circuit 22 in FIG. 1, and the other structure is the same as that in FIG. The key data setting circuit 22b includes an increment counter 31 that inputs the clear signal CLR each time it is output from the comparison circuit 24 and increments it by one. The count value of the increment counter 31 is set as key data.

The CPU 1 easily counts the number of times the clear signal is generated in the watchdog timer 2, that is, the count value of the increment counter, by counting the number of accesses to the watchdog timer in the program being executed. Can be reproduced.

When the processing in the program is normally executed, the CPU 1 sends the key data ((01H) in the example of FIG. 4) reproduced on the CPU 1 side to the watchdog timer 2 as the write data WDAT. Key data setting circuit 22b
Count value of the increment counter 31 (01H)
And the write data WDAT from the CPU 1 stored in the counter control register 23 match, the comparison circuit 24 outputs the clear signal CLR. When the count value of the increment counter 31 and the write data WDAT do not match, it indicates that the process in the CPU 1 has not been normally executed, and therefore the comparator circuit 24 outputs the second runaway detection signal RAb as the runaway state.

FIG. 5 is an operation flow chart of the watchdog timer of the second embodiment. The difference from the first embodiment is that after the count value of the timer counter 14 is cleared by the clear signal CLR in step S10, the key data is updated in the newly inserted step S21, after which the process moves to step S7 and the timer counter is moved. The only point is to restart the count of 14. In the second embodiment, step S2
1, the key data setting circuit 22b is the comparison circuit 2
Increment counter 3 that inputs the clear signal CLR every time it is output from 4 and increments it by 1
1, the key data is updated by setting the count value of the increment counter 31 as the key data.

When the CPU 1 is executing the program normally, the watchdog timer 2 repeats the loop from step S2 to step S3, step S9, step S10, step 21, step S7 and back to step S2. To do. When the increment counter 31 has an 8-bit structure, the key data is (00H) to (01H), (02H) every time this loop is passed once.
(Increases to (FFH) and returns to (00H) again.

In the second embodiment as well, similar to the first embodiment, the combination of the clock frequency and the overflow judgment value can be selected according to the program of the application executed by the CPU, and the mode change not intended by the user. Can significantly improve the protection against access. In addition, since the key data is generated by the increment counter that counts the clear signal, the key data is changed each time the CPU accesses it. With improved accuracy,
High reliability equivalent to that of the improved conventional example described in Japanese Patent No. 7643 is guaranteed.

Next, a third embodiment of the present invention will be described. FIG. 6 is a circuit diagram of a comparison portion of write data and key data in the third embodiment.

The third embodiment is the same as FIG. 1 except for the point that a key data setting circuit 22c is provided instead of the key data setting circuit 22 in FIG. The key data setting circuit 22c is provided with two increment counters 41 and 42 of the same bit length (4 bits in the example) that input and increment the clear signal CLR each time the comparison circuit 24 outputs the clear signal CLR. Among the increment counters, the 8-bit key data is set with the count value of the increment counter 42 as the upper digit and the count value of the increment counter 41 as the lower digit.

The set key data is the clear signal CL.
Each time R is input, (00H) to (11H), (22
H), (33H) ... (FFH), and again (00
Return to H).

In this embodiment as well, as in the second embodiment, the CPU 1 reproduces the count values of the two increment counters by counting the number of accesses to the watchdog timer in the program being executed. Key data can be easily generated.

When the processing in the program is normally executed, the CPU 1 sends the key data ((11H) in the example of FIG. 6) reproduced on the CPU 1 side to the watchdog timer 2 as the write data WDAT. Key data setting circuit 22c
Of the key data (1H) set by synthesizing the count value (1H) of the upper digit increment counter 42 and the count value (1H) of the lower digit increment counter 41.
1H) and the write data WDAT stored in the counter control register 23 match, the comparison circuit 24 outputs a clear signal CLR. When the key data set with the count value of the increment counter 42 as the upper digit and the count value of the increment counter 41 as the lower digit do not match the write data WDAT, CP
The comparison circuit 24 outputs the second runaway detection signal RAb because it is in a runaway state because it indicates that the process in U1 has not been normally executed.

Also in this embodiment, the first embodiment and the second embodiment
Similar to the embodiment, the combination of the clock frequency and the overflow judgment value can be selected according to the program of the application executed by the CPU, and the protection against the access of the mode change not intended by the user can be remarkably improved. it can.

Further, since the count values of the two increment counters are combined to generate the key data, when the key data is updated, the number of bits of 2 bits or more is changed to the changed key data. Therefore, the relationship with the previous key data can be diluted, and it is possible to further improve the accuracy in recognizing the coincidence between the key data and the write data as compared with the second embodiment.

Next, a fourth embodiment of the present invention will be described. FIG. 7 is a circuit diagram of a comparison part of write data and key data in the fourth embodiment.

The fourth embodiment is the same as FIG. 1 except for the point that a key data setting circuit 22d is provided instead of the key data setting circuit 22 in FIG. The key data setting circuit 22d includes an increment counter 51 that inputs and increments a clear signal CLR each time the comparison circuit 24 outputs the clear signal CLR, and a parity bit 5.
2 and a parity generation circuit 53 that determines the value of the parity bit 52. The key data is set such that the upper digit is the count value of the increment counter 51 and the least significant digit is the value of the parity bit 52. In FIG. 7, the increment counter 51 has 7 bits (bit7 to bit1).
The value of the parity bit (bit0) 52 is determined by the parity generation circuit 53 of the even parity method.

In this example, the set key data is from (00H) to (03) every time the clear signal CLR is input.
H), (05H), (06H) ... (FFH)
Return to (00H) again.

Also in this embodiment, the CPU 1 can reproduce the count value of the increment counter by counting the number of accesses to the watchdog timer in the program being executed. The key data can be easily reproduced by performing parity generation and combining with.

When the processing in the program is normally executed, the CPU 1 sends the key data ((59H) in the example of FIG. 7) reproduced on the CPU 1 side to the watchdog timer 2 as the write data WDAT. Key data setting circuit 22d
Count value of the increment counter 51 (0
101100) and parity bit 5 with even parity
When the key data in which the value (1) of 2 is combined (01011001), that is, (59H), and the write data WDAT stored in the counter control register 23 match, the comparison circuit 24 outputs the clear signal CLR. Output. When the key data set by combining the count value of the increment counter 51 and the value of the parity bit 52 do not match the write data WDAT, CP
The comparison circuit 24 outputs the second runaway detection signal RAb because it is in a runaway state because it indicates that the process in U1 has not been normally executed.

In this embodiment as well, as in the other embodiments, C
The combination of the clock frequency and the overflow determination value can be selected according to the program of the application executed by the PU, and the protection against access for mode change not intended by the user can be significantly improved.

Further, since the count value of the increment counter and the parity bit value are combined to generate the key data, the relevance to the previous key data can be diluted when the key data is updated. It is possible to further improve the accuracy in recognizing the coincidence of the key data and the write data as compared with the embodiment.

Although the parity generation circuit 53 determines the value of the parity bit 52 using the even parity method in FIG. 7, the parity generation circuit 53 may use the odd parity method. In the key data generation, the parity bit 52 may be the highest digit and the increment counter 51 may be the lower digit.

Next, a fifth embodiment of the present invention will be described. FIG. 8 is a circuit diagram of a comparison part of write data and key data in the fifth embodiment.

The fifth embodiment is the same as FIG. 1 except for the point that a key data setting circuit 22e is provided instead of the key data setting circuit 22 in FIG. The key data setting circuit 22e includes a memory 61 storing different data at predetermined consecutive addresses (XX0H to XX7H in FIG. 8) and a clear signal CL from the comparison circuit 24.
R is output, and every time it is input, 1 is added to the read address ADR of the memory 61 to update to a new read address ADR, and the last address (XX7H) of the predetermined consecutive addresses is the read address. Sometimes clear signal C
When LR is input, the ring address generation circuit 62 that updates the read address to the top address (XX0H)
And the read address ADR of the ring address generation circuit 62.
And a key data register 63 for storing the data stored at the address of the memory 61 pointed to by. The data stored in the key data register 63 is set as the key data.

In the embodiment of FIG. 8, in the memory 61, every time the clear signal CLR is input, the lower part of the read address ADR is cyclically designated as (0H), (1H) ... (7H), (0H). , Used as a ring buffer. As a result, the set key data is from (48H) to (93H) ... in order of address every time the clear signal CLR is input.
It changes to (65H) and returns to (48H) again.

Also in this embodiment, the CPU 1 can reproduce the read address of the ring address generation circuit 62 by counting the number of accesses to the watchdog timer in the program being executed. In FIG. 9A, the memory 6 is connected to the memory 5 connected to the system bus 4.
If the ring buffer storing the same data as 1 is configured by software, the CPU 1 can easily obtain the key data from the ring buffer provided in the memory 5 based on the reproduced read address.

When the processing in the program is normally executed, the CPU 1 sends the key data ((ACH) in the example of FIG. 8) reproduced on the CPU 1 side to the watchdog timer 2 as the write data WDAT. Key data setting circuit 22e
At the read address ADR (X
When the key data (ACH) read from X3H) and set in the key data register 63 matches the write data WDAT stored in the counter control register 23, the comparison circuit 24 outputs a clear signal CLR. When the key data set in the key data register 63 does not match the write data WDAT, the CPU
The comparison circuit 24 outputs the second runaway detection signal RAb because it is in the runaway state because it indicates that the process in 1 is not normally executed.

In this embodiment as well, as in the other embodiments, C
The combination of the clock frequency and the overflow determination value can be selected according to the program of the application executed by the PU, and the protection against access for mode change not intended by the user can be significantly improved.

Further, in the present embodiment, since a plurality of data stored in the memory 61 can be set so as not to be related to each other by using data generated as a pseudo-random number, the second data can be set. Example, Third Example,
Compared to the fourth embodiment, the reliability can be further improved in recognizing the matching of the key data and the write data.

In the fifth embodiment, the memory 61 may be provided in the memory 5 of FIG. 9 (a). In the case of such a configuration, the read address ADR from the ring address generation circuit 62 is sent to the memory 5 via the system bus 4, the data in the area of the memory 61 provided in the memory 5 is read, and the key is read. It is stored in the data register 63 and set as key data. The CPU 1 obtains the key data from the area of the memory 61 provided in the memory 5 based on the reproduced read address. Since it is not necessary to physically provide the memory 61 in the key data setting circuit 22e, the area of the key data setting circuit 22e can be reduced.

[0066]

As described above, in the watchdog timer of the present invention, the mode register is provided so that the combination of the clock frequency, the overflow judgment value and the like can be designated as the mode, and the number of accesses to the mode register can be set. When a second access to the mode register is provided with a detection mechanism, it is configured to output a runaway detection interrupt to the outside assuming that the CPU has runaway due to illegal access. It is possible to select a combination of the clock frequency and the overflow determination value, and it is possible to remarkably improve the protection against access for mode change not intended by the user.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a watch dog timer 2 of the present invention.

FIG. 2 is a circuit diagram of a comparison portion of write data and key data in the first embodiment.

FIG. 3 is an operational flowchart of the watchdog timer of the first embodiment.

FIG. 4 is a circuit diagram of a comparison part of write data and key data in the second embodiment.

FIG. 5 is an operation flowchart of the watchdog timer of the second embodiment.

FIG. 6 is a circuit diagram of a comparison part of write data and key data in the third embodiment.

FIG. 7 is a circuit diagram of a comparison part of write data and key data in the fourth embodiment.

FIG. 8 is a circuit diagram of a comparison part of write data and key data in the fifth embodiment.

FIG. 9A is a block diagram showing a computer system including a watchdog timer, and is a diagram showing an outline of operation of a conventional watchdog timer.

[Explanation of symbols]

1 CPU 2, 2a Watchdog timer 3 Interrupt controller 4 System bus 5, 61 Memory 11 Mode register 12 Clock selection circuit 13 Count operation control circuit 14 Timer counter 15 Overflow detection circuit 16 Runaway detection interrupt generation circuit 17 Unauthorized access determination unit 21 Access Count detection circuit 22, 22a, 22b, 22c, 22d, 22e Key data setting circuit 23 Counter control register 24 Comparison circuit 31, 41, 42, 51 Increment counter 52 Parity bit 53 Parity generation circuit 62 Ring address generation circuit 63 Key data register

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Takehito Hayakawa             1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa             53 NC Micro Systems Stock Association             In-house F-term (reference) 5B042 JJ13 JJ21 JJ24 JJ29 JJ38                       KK01 LA20 MC25

Claims (7)

[Claims] 1. A clock selection circuit for inputting a plurality of clocks from the outside and selecting and outputting a count clock from the clocks according to mode information, and a count value that is cleared based on a clear signal and the count clock is input. A timer counter that counts the number of pulses, and an overflow determination value is set according to the mode information, and the count value of the timer counter is monitored to detect that the count value is equal to or greater than the overflow determination value. An overflow detection circuit for outputting the mode data, a mode register for inputting and storing the mode data and outputting the mode information based on the mode data, an access from the CPU, and when the access is an access to the mode register, the first time Access When the data from the PU is written to the mode register and the second access is made, the first runaway detection signal is output, and when the access from the CPU is not the access to the mode register, the data from the CPU is converted from a plurality of bits to key data. And an unlawful access determination section that outputs the clear signal if they match and a second runaway detection signal if they do not match, and the overflow signal, the first runaway detection signal, and the second runaway detection. A watchdog timer device, comprising: a runaway detection interrupt generation circuit that transmits a runaway detection interrupt to the outside when at least one of the signals is input. 2. The unauthorized access determination unit detects an access from a CPU, and when the access is an access to the mode register, if the access is a first access, writes data from the CPU to the mode register and a second access. If it is an access, an access frequency detection circuit that outputs a first runaway detection signal, a counter control register that stores data from the CPU when the access from the CPU is not an access to the mode register, and key data composed of multiple bits Is compared with the key data setting circuit, and the data stored in the counter control register is compared with the key data. If they match, the clear signal is output, and if they do not match, the second runaway detection signal is output. The watchdog according to claim 1, further comprising a comparison circuit. Timer devices. 3. The watch dog timer device according to claim 2, wherein the key data setting circuit is set with a fixedly fixed data consisting of a plurality of bits. 4. The key data setting circuit includes an increment counter that increments each time the clear signal is input, and the count value of the increment counter is set as key data. Watchdog timer device. 5. The key data setting circuit includes two increment counters having the same bit length that are incremented each time the clear signal is input, and one count value of the two increment counters is a higher digit. 3. The watchdog timer device according to claim 2, wherein the key data is set with the other one count value as a lower digit. 6. The key data setting circuit includes an increment counter that increments each time the clear signal is input, a parity bit, and a parity generation circuit that determines the value of the parity bit, and the count value of the increment counter. 3. The watchdog timer device according to claim 2, wherein key data is set by synthesizing the value of the parity bit with the value of the parity bit. 7. The key data setting circuit adds a new read address by adding 1 to the read address of the memory each time the clear signal is input, and a memory in which different data are stored at predetermined consecutive addresses. A ring for updating the read address to the first address of the predetermined continuous addresses when the clear signal is input when the last address of the predetermined continuous addresses is the read address address. An address generation circuit and a register for storing data stored at an address of the memory pointed to by a read address of the ring address generation circuit, wherein the data stored in the register is set as key data. Item 2. A watchdog timer device according to item 2.