JP2003148997A - Information processing and controlling device for enhancing noise resistance and noise margin detection means therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a noise margin detection means 2A which can set the number of stages 22 of digital filters 21-23 according to the magnitude of noise 3N, and to provide an information processing and controlling device which is used for notifying the outside of a fact that the noise generating period exceeds a predetermined set value when it has occurred and enhances the noise resistance by masking a system reset signal 11a from the information processing and controlling device 1 for a period B for detecting the noise. SOLUTION: This information processing/controlling device 1 having a measurement means 24 for measuring a pulse width signal 12a, is provided with a noise detection means 12 for detecting the noise 3N; the noise margin detection means 2B for filtering the noise component 12n detected by the detection means 12 through the digital filters 21-23 and for detecting the magnitude of the detected noise in the period B; and the control means 22 for setting and controlling the number of stages of the digital filters.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process data input device, and more particularly, to an information processing / control device for monitoring the output of an analog / digital signal conversion circuit for converting an analog input signal into a digital signal to improve noise resistance, and the same. The present invention relates to noise resistance amount detecting means.

[0002]

2. Description of the Related Art A process data input / output device sends and receives analog signals and digital signals such as relays to and from sensors and operating terminals arranged in the field, and transfers these signals to an information processing / control device. To do. In addition, there are various intrusion routes for noise that enters the information processing / control device, one of which is the noise signal source (for example, opening and closing the power supply of a huge motor) and the signal line (cable) of the process data input / output device. Invades electromagnetically in the form of.

In particular, mV-order analog input signals such as thermocouples are generally susceptible to the opening and closing of the power source of a giant motor. FIG. 5 shows the prior art relating to the present invention.
The effect of the noise 3N superimposed on the analog signal Ai on the digital system will be described by taking the pulse width conversion means as an example. In FIG. 5A, as the pulse width conversion means (PWM) 4C, for example, an analog signal Ai is converted into a pulse width signal by comparing the analog signal Ai and the triangular wave signal 43C with a comparator 43. . At this time, if the noise 3N is superimposed on the analog signal Ai, the output of the comparator 43 is easily affected by the noise before and after the output is switched, and a pulse disturbance 43n is likely to occur. Therefore, the analog noise filter AN
By providing F 3, the noise 3N is attenuated to the noise 3n. When the comparator 43 has a hysteresis characteristic, the pulse disturbance 43n does not occur in the pulse width modulation signal 43a when the attenuation noise 3n is within the dead band width Δ of the hysteresis characteristic. However, when the attenuation noise 3n exceeds the dead zone width Δ, pulse disturbance 43n occurs.

Next, the principle of a double integration type analog-to-digital signal conversion circuit (hereinafter abbreviated as ADC) which is often used when handling analog signals in an information processing / control device and has a high noise elimination performance. A simple circuit example will be described. In FIG. 5B, in an information processing / control device in which noise intrusion is intense, an analog noise filter including analog elements such as a capacitor and a noise filter is used.
(ANF) 3 first noise 3N superimposed on analog input signal Ai
Noise component 3n that cannot be completely removed by this noise filter (ANF) 3 (comparator for ADC 4 in (C) of FIG. 5)
A two-stage method in which a noise component 43n of the output of 43 is removed by a digital filter (hereinafter abbreviated as DNF) 44 is adopted.

In FIG. 5B, in the illustrated example, the analog signal Ai connected to the process data input / output device by external wiring such as a cable has a burst noise 3N superimposed thereon, and an analog noise filter (ANF) 3 This noise 3N is attenuated by and is converted into a digital signal 45a by ADC 4 and read by the central processing unit CPU 5. In FIG. 5C, the analog-to-digital signal converter ADC 4 has a simple response by the integration method strong in noise by filtering the noise 3n contained in the input signal Ai by its own integration operation although the response speed is slightly slow. With such a configuration, for example, double integrator circuits 41 to 43 for converting the analog signal Ai into a pulse width signal.
, Digital filter (DNF) 44 and counter (COUNT) 4
It consists of 5 and.

With this configuration, the analog signal Ai is shown in FIG.
As shown in (D) of, the input switching unit 41 is switched at timing t0 by the command from the CPU 5, and the analog input signal is input.
Input Ai to integrator 42. In the illustrated example, the analog signal Ai is output by the double integration circuit 42 for a predetermined period Ts.
(In the illustrated example, the input signals Ex1 and Ex2 are shown) are integrated.
Then, at timing t1, the input switching unit 41 is switched by a command from the CPU 5, and the reference voltage Er is input to the integrator 42,
The value integrated by the input signals Ex1 and Ex2 is reset with the reference voltage Er. The comparator 43 outputs the pulse width modulation signal 43a until the output of the integrator 42 becomes zero.

The double integrator circuits 41 to 43 measure the reset period Tx1 and Tx2 from the timing t1 to the timing t2 or t3 with the counter 45 by using the pulse width modulated signal 43a with the clock CLK, and the measured value Tx (= Read Tx1, Tx2) into CPU 5. The CPU 5 can perform analog-to-digital conversion with the analog input signal Ex = (Tx / Ts) Er by processing the measured value Tx.

When the noise 3N superimposed on the analog signal Ai is within a predetermined design value, the analog noise filter ANF
Noise 3n is attenuated by 3, and the remaining noise component is AD
It is possible to ensure a predetermined analog-digital conversion accuracy by being attenuated by the double integration circuit 42 of C 4. When the noise 3n exceeds the standard value, the error of analog / digital conversion accuracy starts to increase. When the noise 3n further increases, pulse turbulence is output to the pulse width conversion output 43a of the double integration circuits 41 to 43.
43n occurs. This turbulence 43n is particularly likely to occur near the end points (that is, t2 and t3) of the reset periods Tx1 and Tx2 of the pulse width modulation signal 43a of the double integrator circuits 41 to 43 shown in FIG. 5D.

For this reason, in the prior art for further improving the noise resistance performance, a digital noise filter DNF 44 is inserted to remove, for example, pulse disturbance 43n of a predetermined number of pulses or a predetermined time. Digital noise filter DNF 44 and analog noise filter ANF
A two-stage method that uses 3 and 3 together is adopted.

[0010]

However, in the method of adopting the digital noise filter for removing the disturbance of the pulse of the predetermined number of pulses or the predetermined time according to the prior art, the pulse for removing the disturbance of the pulse is used. If the number of times or the size of time is increased, the noise immunity is improved, but if the system operating speed slows down and an information processing / control device that requires high-speed processing cannot adopt a large digital noise filter. was there.

Further, since the reset signal used for control is affected by noise without exception, a protection means for synchronizing with the clock is used. Further, in a use environment in which noise larger than the assumed noise environment occurs, the information processing / control device malfunctions, but in some cases the cause cannot be identified. In particular, noise has a low reproducibility due to its nature, and even if a noise investigation is performed, there is a high possibility that the cause cannot be grasped unless noise is generated at that time.

Further, when the above-mentioned large noise is generated when the system reset of the information processing / control device is performed,
Since it cannot be removed by clock synchronization, the entire system of the information processing / control device may malfunction. The present invention has been made in view of the above points, and an object thereof is to solve the above-mentioned problems, devise a digital filter circuit to detect the magnitude of noise as a pulse width, and (1)
Noise tolerance detection means that can set the number of digital filter stages according to the noise level according to the noise environment level, and (2) this noise tolerance detection means allows the noise occurrence time width to be set to a preset value. By providing means for notifying the outside when exceeding the limit, and (3) means for masking the system reset signal from the information processing / control device during the period when the noise tolerance detection means detects noise, noise resistance It is an object of the present invention to provide an information processing / control device and a noise withstand amount detecting means for enhancing the information processing.

[0013]

According to the present invention, in the information processing / control apparatus having the measuring means for measuring the pulse width signal, the above-mentioned object is to detect the noise by the noise detecting means and the noise detecting means. A noise withstanding amount detection means for filtering the noise component with a digital filter and detecting the magnitude of the detected noise in a time width, and a control means for setting / controlling the number of filter stages of the digital filter are provided.

With such a configuration, the analog input signal can be detected with its ADC conversion accuracy at a presumed noise environment level, and the magnitude of noise entering from the wiring system can be detected as the pulse width. Further, in an information processing / control device having a measuring means for measuring a pulse width signal, a noise detecting means for detecting noise and a noise component detected by this noise detecting means are filtered by a digital filter,
It is provided with a noise tolerance detecting unit that detects the magnitude of the detected noise in a time width, and a notification unit that notifies the outside when the time width in which the noise is generated exceeds a predetermined set value. .

With this configuration, it is possible to notify the abnormality to the outside when the time width in which the noise is generated exceeds the preset value. As a result, for example, it is possible to easily grasp the cause of the noise by holding the data of the noise occurrence time and the magnitude of the generated noise and analyzing the data. Further, in an information processing / control device having a measuring means for measuring a pulse width signal, a noise detecting means for detecting noise and a noise component detected by the noise detecting means are filtered by a digital filter to determine the magnitude of the detected noise. And a mask control means for masking a system reset signal of the information processing / control device during a period in which the noise withstand amount detecting means detects noise.

With this configuration, the system reset signal of the information processing / control device can be masked while noise is being detected. As a result, even if an extremely large amount of noise enters and the information processing / control device enters an abnormal state, the system reset in this abnormal state is canceled, and when the noise is removed and the system becomes stable, the system is reset. The information processing / control device can be prevented from being locked in in an abnormal state by restarting by performing the restart, and a more reliable information processing / control device can be configured to improve noise resistance.

The noise detecting means receives the analog input signal from the outside and converts it into a pulse width signal according to the size of the analog input signal, or a pulse width converting means and the pulse width converting means. Analog to digital-to-analog signal conversion by measuring the signal
A digital signal conversion circuit (ADC) is provided, and the turbulence of the pulse generated immediately after the pulse width conversion of these pulse width conversion means can be monitored and detected.

With such a configuration, by constantly monitoring and storing the output signals of these pulse width conversion means, it is possible to detect the magnitude of noise that has occurred during the past operation, and obtain a clue to noise countermeasures. be able to. Further, the noise tolerance detecting means is a plurality of stages of pulse signal delay means for inputting a pulse width signal, a means for controlling the number of stages of this delay means, and a pulse signal delay means for delaying by the set value of the means for controlling the number of filter stages. It is possible to provide a selecting means for enabling / disabling the pulse width input signal, and a pulse number measuring means for starting with the pulse width input signal and stopping with the output signal of the selecting means.

With such a configuration, the disturbance component of the pulse included in the pulse width signal from the pulse width conversion means can be removed by the filter stage number control means of the delay means, and the magnitude of noise can be measured by the pulse number measurement means. it can. Further, it is possible to provide a notification means for notifying the outside when the time width in which the noise is generated exceeds a predetermined set value.

The notifying means includes a comparator,
An alarm setting means is provided, and the comparator compares the measured value of the pulse number measuring means of the noise withstanding amount detecting means with the time data preset by the alarm setting means, and compares the time data set by the alarm setting means. When the one is bigger, an alarm can be output. With this configuration, an alarm can be output when the measured value of the pulse number measuring means of the noise tolerance detecting means exceeds the time data preset by the alarm setting means.

In the noise tolerance detecting means, the pulse signal delay means is composed of a plurality of stages of shift registers,
The filter stage number control means has a register A for receiving data from the central processing unit, and a plurality of ANDs for taking the product of the output signal of each stage of the shift register and the data of the register A.
It can be configured by including an element (AND1 to m) and an AND element (ANDn) that takes the product of the outputs of the AND elements (AND1 to m) and outputs as the internal signal m.

The pulse number measuring means is a counter B.
And a first latch circuit for inputting a pulse width signal to start the counter B and a second latch circuit for inputting an internal signal m and stopping the counter B. Further, the mask control means for masking the system reset signal of the information processing / control device inputs the first to third JK flip-flops and the pulse width signal during the period in which the noise tolerance detection means detects noise. 1st latch circuit to set 1JK flip-flop and internal signal m
To reset the first JK flip-flop
The latch circuit and the output of the first JK flip-flop and the clock are logically ANDed to form a clock signal during the period in which the noise immunity detection means detects noise to form the second, third
Input to the reset of the JK flip-flop, input the system reset signal to the set of the second JK flip-flop,
A reset signal synchronization circuit is formed by inputting the output of the second JK flip-flop to the set of the third JK flip-flop, and the output of this reset signal synchronization circuit is used for information processing.
The controller can be reset.

With this configuration, the information processing / control device can be reset by the output of the reset signal synchronizing circuit.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an information processing / control apparatus and noise immunity detection means for enhancing noise immunity according to an embodiment of the present invention, and FIG. 2 is a detailed block diagram of the noise immunity detection means. 3 is a block diagram of an information processing / control apparatus having a reset signal synchronizing circuit according to another embodiment, and FIG. 4 is a timing operation diagram for explaining the present invention. (Embodiment 1) In FIGS. 1 and 5, the present invention relates to an information processing / control apparatus 1 having a measuring means 24 for measuring a pulse width signal 12a.
Noise detection means 2A that detects the noise component (12n) detected by this noise detection means 2A
4 = (21 to 23)) and set the number of filter steps of the noise immunity detection means 2B that detects the magnitude of the detected noise (3N) in the time width (B) and the digital filter (21 to 23) The setting means 22 can be provided and configured.

With such a configuration, the analog input signal Ai can be detected with the ADC conversion accuracy at a presumed noise environment level, and the magnitude of noise (3N) intruding from the wiring system can be detected as the pulse width. That is, the means 2A for detecting the magnitude of noise (3N) is, for example, a pulse width (PWM) conversion means 12 for converting the analog signal Ai into the pulse width signal 12a.
And the detection noise (jitter component) (12n) included in the output of this PWM conversion means 12 as a pulse disturbance, a pulse signal multi-stage delay means 21 in the illustrated example, and a setting for setting the number of filter stages of this delay means 21. Means 22, a selection means 23, a digital filter (42) consisting of, pulse number measuring means 24,
And a noise withstanding amount detecting means 2B.

With such a configuration, the magnitude of the noise (3N) is measured by the pulse number measuring means 24 at the first pulse change of the pulse width (PWM) converting means 12, for example, the change to the L level, and the filter is started. The pulse of the period set by the stage number control means 22 is invalidated by the selection means 23, and after this period elapses, noise is generated by stopping the measurement of the pulse number measurement means 24 by the change pulse to the L level from the selection means 23. The noise generation period (B) can be measured according to the size of (3N). (Embodiment 2) Further, in the information processing / control apparatus 1 having the measuring means 24 for measuring the pulse width signal 12a,
The noise detection means 2A that detects (3N) and the noise component (12n) detected by this noise detection means 2A
Noise tolerance detection means 2B that detects the magnitude of the detected noise (3N) in the time width (B) after filtering with ~ 23, and noise (3N)
And a notification means 2C for notifying the outside when the time width (B) in which the occurrence occurs exceeds a predetermined set value.

With this configuration, when the time width (B) in which the noise (3N) is generated exceeds the preset value, it is possible to notify the abnormality to the outside. As a result, for example,
It is possible to easily grasp the cause of the noise by holding the data of the noise occurrence time and the data of the magnitude of the generated noise (3N) and analyzing the data. (Third Embodiment) Further, in the information processing / control apparatus 1 having the measuring means 24 for measuring the pulse width signal 12a, noise is generated.
The noise detection means 2A that detects (3N) and the noise component (12n) detected by this noise detection means 2A
Filtered by ~ 23, the noise tolerance detection means 2B that detects the magnitude of the detected noise (3N) in the time width (B), and the period during which the noise tolerance detection means 2B detects noise (3N), The information processing / control apparatus 1 can be configured by including a mask control unit 2D that is shown as a system reset prohibition that masks the system reset signal 11a.

With this configuration, the system reset signal 11a of the information processing / control device 1 can be masked while the noise (3N) is being detected. As a result, even if an extremely large noise (3N) intrudes and the information processing / control device 1 enters an abnormal state, the system reset in this abnormal state is stopped, and the noise (3N) is removed to a stable state. By resetting the system and restarting when it becomes
It is possible to prevent the information processing / control apparatus 1 from being locked in in an abnormal state and to configure the information processing / control apparatus 1 having higher reliability and improved noise resistance.

[0029]

(Embodiment 1) Referring to FIG. 1, an information processing / control apparatus 1 according to the present invention includes an information processing / control unit 11 that operates as a main body of the information processing / control apparatus 1 and an analog signal.
The noise detection means 2A indicated by the PWM conversion means 12 for detecting the noise 3N from Ai, the noise tolerance detection means 2B, and the noise magnitude 24a detected by the noise tolerance detection means 2B are set to a predetermined set value 25a. Alarm setting means 25 for notifying the outside when exceeding and notification means 2C consisting of comparator 26,
The system reset inhibiting means 27 for masking the system reset signal 11a of the information processing / control apparatus 1 can be provided while the noise (3N) is being detected.

The noise detecting means 2A receives the analog input signal Ai from the outside and converts it into the pulse width signal 12a according to the magnitude of the analog input signal Ai, as described in the prior art of FIG. Pulse width (PWM) conversion means (4C), or pulse width conversion means 41 to 43 and this pulse width signal 43a
An analog / digital signal conversion circuit (ADC) 4 for converting an analog / digital signal by measuring the pulse width is provided, and the pulse disturbance 12n generated immediately after the pulse width conversion of these pulse width conversion means 41 to 43 is monitored and input. It is possible to detect the magnitude of noise (3N) superimposed on the signal Ai.

Now, assume that burst noise 3N is superimposed on the input signal line as noise (3N) in the common mode. This common mode noise is converted into normal mode noise on the one hand based on the imbalance of the input circuit including the input signal line stray capacitance and enters the above-mentioned pulse width conversion means (4C) or pulse width conversion means 41 to 43. To do. Also, common mode noise causes a current to flow to the ground via the capacitance component of the analog filter and the stray capacitance, and this ground current resonates due to the inductance of the signal 0V circuit and similarly generates a noise voltage in the 0V circuit.

These noise voltages are particularly affected by these noises before and after the output pulse 12a of the pulse width converting means 2A including the ADC 4 is switched, and pulse disturbance 12n is generated. This pulse turbulence 12n is typically a noise (3
Since it is related to the magnitude of N), the magnitude of the noise 3N can be estimated by collecting the data of the burst noise 3N level and the pulse disturbance 12n time (B) in advance.

With such a configuration, by constantly monitoring and storing the output signals 12a of the pulse width converting means 2A, it is possible to detect the magnitude of the noise (3N) generated during the past operation, and to prevent noise. You can get a clue to. In addition, the noise tolerance detection means 2B is a pulse width signal
Pulse signal delay means 21 for inputting 12a, filter stage number control means 22 of this delay means 21, and pulse signal delay means 21 by the set value 22a of this filter stage number control means
Pulse width input signals 21a, 22a ... 22m that are delayed by selecting means 23, and pulse number measuring means 24 that starts with the pulse width input signal 12a and stops with the output signal 23a of the selecting means 23. , And can be configured.

With this configuration, the pulse width signal from the pulse width conversion means 2A is controlled by the filter stage number control means 22 of the delay means.
The pulse turbulence component 12n included in 12a can be removed, and the magnitude of the noise 3N (time B) can be measured by the pulse number measuring means 24. Next, the noise tolerance detection means 2B according to the present invention
An example will be described. In FIG. 2, the pulse signal delay means (21) is composed of a plurality of stages of shift registers SR1, SR2, ... SRm, and the filter stage number control means (22) is a central processing unit.
The selection means 23 has a register A 46 for receiving data from the CPU, and the selection means 23 outputs the output signals sr1, sr2, ... srm of each stage of the shift registers SR1, SR2, ... SRm and the CPU from the CPU set in the register A. Multiple AND elements (AND1 to m) that multiply the data
And the output of this AND element (AND1 to m)
It can be configured by including an AND element (ANDn) that outputs as m.

Hereinafter, description will be made with reference to FIGS. 2, 4 and 5. In the logic operation, the L level is set to a significant level here, and the timing is such that the L level is output when the H level changes from the L level to the ANDn element and all inputs are at the L level. With such a configuration, the analog input signal Ai (3a) noise-filtered by the analog noise filter ANF 3 is, for example, described above with reference to (C) of FIG.
It is input to the ADC 4 (input switching unit 41, integrator 42, comparator 43) and converted into a pulse width signal 12a (= 43a). Then, in the pulse width signal 12a (= 43a), pulse disturbance 12n (= 43n) occurs when the noise environment is bad. This will be described below with reference to FIG. In FIG. 4, the horizontal axis is the time axis,
Clock CLK, output signal, input signal (no noise), input signal (with noise), internal signal (1 to m)
Is displayed.

In the case of the ADC shown in (C) and (D) of FIG. 5, the output signal means the timing of the start of analog / digital conversion by the command from the CPU 5 of FIG.
In the case of the ADC shown in (D), the timing t1 at which the counter 45 starts counting corresponds to this. Then, the counter 45 stops counting the input signal (noise-free) (timing t2, t3), and the CPU 5 reads the count value Tx (= Tx1, Tx2), whereby analog / digital conversion can be performed. .

In a place where the noise environment is bad, pulse disturbance 12n (= 43n) occurs in the pulse width signal 12a (= 43a). This pulse disturbance 12n is caused by shift registers SR1, SR2, ... SR
Output signals sr1, sr2 ,.
・ Srm is formed. On the other hand, the data DATA1 is given from the CPU 5 to the register A 46 as the filter stage number control means (22). Data DATA1 is used as this filter stage number control means (22).
Is, for example, r (r≤r
m), the H level is set to AND1 to r, and AND (r + 1) to
Set L level for m. By setting in this way, the outputs of these shift registers SR1, SR2, ..., SRm are logically ANDed by the corresponding AND elements, and the shift register SR
1, SR2, ... SRr output AND elements AND1 to ANDr output have pulse disturbance 12n, but shift register SR (r + 1) to
The outputs of AND elements AND (r + 1) to ANDm for SRm are set to the L level.

Next, the outputs of these AND elements AND1 to ANDm are
A logical product is obtained by the logical element shown by ANDn. Since this logic element considers the L level as a significant signal here,
When all inputs are at L level, L level is output. Therefore, a logical sum element specifically corresponds to a logical element that considers the H level as a significant signal. This logical element ANDn can be logically ANDed to form the signal 44a shown at the bottom of FIG. 4 as the internal signal m 1.

Therefore, returning to FIG. 2, the pulse width signal 43a of the double integrator circuits 41 to 43 is input to the start of the counter B 45 via the latch elements L3 and L4, and this internal signal m is input to the stop of the counter B 45. By inputting (44a), it is set by the filter stage number control means (22) from when the first pulse signal with an arrow in the input signal 12a (with noise) shown in FIG. 4 changes to the L level. If the pulse disturbance 12n is set within the elapsed time of the filter time B0 (1 clock time multiplied by r times), the counter A 45 outputs this set filter time, and the pulse disturbance 12n changes the filter time B0. If it exceeds, the duration B of the pulse disturbance 12n can be measured.

Therefore, this measured pulse disturbance 12n
The comparator 26 compares the duration B of the data with the DATA2 set by the CPU 5,
When the duration B is longer, the output signal OUT3 is output as "abnormal noise has entered", and information can be provided to the operator. As a result, the operator can take an appropriate measure, for example, temporarily increase the filter stage number of the filter stage number control means (22), and finally carry out noise investigation and improvement processing by the manufacturer.

That is, the means for notifying the outside when the time width B in which the noise 3N is generated exceeds the predetermined set value (B0) is input to the comparator 26 by the comparator 26 and DATA2 from the CPU 5. And an alarm setting means to be configured, and the pulse number measuring means 24,
Input counter B 45 and pulse width signal 43a
The first latch circuit L3 that starts B45 and the internal signal m (44
The second latch circuit L4 for inputting a) and stopping the counter B 45 can be configured.

With this configuration, the noise tolerance detecting means 2
The measured value B of the pulse number measuring means 24 of is the alarm setting means.
The alarm OUT3 can be output when the preset time B0 data in 25 is exceeded. (Embodiment 2) Further, in FIG. 1 and FIG. 3, during the period during which the noise tolerance detection means 2B detects the noise 3N,
The mask control means 2D for masking the system reset signal 11a of the control device 1 includes first to third JK flip-flops 48 to
50 and the pulse width signal 12a (= 43a) are input, the first latch circuit L5 that sets the first JK flip-flop 48, and the internal signal m (44a) are input, and the second JK flip-flop 48 is reset. The latch circuit L6, the output OUT2 of the first JK flip-flop 48, and the clock CLK are logically ANDed to form a clock signal for the period during which the noise tolerance detection means 2B detects the noise 3N to form the second and third JK flip-flops. 49,50
Input to the reset of the system reset signal 11a to the second
A reset signal synchronization circuit is formed by inputting to the set of JK flip-flops 49, and inputting the output 49a of the second JK flip-flop 49 to the set of third JK flip-flops 50, and outputting 50a ( = 27a), the information processing / control device 1 can be reset.

With this configuration, the information processing / control apparatus 1 can be reset by the output of the reset signal synchronization circuit 50a (= 27a).

[0044]

As described above, the size of noise is detected as a pulse width by using the information processing / control apparatus for enhancing noise resistance and the noise withstand amount detecting means according to the present invention, and (1) noise environment Noise tolerance detection means that can set the number of filter stages of the digital filter according to the level of noise, and (2) this noise tolerance detection means, the noise occurrence time width exceeds the preset value. The noise resistance is enhanced by providing means for notifying the outside to the outside and (3) means for masking the system reset signal from the information processing / control device during the period when the noise tolerance detection means detects noise. An information processing / control device and its noise immunity detection means can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing / control apparatus and noise immunity detection means for enhancing noise immunity according to an embodiment of the present invention.

FIG. 2 is a detailed block diagram of a noise tolerance detector.

FIG. 3 is a block diagram of an information processing / control device having a reset signal synchronization circuit according to another embodiment.

FIG. 4 is a timing operation diagram illustrating the present invention.

FIG. 5 is an explanatory diagram using a pulse width conversion means as an example of the influence of noise superimposed on an analog signal on a digital system.

[Explanation of symbols]

1 Information processing / control device 11 Information processing / control unit 11a, 27a System reset signal 12 Pulse width conversion means 12a, 43a pulse width signal 12n, 43n, 3N noise signal 2A noise detection means 2B noise tolerance detection means 2C notification means 2D mask control means 21 pulse signal multi-stage delay means 21a ~ 21m delayed signal 22 Filter stage control means 22a, 22a, 25a Set value 23 means of selection 23a, 44a Internal signal 24 pulse number measuring means 24a, B detection noise signal 25 Alarm setting means 26 Comparator 27 System reset inhibit circuit 3, ANF analog filter Ai, 3a analog signal Noise superimposed on 3N and 3n analog signals 43n Noise superimposed on digital signal 4,4C noise detection means ADC, 41-43 Analog / digital conversion means 44, DNF Digital Filter 45,51 counter 46 registers 48-50 flip-flops 5 CPU AND1 to ANDm, ANDn logic element SR1 to SRm shift register PWM pulse width modulation means L1 to L6 latch circuit

Claims (10)

[Claims] 1. An information processing / control apparatus having a measuring means for measuring a pulse width signal, wherein noise detecting means for detecting noise and noise detected by the noise detecting means are filtered by a digital filter. An information processing / control apparatus for enhancing noise resistance, comprising: a noise withstanding amount detecting means for detecting the size of the noise in a time width; and a controlling means for setting / controlling the number of filter stages of a digital filter. 2. An information processing / control apparatus having a measuring means for measuring a pulse width signal, wherein noise detecting means for detecting noise and noise detected by the noise component detected by the noise detecting means are filtered by a digital filter. A noise withstanding amount detecting means for detecting the magnitude of the noise in a time width, and a notifying means for notifying the outside when the time width in which the noise is generated exceeds a preset set value. An information processing and control device that improves noise resistance. 3. An information processing / control apparatus having a measuring means for measuring a pulse width signal, wherein noise detecting means for detecting noise and noise detected by the noise detecting means is filtered by a digital filter. A noise withstanding amount detecting means for detecting the magnitude of the time width and a mask controlling means for masking a system reset signal of the information processing / control device during a period in which the noise withstanding amount detecting means detects noise. An information processing / control device that improves noise resistance. 4. An information processing / control apparatus for enhancing noise resistance according to any one of claims 1 to 3, wherein the noise detection means receives an analog input signal from the outside and the analog input signal is received. A pulse width conversion means for converting into a pulse width signal according to the magnitude of the signal, or a pulse width conversion means and an analog / digital signal conversion circuit for converting the pulse width signal into an analog / digital signal (hereinafter referred to as ADC (Abbreviated as a conversion circuit), and monitors and detects the disturbance of the pulse generated immediately after the pulse width conversion of these pulse width conversion means, and enhances noise resistance. 5. The information processing / control apparatus for enhancing noise resistance according to any one of claims 1 to 3, wherein the noise resistance detection means has a plurality of stages of pulse signals for inputting pulse width signals. A delay unit, a filter stage number control unit of the delay unit, a selection unit for enabling / disabling the pulse width input signal delayed by the pulse signal delay unit according to a set value of the filter stage number control unit, and the pulse width An information processing / control apparatus for enhancing noise resistance, comprising: a pulse number measuring means that starts with an input signal and stops with an output signal of a selecting means. 6. The information processing / control apparatus for enhancing noise resistance according to claim 1 or 3, wherein the noise occurrence time width exceeds a predetermined set value. An information processing / control device for enhancing noise resistance, comprising a notification means for notifying the outside when. 7. The information processing / control apparatus for enhancing noise resistance according to claim 2 or 6, wherein the notifying means includes a comparator and an alarm setting means, and the pulse of the noise tolerance detecting means is provided. The measured value of the number measuring means, the time data preset by the alarm setting means,
Is compared with the comparator, and when the time data set by the alarm setting means is larger, an alarm is output. An information processing / control device for enhancing noise resistance. 8. The noise immunity detection means used in the information processing / control apparatus for enhancing noise immunity according to claim 5, wherein the pulse signal delay means is composed of a plurality of stages of shift registers, and the filter stage number control means is at the center. A plurality of AND elements (AND1 to m) having a register A for receiving data from the processing device and multiplying an output signal of each stage of the shift register by the data of the register A, and the AND element (AN
AND which outputs the product of the outputs of D1 to m) and outputs as the internal signal m
A noise immunity detection circuit comprising: an element (ANDn). 9. The noise immunity detection means used in the information processing / control apparatus for enhancing noise immunity according to claim 8, wherein the pulse number measurement means inputs a counter B and the pulse width signal, And a second latch circuit for inputting the internal signal m and stopping the counter B, the noise immunity detecting means. 10. The information processing / control device for enhancing noise resistance according to claim 3, wherein a system reset signal of the information processing / control device is masked during a period in which the noise withstand amount detecting means detects noise. The mask control means includes first to third JK flip-flops, a first latch circuit that inputs the pulse width signal and sets a first JK flip-flop, and the internal signal.
A second latch circuit that inputs m and resets the first JK flip-flop, and the output of this first JK flip-flop and the clock are logically ANDed to form a clock signal during the period when the noise tolerance detector detects noise. Reset signal synchronization by inputting the system reset signal to the second JK flip-flop set and inputting the output of the second JK flip-flop to the third JK flip-flop set. An information processing / control device that enhances noise resistance, characterized in that the information processing / control device is reset by the output of the reset signal synchronization circuit.