JPH07307728A - Clock output monitoring method and clock output monitoring circuit - Google Patents

Abstract

PURPOSE:To suppress the increase of a circuit scale in accordance with the increase of the number of signals and to shorten the detection time from the generation of an abnormality to the detection. CONSTITUTION:A clock pulse generation circuit 1 generates clock signals CLK 1 to CLK n and frame pulse signals FP 1 to FP n. A comparison circuit 2 compares the waveforms of the clock signals CLK 1 to CLK n and generates a comparison result signal ALM 1 from the difference. A comparison circuit 3 compares the waveforms of the frame pulse signals FP 1 to FP n, generates a comparison result signal ALM 2 from the difference and generates a reset signal RST from the frame pulse signals. A temporary holding circuit 4 holds the signals ALM 1 and ALM 2 when these signals are outputted and release the holding of the signals by the input of a signal RST.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to clock output monitoring for detecting abnormalities in clock signals and frame pulse signals used in transmission equipment and the like.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional clock output monitoring circuit for detecting an abnormality of a plurality of clock signals and frame pulse signals used in a transmission device or the like. Reference numeral 1 is a clock pulse generation circuit for generating a plurality of clock signals CLK1 to CLKn and frame pulse signals FP1 to FPn, 10 is a disconnection detection circuit for detecting output disconnection of a set of clock signals and frame pulse signals, and 11 is an OR circuit. Is. Next, the operation of such a clock output monitoring circuit will be described. The clock pulse generation circuit 1 sets a synchronized clock signal CLK1 and frame pulse signal FP1 as one set and generates a plurality of sets up to n sets of the clock signal CLKn and the frame pulse signal FPn. Disconnection detection circuit 10
Detects an output disconnection of such a set of clock signal and frame pulse signal.

FIG. 6 is a block diagram of the disconnection detection circuit 10,
FIG. 7 is a timing chart for explaining the operation of the disconnection detection circuit 10. Here, the clock signal CLK is used.
1. A set of the frame pulse signal FP1 will be described. In FIG. 6, 50 is a flip-flop circuit and 51 is a monostable multivibrator circuit. Frame pulse signal FP
1 is output from the clock pulse generation circuit 1 for each frame as shown in FIG. Then, the flip-flop circuit 50 holds the frame pulse signal FP1 at the rising edge of the clock signal CLK1. As a result, the output signal Q of the flip-flop circuit 50 becomes as shown in FIG.

Next, the monostable multivibrator circuit 51
Each time the "L" level signal Q is input, the alarm signal ALM4 is set to the "H" level for a certain time width. This time width is set to be longer than one frame period, and therefore the clock signal CLK1 and the frame pulse signal FP are set.
If 1 is normal, the alarm signal ALM4 is repeatedly set to "H" level by the signal Q before returning to "L" level, and this state is maintained.

When the output of the frame pulse signal FP1 is interrupted due to some abnormality as shown at point C in FIG. 7 (a), the "L" level signal Q is not output and the alarm signal ALM4 is output as described above. "L" after the passage of time
It becomes a level. In this way, the clock signal CLK1
Alternatively, the abnormality of the frame pulse signal FP1 is detected. Then, the logical sum circuit 11 takes the logical sum of the plurality of disconnection detection circuits 10 that perform such detection and outputs a final alarm signal, and monitors the clock signals CLK1 to CLKn and the frame pulse signals FP1 to FPn. Has been realized.

[0006]

In the conventional clock output monitoring circuit, the number of clock signals and frame pulse signals must be equal to the number of disconnection detection circuits. Therefore, as the number of signals increases, the scale of the clock output monitoring circuit increases. There was a problem that it became too large. Further, the above-mentioned time width is set to 2 frame periods or more in order to allow a margin for malfunction due to variations in the monostable multivibrator circuit in the disconnection detection circuit, and therefore an abnormality occurs in the clock signal or the frame pulse signal. There is a problem in that the detection time from when the alarm signal is output to the output of the alarm signal becomes long and the abnormality detection may be significantly delayed. In order to solve the above problems, it is an object of the present invention to provide a clock output monitoring circuit capable of reducing the detection time without increasing the circuit scale even if the number of signals increases.

[0007]

According to the present invention, a plurality of clock signal waveforms are compared, a first comparison result signal is generated from the difference, and a plurality of frame pulse signal waveforms are compared to determine the difference. A second comparison result signal is generated, and abnormality of the clock signal and the frame pulse signal is detected based on the first or second comparison result signal. Also, one of the plurality of clock signals is used as a basic clock signal, and this and all other clock signals are subjected to waveform comparison, and the difference is used as a first comparison result signal. A second comparison circuit, in which one of the frame pulse signals is used as a basic frame pulse signal, and this and all other frame pulse signals are subjected to waveform comparison, and the difference is used as a second comparison result signal; When the second comparison result signal is output, it is held for a predetermined time and is output as an alarm signal.

Further, the first comparison circuit has a plurality of exclusive OR circuits to which one of the basic clock signal and another clock signal is input, and a logical sum of outputs of the plurality of exclusive OR circuits. And a logical sum circuit that uses this result as a first comparison result signal. The second comparison circuit receives a plurality of exclusive logic signals to which one of the basic frame pulse signal and another frame pulse signal is input. A logical sum of the outputs of the summing circuit and the plurality of exclusive OR circuits is used as the second comparison result signal, and a logical product of the plurality of frame pulse signals is calculated, and the result is reset signal. And a temporary holding circuit for removing noise from the first and second comparison result signals, and the first and second noise removing circuits. Hold this when the signal is output It is composed of first and second holding circuits for releasing the holding by inputting a reset signal, and a logical sum circuit for taking the logical sum of the outputs of the first and second holding circuits and outputting the result as an alarm signal. It is a thing.

[0009]

According to the present invention, the abnormality of the clock signal and the frame pulse signal is detected by the result of the waveform comparison of the plurality of clock signals or the result of the waveform comparison of the plurality of frame pulse signals. The temporary holding circuit outputs the first comparison result signal, which is the result of waveform comparison of the plurality of clock signals, from the first comparison circuit, or outputs the first waveform comparison result of the plurality of frame pulse signals. When the second comparison result signal is output from the second comparison circuit, this is held for a predetermined time and output as an alarm signal.

The first comparison result signal is generated by the OR circuit from the outputs of the exclusive OR circuits in the first comparison circuit, which receives the clock signal, and the second comparison result signal is , A second comparison circuit that receives the frame pulse signal as an input, and is generated by the logical sum circuit from the outputs of the plurality of exclusive logical sum circuits. Then, the alarm signal is noise-removed from the first and second comparison result signals by the first and second noise removing circuits in the temporary holding circuit, and is held by the first and second holding circuits. It is generated by taking the logical sum by the circuit.

[0011]

1 is a block diagram of a clock output monitoring circuit showing an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of the clock output monitoring circuit, which is the same as FIG. Are given the same reference numerals. In FIG. 1, reference numeral 2 denotes the first comparison result signal ALM1 from the difference between the waveforms of the clock signals CLK1 to CLKn.
A first comparison circuit 3 for generating the frame pulse signal F
It is a second comparison circuit that compares the waveforms of P1 to FPn and generates a second comparison result signal ALM2 from the difference.

Reference numeral 4 is comparison result signals ALM1 and ALM.
When 2 is output, hold this and reset signal RS
This is a temporary holding circuit that releases this holding by inputting T. The clock pulse generation circuit 1 generates n sets of clock signals and frame pulse signals, but in FIG. 2, three sets, that is, clock signals CLK1 to CLK3 are generated.
And the frame pulse signals FP1 to FP3.

Next, the operation of such a clock output monitoring circuit will be described. The comparison circuit 2 compares the waveforms of the clock signals CLK1 to CLKn output from the clock pulse generation circuit 1 to detect abnormality of the clock signal. Figure 3
(A) is a block diagram showing one embodiment of the comparison circuit 2, 20 is an exclusive OR circuit, and 21 is an OR circuit.

Each of the exclusive OR circuits 20 uses the clock signal CLK1 as a basic clock signal, and performs an exclusive OR of the clock signal CLK1 and other clock signals CLK2 to CLKn. Then, the OR circuit 21 is connected to each exclusive OR circuit 2
The output of 0 is ORed and the result is output as the first comparison result signal ALM1.

When there is no difference between the clock signals CLK1 to CLK3 as shown in FIGS. 2A to 2C, the comparison result signal A
LM1 remains at the "L" level as shown in FIG. The output A that appears at the position where the comparison result signal ALM1 is at the "L" level is noise. This noise A is generated even though the clock signals CLK1 to CLKn generated by the clock pulse generation circuit 1 are originally the same.
It is caused by a slight difference between the components in the circuit and the state of the transmission line.

Further, when an output interruption occurs in the clock signal CLK3 as shown in a portion B of FIG. 2 (c), the clock signal C
A difference is generated between the LK1 and the LK1, and this difference becomes a signal at the “H” level and is output from the exclusive OR circuit 20, whereby the comparison result signal ALM1 becomes “H” as shown in FIG. "H" level. In this way, the abnormality of the clock signal is detected by detecting the difference between the plurality of clock signals CLK1 to CLKn.

Next, the comparison circuit 3 outputs the frame pulse signals FP1 to FP output from the clock pulse generation circuit 1.
The waveforms of n are compared to detect an abnormality of the frame pulse signal. FIG. 3B is a block diagram showing an embodiment of the comparison circuit 3, where 30 is an exclusive OR circuit, 31 is an OR circuit, and 32 is an AND circuit.

Each of the exclusive OR circuits 30 takes the frame pulse signal FP1 as a basic frame pulse signal, and performs an exclusive OR between the frame pulse signal FP1 and the other frame pulse signals FP2 to FPn. Then, the logical sum circuit 31 takes the logical sum of the outputs of the exclusive logical sum circuits 30 and outputs the result as the second comparison result signal ALM2. In this way, the abnormality detection similar to that of the comparison circuit 2 is also performed in the comparison circuit 3.

Further, the logical product circuit 32 generates the reset signal RST by taking the logical product of the frame pulse signals FP1 to FPn. In the present embodiment, the AND circuit 32 is used so that the reset signal RST can be generated even if any of the negative logic frame pulse signals FP1 to FPn is disconnected. However, the reset signal RST is temporarily held. It is for releasing the holding operation of the circuit 4 described later,
It may be generated from one of the normal frame pulse signals FP1 to FPn. Therefore, the reset signal RST can be generated by a configuration other than the logical product circuit.

Next, the comparison result signal AL thus obtained
The M1, ALM2 and reset signal RST are temporarily held by the holding circuit 4
Entered in. FIG. 4 is a block diagram showing an embodiment of the temporary holding circuit 4. Reference numeral 40 is a first noise removing circuit which is, for example, an integrating circuit for removing the above-mentioned noise A from the comparison result signal ALM1, and 41 is the same comparison. Result signal ALM2
It is a second noise removing circuit for removing the noise A from the.

Reference numeral 42 denotes a first holding circuit which is, for example, a flip-flop circuit which holds a signal output from the noise removing circuit 40 and releases the signal when the reset signal RST is input, and 43 similarly. Noise removal circuit 4
A second holding circuit for holding the output of 1 and a logical sum circuit 44.

The noise removing circuits 40 and 41 remove noise B, which is irrelevant to the abnormality of the clock signal and the frame pulse signal, from the comparison result signals ALM1 and ALM2. Next, the holding circuits 42 and 43 hold the outputs of the noise removal circuits 40 and 41 for a predetermined time when the outputs thereof become the “H” level. The predetermined time here is set to be the frame period in the longest case, and therefore the holding circuit 42,
Reference numeral 43 is adapted to release this holding by inputting the reset signal RST.

The OR circuit 44 is a holding circuit 42,
The output of 43 is ORed and the result is the alarm signal ALM
Output as 3. In this embodiment, the clock signal CLK
Since the output disconnection occurred in 3, the comparison result signal ALM
1 is output as shown in FIG. 2 (d), the alarm signal AL
M3 becomes "H" level as shown in FIG. 2 (i), and returns to "L" level with the input of the reset signal RST.

As described above, the clock signal CLK1
~ CLKn and the frame pulse signals FP1 to FPn can be monitored, and since the abnormality detection is performed by the waveform comparison, not only the output interruption of the clock signal and the frame pulse signal but also the waveform abnormality can be detected.

[0025]

According to the present invention, the abnormality of the clock signal and the frame pulse signal is detected by the result of the waveform comparison of a plurality of clock signals or the waveform comparison of a plurality of frame pulse signals. It is possible to significantly reduce the detection time from the occurrence of an abnormality to the detection, and it is possible to significantly reduce the variation in the detection time. Further, since the waveform comparison is performed, not only the output interruption of the clock signal or the frame pulse signal but also the waveform abnormality can be detected.

The first comparison circuit, the second comparison circuit,
Also, by configuring the clock output monitoring circuit from the temporary holding circuit, the detection time from the occurrence of an abnormality in the clock signal or frame pulse signal to the detection is very short, the variation in the detection time is also very small, and the signal It is possible to realize a clock output monitoring circuit in which the circuit scale does not become excessively large even if the number increases.

The first comparison circuit is composed of a plurality of exclusive OR circuits and an OR circuit, and the second comparison circuit is composed of a plurality of exclusive OR circuits, an OR circuit and an AND circuit. By configuring the temporary holding circuit from the first and second noise removing circuits, the first and second holding circuits, and the logical sum circuit, the detection time is very short and the variation in the detection time is very large. It is possible to realize a clock output monitoring circuit that is small and does not increase in circuit scale even if the number of signals increases, with a simple configuration.

[Brief description of drawings]

FIG. 1 is a block diagram of a clock output monitoring circuit showing an embodiment of the present invention.

FIG. 2 is a timing chart diagram for explaining the operation of the clock output monitoring circuit of FIG.

FIG. 3 is a block diagram showing an embodiment of first and second comparison circuits.

FIG. 4 is a block diagram showing an embodiment of a temporary holding circuit.

FIG. 5 is a block diagram of a conventional clock output monitoring circuit.

6 is a block diagram of the disconnection detection circuit of FIG.

FIG. 7 is a timing chart diagram for explaining the operation of the disconnection detection circuit of FIG.

[Explanation of symbols]

1 ... Clock pulse generating circuit, 2 ... First comparing circuit, 3
... second comparison circuit, 4 ... temporary holding circuit, 20,30 ... exclusive OR circuit, 21,31,44 ... OR circuit, 32
... AND circuit, 40, 41 ... Noise elimination circuit, 42, 43
... holding circuit.

Claims (3)

[Claims] 1. A clock output monitoring method for monitoring abnormality of a plurality of clock signals and a frame pulse signal output from a clock pulse generation circuit, wherein waveforms of a plurality of clock signals are compared, and a difference is obtained.
The comparison result signal is generated, the waveforms of a plurality of frame pulse signals are compared, a second comparison result signal is generated from the difference, and a clock signal and a frame pulse are generated based on the first or second comparison result signal. A clock output monitoring method characterized by detecting a signal abnormality. 2. A clock output monitoring circuit for monitoring abnormality of a plurality of clock signals and frame pulse signals output from a clock pulse generation circuit, wherein one of the plurality of clock signals is used as a basic clock signal and another A waveform is compared with all clock signals, and a first comparison circuit that uses the difference as a first comparison result signal, and one of a plurality of frame pulse signals as a basic frame pulse signal and this and all other A waveform comparison between the frame pulse signal and a second comparison result signal, the difference of which is used as a second comparison result signal; and when the first or second comparison result signal is output,
And a temporary holding circuit which holds this for a predetermined time and outputs it as an alarm signal. 3. The clock output monitoring circuit according to claim 2, wherein the first comparison circuit includes a plurality of exclusive OR circuits to which one of the basic clock signal and another clock signal is input, And a logical sum circuit that takes the logical sum of the outputs of a plurality of exclusive logical sum circuits and uses this result as a first comparison result signal, and the second comparison circuit is the basic frame pulse signal and another frame pulse signal. Of a plurality of exclusive OR circuits to which one of the two is input, and a logical sum circuit that takes the logical sum of the outputs of the plurality of exclusive OR circuits and uses the result as a second comparison result signal; The temporary holding circuit removes noise from the first and second comparison result signals, and a first and second noise removal circuit. The temporary holding circuit removes noise from the first and second comparison result signals. Circuit and this 1st, 1st When the signal is output from the second noise removing circuit, the first and second holding circuits that hold the signal and release the holding by inputting the reset signal, and outputs of the first and second holding circuits And a logical sum circuit that outputs the result as an alarm signal.