JP2003143489A - Video signal generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem in a conventional technique that the vicinity of a pixel composing section serving as an image pickup element must be formed with a circuit function composing section, this causes increases in an area of a device and in power consumption, and especially, the increase in the number of pixels makes it difficult to operate the device because a high speed is required. SOLUTION: A video image generator 10 consisting of a single CMOS structure has four pixel composing sections 110, 111, 112 and 113, a driving pulse control section 12, a shutter driving pulse control section 13 and an image data shaping section, all of which are incorporated in the device. Constituting the device with the CMOS structure on the same plane of a wafer enables to incorporate these components into the device 10 consisting of a single CMOS structure. This constitution can realize high performance such as small size, low power consumption and high speed without a peripheral circuit, and driving method can be facilitated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal generator, and more particularly to a video signal generator for generating a clear video signal by shutter control by using an image pickup device having a pixel number greater than that of an HDTV image. Regarding the device.

[0002]

2. Description of the Related Art FIG. 15 is a block diagram showing an example of a conventional video signal generator. This video signal generator includes a pixel configuration unit 1 in which a plurality of pixels are arranged in a two-dimensional matrix,
From the pixel configuration unit 1, a drive pulse control unit 2 that supplies a horizontal drive pulse and a vertical drive pulse to the pixel configuration unit 1, a shutter drive pulse control unit 3 that supplies a shutter drive pulse to the pixel configuration unit 1, The image data shaping unit 4 shapes the extracted image data.

Here, the pixel configuration unit 1 includes a charge transfer element (C
Since it is an image pickup device having a CD structure and the manufacturing process is complicated and there are many kinds, only simple various drive pulse trains can be incorporated in the pixel configuration unit 1. Therefore, as shown by hatching in FIG. 15, the circuit functional components such as the drive pulse control unit 2, the shutter drive pulse control unit 3, and the image data shaping unit 4 need to be provided separately from the pixel configuration unit 1. is there.

[0004]

Therefore, in the conventional video signal generator, the circuit functional components (drive pulse control unit 2, shutter drive pulse control unit 3) described above are provided around the pixel configuration unit 1 which is an image sensor. , The image data shaping section 4) must be formed, and the area of the device is increased and the power consumption is also increased. In particular, when the number of pixels is increased to obtain a high-quality image, the scale of the image is increased more and more, and in order to secure a moving image, operation is difficult because it is required to operate at high speed. There is.

By the way, in particular, it has not been conventionally considered to capture a moving image of sports, animals, etc., and obtain a high-resolution image similar to a photograph from this moving image. In order to obtain an image similar to that of a photograph, the number of pixels is insufficient for a high definition television signal (HDTV signal), and it is necessary to separately prepare equipment such as a photographer and a digital camera mainly for still images. Then, in order to obtain a still image as clear as a photograph, it is necessary to stop the optical image of the subject and then convert it into a video signal.

In order to print a high-resolution photo-like image, for example, the number of input pixels is A4 size (about 30).
cm × 20 cm) and the pixel density is 12 dots / mm when printing on a recording paper of 3600 dots × 2400
Dots are needed as an approximate number of pixels. But,
In TV images, the number of pixels is 640 x 480, and HD
Even TV images have only 1920 x 1080 pixels,
It is necessary to prepare an image input device having four times as many pixels (3840 × 2160) as an HDTV image.

However, there is no television camera for HDTV having four times the number of pixels, and there is a problem that a high resolution line scanner or a digital camera cannot handle a moving image with only a still image. In particular, it was possible to project a movie-like image with a movie film as a moving image on a large screen such as a movie theater, but with a device having an electronic image pickup unit such as a TV camera, the resolution is low and a photograph-like image is obtained. This is difficult to achieve, and this is a major issue.

Further, if the read time is increased as the number of pixels increases, the read time per screen increases, and flicker results in a difficult-to-see screen display.
It is necessary to speed up the reading time in units of pixels, but this is difficult to speed up the imaging unit, and is very difficult to realize.

When the irradiation amount of the subject light image is extremely small like a starry sky, a practical image cannot be obtained because the accumulation time cannot be increased beyond the vertical scanning period in order to obtain a continuous image.

The present invention has been made in view of the above points,
It is an object of the present invention to provide a video signal generation device in which a pixel configuration unit which is an image sensor and a circuit function configuration unit around the pixel configuration unit can be incorporated in the same CMOS structure.

Another object of the present invention is to divide an optically continuous high-resolution image and pick it up at the same time to speed up the reading speed and obtain a high resolution even in a moving image state while adjusting to the characteristics of the image pickup device. By storing the image captured in the divided mode for one screen and dividing the previously stored image into signals along the standard HDTV signal and outputting the signals, the shutter depending on the irradiation amount of the light image of the subject is provided. An object of the present invention is to provide a video signal generator that obtains a high resolution image including operations.

Another object of the present invention is to provide a video signal generator using a CMOS image pickup device which has a simple pixel structure and which can obtain a clear still image of high quality even in a moving image.

Still another object of the present invention is to provide a video signal generator capable of generating a video signal of a continuous intermittent image even if the movement of the subject light image is fast.

[0014]

In order to achieve the above object, a first aspect of the present invention comprises a pixel configuration section for capturing a subject light image with a photodiode and converting it into image data which is an electric signal, and a pixel configuration section. An image data shaping unit that performs noise removal and signal level adjustment shaping processing on the output image data and outputs it as a video signal to the outside, and reset pulse and transfer based on the horizontal synchronization signal, vertical synchronization signal and reset signal. A drive pulse control unit that generates a pulse and a row selection pulse and supplies the pulse to the pixel configuration unit, and a shutter drive pulse control unit that generates a shutter signal based on the shutter control signal data and supplies the shutter signal to the pixel configuration unit The structure is formed as a CMOS structure on the same plane.

In the present invention, since the pixel configuration section, the image data shaping section, the drive pulse control section, and the shutter drive pulse control section are each configured with a CMOS structure, they are all formed on the same plane of the wafer as a CMOS structure. be able to.

In order to achieve the above object, a second aspect of the present invention is the pixel configuration section of the first aspect of the present invention, wherein M times the number of horizontal pixels of a standard high definition television image (M is 2). The number of pixels is N.times.the number of pixels in the vertical direction (N is an integer of 2 or more) and is divided by M.N in the horizontal direction. , MN divided pixel constituent units output a total of MN image data in parallel, and the image data shaping unit outputs MN divided pixel constituent units in parallel. Noise removal and signal level adjustment shaping processing is applied to each image data separately, and M
In this configuration, N video signals are output to the outside in parallel. In this invention, a standard high definition television (HD
It is possible to obtain a high-resolution video signal having the number of pixels which is M · N times the number of pixels of a (TV) image.

In order to achieve the above-mentioned object, a third aspect of the present invention is to provide each pixel constituting the pixel constituting section of the first aspect of the invention with
A photodiode that illuminates the subject light image and accumulates charges according to the amount of incident light; a transfer transistor that transfers the charges accumulated in the photodiode; and a photodiode charge that is transferred via the transfer transistor. Storage unit, an amplification transistor that amplifies the charge accumulated in the storage unit, a row selection transistor that outputs the charge amplified by the amplification transistor when turned on by a row selection pulse, and the storage unit is reset And a shutter signal transistor that resets the accumulated charge of the photodiode by a shutter signal, and the shutter drive pulse control unit includes a shutter signal transistor for all pixels within the blanking period of the vertical synchronization signal. Is turned on and the accumulated charges of the photodiodes of all pixels are simultaneously After setting to zero, a shutter signal that simultaneously turns off the shutter signal transistors of all pixels is periodically generated, and the drive pulse control unit sets the reset pulse that turns on the reset transistor while the shutter signal transistor is off. The shutter signal transistor is turned on immediately before the shutter signal transistor is turned on and the transfer pulse is turned off immediately before the vertical synchronization signal blanking period. The charge stored in the photodiode during the off period is transferred to the storage section via the transfer transistor that is turned on, and then determined at the readout position of each pixel in the video period outside the blanking period of the vertical synchronization signal. A row selection pulse that sequentially turns on the row selection transistors is output at the specified read timing. It is obtained by a configuration in which.

According to the present invention, the electric charge accumulated in the photodiode within the blanking period of the vertical synchronizing signal can be transferred to the accumulating portion via the transfer transistor which is turned on. Charges can be transferred without affecting row selection.

Further, in order to achieve the above object, a fourth invention is such that the shutter drive pulse control unit turns off the shutter signal transistor within one vertical synchronizing signal period or within a plurality of vertical synchronizing signal periods. It is characterized by being configured to generate a shutter signal. According to the present invention, when the shutter signal transistor is turned off within one vertical synchronizing signal period, a high-speed moving image can be captured as a still image, and the shutter signal transistor can be turned on within a plurality of vertical synchronizing signal periods. When turned off, long exposure is possible.

In order to achieve the above-mentioned object, a fifth aspect of the invention is to provide a plurality of pixel circuits forming an image pickup section and a drive pulse generating means for supplying various drive pulses to the plurality of pixel circuits. In a video signal generator that converts a light image into a video signal that is an electrical signal and outputs the video signal, each of the plurality of pixel circuits includes a photodiode that illuminates a subject light image and accumulates electric charge according to the amount of incident light. A transfer transistor that transfers the charge stored in the diode, a storage unit that stores the charge of the photodiode transferred through the transfer transistor, an amplification transistor that amplifies the charge stored in the storage unit, and an amplification unit. Row select transistor that turns on the charge amplified by the row select transistor by the row select pulse and resets the storage unit And a drive pulse generating means for turning on the reset transistor for a first predetermined period to generate a reset pulse for resetting the storage unit, and thereafter for turning on the transfer transistor for a second predetermined period to turn on the photo transistor. The transfer pulse that transfers the charge stored in the diode to the storage unit is generated simultaneously for all pixel circuits, and then the row selection is performed at the read timing determined by the read position of each pixel in the video period. It is configured to generate a row selection pulse that sequentially turns on the use transistors.

In the present invention, the method of applying the drive pulse is devised to eliminate the need for the shutter signal transistor for resetting the charge of the photodiode, so that the number of transistors around the photodiode can be reduced as compared with the conventional case. . Further, even if the subject light image is a moving image, a still image can be obtained by transferring the charges accumulated in the photodiode to the accumulation unit.

In order to achieve the above-mentioned object, a sixth aspect of the present invention provides a plurality of pixel circuits forming an image pickup section and a drive pulse generating means for supplying various drive pulses to the plurality of pixel circuits. In a video signal generator that converts a light image into a video signal that is an electrical signal and outputs the video signal, each of the plurality of pixel circuits includes a photodiode that illuminates a subject light image and accumulates electric charge according to the amount of incident light. A transfer transistor that transfers the charge stored in the diode, a storage unit that stores the charge of the photodiode transferred through the transfer transistor, an amplification transistor that amplifies the charge stored in the storage unit, and an amplification unit. Row select transistor that turns on the charge amplified by the row select transistor by the row select pulse and resets the storage unit And a drive pulse generating means for turning on the reset transistor and the transfer transistor at the same time for a first predetermined period to generate a reset pulse and a transfer pulse for resetting the storage section and the photodiode, and then the transfer transistor. Only second
Is turned on for a predetermined period of time to generate a transfer pulse that transfers the charge accumulated in the photodiode to the storage section at the same time for all pixel circuits, and then at the read position of each pixel in the video period. The configuration is such that a row selection pulse for sequentially turning on the row selection transistors is generated at a predetermined read timing.

According to the present invention, the reset transistor and the transfer transistor are simultaneously turned on for the first predetermined period to generate a reset pulse and a transfer pulse for resetting the storage section and the photodiode, and then only the transfer transistor is turned to the second. Since the transfer pulse for transferring the electric charge accumulated in the photodiode to the accumulating portion is generated by turning on for a predetermined period of time, a fast shutter operation can be performed.

In order to achieve the above-mentioned object, a seventh invention is the drive pulse generating means of the fifth or sixth invention,
The reset pulse alone or the reset pulse and the transfer pulse are generated with a certain period from the beginning in the blanking period of the vertical synchronization signal as the first predetermined period, and the vertical synchronization signal is generated from the predetermined time point immediately after the first predetermined period has elapsed. The transfer pulse is generated with the period until immediately before the end of the blanking period as the second predetermined period, and the row selection pulse is sequentially generated in the video period outside the blanking period of the vertical synchronization signal. .

According to the present invention, the charge accumulated in the photodiode within the blanking period of the vertical synchronizing signal can be transferred to the accumulating portion via the transfer transistor which is turned on. Charges can be transferred without affecting row selection.

In order to achieve the above-mentioned object, the eighth invention further comprises a mechanical shutter mechanism for intermittently irradiating the photodiode with a subject light image on the incident light side of the photodiode of all pixel circuits, The drive pulse generating means generates a reset pulse and a transfer pulse so that the mechanical shutter mechanism intermittently transfers charges according to the amount of light of the subject light image accumulated in the photodiode to the accumulating unit and accumulates the charges. And

In the present invention, the mechanical shutter mechanism allows the photodiode to intermittently accumulate the electric charge of the subject light image, so that a continuous intermittent image signal is generated even if the subject light image operates quickly. be able to.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a block diagram of an embodiment of a video signal generator according to the present invention. In the figure,
In the video signal generator 10 having one CMOS structure, four pixel components 110, 111, 112 and 11 are provided.
3, a drive pulse control unit 12, a shutter drive pulse control unit 13, and an image data shaping unit 14 are incorporated. As described above, the drive pulse control unit 12, the shutter drive pulse control unit 13, and the image data shaping unit 14 can be incorporated together with the pixel configuration units 110, 111, 112, and 113 in the video signal generator 10 having one CMOS structure. This is because, as will be described later, these are configured with a CMOS structure on the same plane of the wafer.

The video signal generating device 10 includes an HDTV
Horizontal sync signal HD and vertical sync signal V synchronized with standard signals
D, clock (Clock), shutter control signal data Sdata, shutter drive timing signal Sres
et is input. The drive pulse control unit 12 generates a vertical drive pulse 15 and a horizontal drive pulse 16 that are synchronized with the input horizontal synchronization signal HD, vertical synchronization signal VD, and a clock and supplies them to the pixel configuration units 110 to 113. The shutter drive pulse control unit 13 has a shutter control signal data Sdata and a shutter drive timing signal Sres.
The shutter drive pulse 17 is generated based on et and is supplied to the pixel configuration units 110 to 113.

Further, the image data shaping section 14 shapes the pixel data output from the pixel construction sections 110 to 113 to subject light image data Dout0, Dout1, D.
Output as out2 and Dout3 in parallel. Further, the video signal generator 10 outputs a read signal Pt for the shutter period. As will be described later, the pixel configuration units 110 to 113 have a total pixel number that is four times the pixel number of the HDTV, and have a pixel configuration that is horizontally divided into four.

Next, the configuration and operation of each pixel constituting the pixel configuration sections 110 to 113 will be described. FIG. 2 shows a circuit diagram of an example of a pixel circuit for one pixel of the pixel configuration section in FIG. This pixel circuit has a plurality of pixel circuits in the horizontal direction and N pixels in the vertical direction.
Pixels (when the number of lines is N lines) are arranged in a matrix to form the pixel components 110 to 113, and each of the MOS field effect transistors Tr3 in the plurality of pixel circuits for one line in the same row is formed. The gates are switching-controlled simultaneously by the same row selection signal Th.

In FIG. 2, first, a shutter signal Ts is applied to the gate of the MOS field effect transistor Tr1.
By turning off the transistor Tr1 for a predetermined shutter-on time, an image of the object image is formed on the photodiode PD whose cathode is connected to the source of the transistor Tr1, and charges corresponding to the amount of light of the subject light image are accumulated. To do.
That is, although the charge amount of the PD changes according to the light amount of the subject light image incident on the photodiode PD, the voltage across the PD changes due to the charge according to the subject light amount while the transistor Tr1 is off.

Next, a charge transfer pulse Tt is applied to the gate of the MOS field effect transistor Tr4 for charge transfer, which is connected between the cathode of the photodiode PD and the non-grounded side terminal of the capacitor C constituting the storage section. Then, the transistor Tr4 is turned on, and the transistor Tr5 is turned on by the reset pulse Tr applied to the gate of the MOS field effect transistor Tr5 whose source is connected to the non-grounded side terminal of the capacitor C in advance to zero the charge. The electric charge of PD is transferred to the placed capacitor C through the drain and source of the transistor Tr4. After the charge transfer, the transistor Tr4 is turned off.

The voltage generated at both ends of the capacitor C according to the electric charge accumulated in the capacitor C is amplified by the MOS field effect transistor Tr2 for amplification, and is amplified from the source of the transistor Tr2 to the drain of the MOS field effect transistor Tr3. Supplied. A row selection pulse Th is supplied to the gate of the transistor Tr3 to turn on the transistor Tr3 for one line period, and the signal amplified by the transistor Tr2 is output as a video signal via the drain and source of the transistor Tr3. It
After the row selection is completed, the transistor Tr1 is turned off by the shutter signal Ts applied to the gate of the transistor Tr1 while the transistor Tr4 is off, and the next subject light image is stored in the photodiode PD. The same operation is repeated thereafter.

By using the same shutter signal Ts for all pixels, the electric charge of the subject light image is accumulated in each photodiode PD in all pixel circuits at the same time.
Then, the charges transferred to the capacitor C are simultaneously turned on by the row selection pulse Th to turn on the plurality of row selection transistors Tr3 on the same line, and sequentially turn on the plurality of row selection transistors Tr3 on different lines. Output a signal.

For example, the vertical synchronization period V shown in FIG.
At D, during the high level period Son of the shutter signal Ts shown in FIG. 7B, the transistor Tr1 of FIG. 2 is turned off and the subject light image is accumulated in the PD. If the subject light amount is small, the Tr1 off period (shutter on period) is increased as shown by Son 'in FIG. 3 (B), and if the subject light amount is large, the shutter on period is shown by Son "in FIG. 3 (B). Reduce.

Next, while the transistor Tr1 is off, the transistor Tr4 of FIG. 2 is turned on by the transfer pulse Tt shown in FIG. 3 (C) to transfer the electric charge generated in the PD to the capacitor C. If the transfer pulse Tt is turned on within the blanking period of the vertical synchronizing signal, the row selection performed during the video period is not affected. When the shutter signal Ts is used within the VD period, the video signals are continuously selected in rows, so that FIG.
As shown in (D), the readout signal Pt during the shutter period
Is always turned on.

Next, the case where the shutter operation is performed for a period longer than the vertical synchronization period VD will be described with reference to the timing chart of FIG. In the vertical synchronization period VD shown in FIG. 4A, the shutter signal Ts shown in FIG.
During the period S, which is the D period, the level is kept high and the period S
While it is on, the transistor Tr1 of FIG. 2 is turned off, and the light image of the subject is applied to the photodiode PD to accumulate electric charges. The shutter-on period (T
The off period of r1) is set longer than Son as shown by Son 'in FIG. 4B, and if the subject light amount is large,
The shutter on period (off period of Tr1) is shortened as indicated by "Son".

Next, while the transistor Tr1 is off, the transfer pulse Tt is set to a high level as shown in FIG. 4C, the transistor Tr4 in FIG. 2 is turned on, and the charge accumulated in the photodiode PD is stored in the capacitor C. Forward. The transfer pulse Tt turns on the transfer transistor Tr4 within the blanking period of the vertical synchronizing signal, thereby eliminating the influence on the row selection performed during the video period. In this case, the repetition period P of the transfer pulse Tt becomes the interval of the shutter signal Ts. Further, as shown in FIG. 4D, the read signal Pt in the shutter period is turned on only in the video period Tr immediately after the transistor Tr4 is turned on by the transfer pulse Tt.

4E to 4H are timing charts when the shutter signal interval is P ', which is shorter than the shutter signal interval P, and FIG. 4E shows the vertical synchronizing signal and FIG. (F) shows the shutter signal Ts, (G) shows the transfer pulse Tt, and (H) shows the read signal Pt during the shutter period.

Next, the structure of an image pickup apparatus including the video signal generator of the present invention and the operation of the image pickup apparatus will be described. FIG. 5 shows a block diagram of an example of a camera system including a video signal generator according to the present invention. In the figure, the image pickup unit 22 has an A / D conversion unit 23 built therein, and constitutes one embodiment of the video signal generator of the present invention shown in FIG. Imaging unit 22 incorporating this A / D conversion unit 23
Is four times the number of pixels 1920 in the horizontal direction and 1080 (1080 × 1080) in the vertical direction of a high-definition television (HDTV) system imaging device.
3840 horizontal pixels, 2160 vertical pixels
It has a solid-state image sensor (that is, 3840 × 2160). The circuit configuration of each pixel is similar to that of the pixel circuit of FIG.

In addition to this number of pixels, some pixels may be provided for the black level reference portion in order to secure optical black, for example. Also, for color images,
Although it has a total of three imaging units for each of the three primary colors,
Here, only one will be described as a representative.

The image pickup unit 22 is composed of four times as many pixels as the HDTV image as described above. The number of pixels is divided into four in the horizontal direction, and four pixels 110 to 113 shown in FIG. It is configured to have a component. That is, four pixel constituent parts 110 to 1 each having 960 (= 3840/4) pixels in the horizontal direction and 2160 pixels in the vertical direction.
13 are arranged in the horizontal direction. This is HDTV
It is necessary to increase the speed in order to output an image signal having four times as many pixels as the image, but it is difficult to increase the speed and it is easy to correct the boundary portion.

The subject light image is formed on the image pickup section 22 via the lens 21 of FIG. 5, and photoelectrically converted by the pixel construction sections 110 to 113 shown in FIG.
It is converted into a divided analog electric signal, taken out in parallel, and supplied to the image data shaping unit 14 in FIG. Here, the analog electric signals imaged by the four pixel configuration units 110 to 113 are the same as the four pixel configuration units 11 on the same line.
It is obtained in time series from 0 to 113.

The above-mentioned image data shaping section 14 has the structure shown in the block diagram of FIG.
The black level fixing circuit 31 detects the black level of the analog 4 parallel signals extracted from 10 to 113 and fixes them to a fixed potential, and then the gain / offset adjusting circuit 32 fixes the analog 4 parallel signals. It is supplied to the A / D converter 33 so that the gain and offset are the same. The A / D converter 33 corresponds to the A / D converter 23 shown in FIG. 5, and after the input analog 4-parallel signal is converted into a digital signal, the output signal shaping circuit 34 removes noise and the like. Then, it is shaped and output as a digital 4-parallel signal.

Referring back to FIG. 5 again, the image pickup section 22 will be described.
Digital 4 output from the image data shaping unit 14 in
The parallel signal is a horizontal division image signal obtained by dividing the screen into four in the horizontal direction, which is schematically shown by H1 to H4 in FIG. 5, and is supplied to the signal processing unit 24 to have a predetermined gamma, gain, offset, frequency band, or the like. The signal is processed and then supplied to the horizontal / standard conversion unit 25.

Here, a digital signal (video signal) which is input to the horizontal / standard conversion unit 25 and which is divided into four in the horizontal direction.
As shown in FIG. 7A, each of the
A video signal of 0 pixels and 2160 lines in the vertical direction, which is generated based on, for example, an HDTV system (high-definition system) synchronization signal (horizontal scanning frequency 33.75 kHz, vertical scanning frequency 30 Hz, clock frequency 74.25 MHz), with a frequency of 67.5 kHz It is a signal obtained based on a horizontal drive signal HD, a vertical drive signal VD having a frequency of 30 Hz, and a clock having a frequency of 74.25 MHz. That is, since an image with less flicker must be 30 Hz in the vertical direction, the driving frequency in the horizontal direction is 67.5 kHz (= 33.75 kHz × 2).

On the other hand, the standard system 4-division video signals V1 to V4 output from the horizontal / standard conversion unit 25 are divided into two in the horizontal direction and two in the vertical direction, that is, a total of four divisions. As shown in FIG. 7B, each of the generated video signals is 1920 pixels in the horizontal direction (= 960 pixels ×
2), 1080 lines in the vertical direction (= 2160 lines /
2), for example, a horizontal drive signal H with a frequency of 33.75 kHz
It is a video signal conforming to the HDTV standard, which is obtained based on a vertical drive signal VD having a frequency of 30 Hz and a clock having a frequency of 74.25 MHz.

The horizontal / standard conversion unit 25 has two memories (one memory is # 1 and the other is memory # 2).
7C includes a memory control circuit and the like.
(D) and, as schematically shown in FIG.
1 stores all the first four-divided video signals H1 to H4 in the horizontal direction for one screen in a 1VD period as they are and stores the next 1
The first 4-division video signal H1 written immediately before in the VD period
To H4 are output as second four-divided video signals V1 to V4, which are obtained by dividing each of the two in the horizontal and vertical directions.

On the other hand, in the memory # 2, when the operation read by the memory # 1 is being performed, the first 4-divided video signals H1 to H4 in the 1VD period following the 1VD period read by the memory # 1. All are stored as they are, and in the next 1VD period (that is, when the memory # 1 is writing 1
The first 4-division video signal H written immediately before (in the VD period)
1st-H4 divided into two in the horizontal and vertical directions respectively
4 divided video signals V1 to V4. here,
Each of the second 4-divided video signals V1 to V4 is shown in FIG.
As shown in (B), the video signal conforms to the HDTV standard, which is a standard method.

In this way, in the horizontal / standard conversion unit 25, the memory # 1 and the memory # 2 are alternately written every 1 VD period for writing the first 4-divided video signals H1 to H4 and the second.
The four 4-divided video signals V1 to V4 are read out, and when one memory is performing a write operation, the other memory is performed a read operation. V4 can always be output in parallel. Therefore, memory # 1 and memory #
As for 2, either one is always writing,
In this case, the read signal Pt during the shutter period is always on (predetermined logical value).

In FIG. 5, H, which is the second 4-division video signal output from the horizontal / standard conversion unit 25 in bit parallel.
The DTV standard signals V1, V2, V3 and V4 are converted by the parallel / serial conversion unit 26 into bit serial signals according to a predetermined standard, and then supplied to the transmission unit 27. On the other hand, 4
The four sets of audio signals from the microphone 28 of the book are A / D
After being converted into a digital signal by the conversion unit 29, the signal processing unit 30 performs processing such as volume and sound quality and supplies the processed signal to the transmission unit 27. In the transmission section 27, four sets of digital audio signals M1, M2, M3 and M4 from the signal processing section 30 are added to the bit serial HDTV standard signals V1, V2, V3 and V4.
Are multiplexed and output to a predetermined transmission path.

By the way, the above is the operation when the ON period of the shutter of each pixel of the image pickup unit 22 is within the 1VD period, but it is also possible to use it for a long exposure in which the ON period of the shutter is longer than the 1VD period. . FIG. 9 shows two memories # 1 and # 2 of the horizontal / standard conversion unit 25 during long-time exposure.
The usage state of is schematically shown.

In FIG. 9, first, a four-divided image 1 which is horizontally divided into four is written in the memory # 1 (image 1
Write), and then read this as a four-division image conforming to the HDTV standard, which is divided into two in the horizontal direction and in the vertical direction (Image 1 Read). The horizontal four-divided image 2 in the next 1VD period is not immediately written in the memory # 2, and the subject optical image is left to be radiated to the imaging unit 22 for a predetermined time.
During this period, the image 1 is continuously read from the memory # 1 (in the example of FIG. 9, the HDTV standard 4-division image 1 is continuously read during the 3VD period). Next, the horizontal four-divided image 2 obtained by the long-time exposure is written in the memory # 2 (image 2 Write). Next, the image 2 written in the memory # 2 is divided into two in the horizontal and vertical directions.
The image is converted into a TV standard 4-division image and continuously read for a plurality of VD periods (Image 2 Read).

In this way, long-time exposure is performed, and a very dark subject light image is sufficiently accumulated and output as a visible image. In this way, the imaging unit 22 is exposed for a long time and the reading unit repeatedly reads the same memory, so that a stable and clear image can be obtained. It is especially suitable for observing a subject light image with a small amount of light such as the starry sky and changing slowly.

In the embodiment described above, the pixel circuit is a CMOS-structured pixel circuit having a simple manufacturing method shown in FIG. 2, so that the shutter ON period of each pixel is within 1 VD period. That is, the peripheral drive pulse control unit 12, the shutter drive pulse control unit 13, and the image data shaping unit are provided with an imaging unit (pixel configuration unit) that can be used in long-time exposure in which the shutter ON period is longer than 1 VD period. CMOS on the same wafer with 14 on the same plane
The video signal generator 10 incorporated in the structure can be realized.

Therefore, according to the present embodiment, it is possible to obtain a video signal generator having high performance such as small size, low power consumption and high speed, which requires no peripheral circuit and can be easily driven. In particular, by outputting the read signal Pt for the shutter period, memory control becomes easier, and short-time exposure and long-time exposure can be facilitated.

Next, a second embodiment of the present invention will be described. In the above embodiment, the pixel circuit is configured as shown in FIG. 2 and the shutters are set at the same time for all pixels. With this configuration, for example, charges due to the subject light image in the vertical synchronizing signal period can be accumulated in the photodiodes PD of all pixels at the same time for a predetermined period, and the accumulated charges are stored in the capacitor C in the blanking period of the vertical synchronizing signal. By transferring, it can be taken out as a video signal during the video period of the next vertical synchronizing signal.

However, in this structure, the number of transistors is 5, and a large number of driving pulses are required in the pixel structure, which is complicated. From the viewpoint of performance, it is desirable that the periphery of the photodiode PD, which makes the subject light image an electric charge, have a structure as simple as possible so that noise is not easily mixed in and electric charge is hardly discharged. Is disposed around the photodiode PD, which causes a problem of performance deterioration. In particular, when the area of the imaging unit is reduced or the number of pixels is increased to achieve high resolution, the wiring portion becomes complicated, and the area of the pixel portion is small, which may hinder performance improvement.

Therefore, in the second embodiment of the present invention,
In order to solve the above problems, a pixel circuit has a circuit diagram configuration shown in FIG. In the figure, the same components as those in FIG. 2 are designated by the same reference numerals. That is, the pixel circuit of the present embodiment has a configuration in which the transistor Tr1 to which the shutter signal Ts is applied to the gate is deleted from the pixel circuit of the first embodiment shown in FIG. Therefore, when the pixel circuit of this embodiment is used, the shutter drive pulse control unit 13 of FIG. 1 is unnecessary.

Next, the operation of this pixel circuit will be described with reference to FIG.
The timing chart of No. 1 will be described. Note that FIG.
(A1) to (A4) show signal waveform diagrams on the same time axis, and FIGS. 11 (B1) to (B4) show the same time axis and
The signal waveform diagram of a time axis different from the same figure (A1)-(A4) is shown. First, the operation when the light amount of the subject light image is small will be described with reference to FIGS. 11 (A1) to 11 (A4). As shown in FIG. 11 (A2), the reset pulse Tr has a blanking period (V. V.) of the vertical synchronizing signal (VD) shown in FIG. 11 (A1).
A high level is set at the beginning of (Blanking), and the transistor Tr5 in FIG. 10 is turned on. As a result, a predetermined voltage is applied to the capacitor C via the drain and source of the transistor Tr5, and the capacitor C is reset to the predetermined potential.

After that, the reset pulse Tr becomes low level as shown in FIG. 11 (A2) within the blanking period of the vertical synchronizing signal (VD), and immediately after the transistor Tr5 is turned off, the gate of the transistor Tr4 is turned on. The transfer pulse Tt applied to the transistor Tr4 becomes high level as shown in FIG. 11A3, the transistor Tr4 is turned on, and the charge due to the subject light image accumulated in the photodiode PD is thereby changed to the drain and source of the transistor Tr4. Are all transferred to the capacitor C via. Therefore, the charge of the photodiode PD becomes zero at the end of this charge transfer.

The charge transfer is completed immediately before the blanking period of the vertical synchronizing signal (VD) is completed, and the transfer pulse Tt is set to the low level to turn off the transistor Tr4. By performing the operation up to this point on all pixels at the same time, the electronic shutter operation is performed in which the subject light image is charged for the same time. Next, the row selection pulse Th is set to the high level at the read timing determined by the position of each pixel in the video period outside the blanking period of the vertical synchronization signal, and the transistor Tr3 in FIG.
Is turned on, and the terminal voltage of the capacitor C amplified by the amplifying transistor Tr2 is output as a video signal via the transistor Tr3.

By operating with such a pixel circuit configuration, it is possible to perform the electronic shutter operation for the same time with a smaller number of transistors and pulse trains as compared with the pixel circuit of FIG. The shutter-on period of this pixel circuit is a video period outside the blanking period of the vertical synchronizing signal, as shown in FIG. In addition, in the pixel circuit shown in FIG. 10, the periphery of the photodiode PD can be made into a simple structure,
Since it is possible to reduce the factor that hinders the charge formed from the subject light image, it is possible to obtain a charge amount with a good S / N.

When the light quantity of the subject light image is small as described above, it is necessary to use the light quantity of the entire period of the vertical synchronizing signal by using the pulse trains shown in (A2) and (A3) of FIG. When it is desired to perform a fast electronic shutter operation with a large amount of light, the pulse trains of FIGS. 11B2 and 11B3 are used.

That is, when the light amount of the subject light image is large, the reset pulse Tr shown in FIG. 11 (B2) and the transfer pulse Tt shown in FIG. 11 (B3) are combined with the vertical synchronization signal shown in FIG. 11 (B1). From the beginning of the blanking period of the above, the transistors Tr5 and Tr of FIG.
Turn on 4 respectively. As a result, the capacitor C and the photodiode PD are reset at the same time. Immediately after completion of the reset, the reset pulse Tr and the transfer pulse Tt are set to the low level to turn off the transistors Tr5 and Tr4, respectively.

Next, the electric charge due to the subject light image is accumulated in the photodiode PD of FIG. When the storage is completed, only the transistor Tr4 is turned on by the transfer pulse Tt to transfer the charge of the photodiode PD to the capacitor C. The transfer period is a short high level period of the transfer pulse Tt immediately before the end of the blanking period of the vertical synchronizing signal, as indicated by g in FIG. 11 (B3). Therefore, the photodiode P
Although not all the charges in D have been transferred and some charges remain in PD, they are erased at the next reset.

Next, the row selection pulse Th is set to the high level at the read timing determined by the position of each pixel during the video period other than the blanking period of the vertical synchronizing signal to turn on the transistor Tr3 in FIG. Transistor Tr
The terminal voltage of the capacitor C amplified in 2 is output as a video signal via the transistor Tr3.

As a result, as shown in FIG. 11B4, the electronic shutter operation can be performed within the blanking period of the vertical synchronizing signal. Therefore, a very fast movement of the subject light image can be extracted as a still image. In addition, the reset pulse width depends on the light quantity of the light image of the presentation object, as shown in FIG.
Since the selection can be made as indicated by the dotted line in 2), the operation of the subject optical image that is faster can be stopped by increasing the light amount.

Next, the operation when the shutter operation is performed intermittently will be described. When a moving subject is imaged, when the shutter operation is continuously performed using the pulse trains shown in FIGS. 11A2 and 11A3, when the movement of the subject optical image is fast, FIG. As shown, the whole image overlaps and only a blurred image is obtained. Also, FIG.
When the pulse trains shown in 2 (B2) and (B3) are used, it is possible to capture an image only in a moment, so it is difficult to capture the subject optical image of this fast operation.

Therefore, in order to continuously obtain the still images of the fast-moving subject light image, in the present embodiment, a mechanical shutter as shown in FIG. 13 is inserted between the lens 21 and the image pickup section 22 of the image pickup device. . This mechanical shutter includes a motor 41, a rotating disk 43 having a rotating shaft 42 of the motor 41 having a tip end fixed to the center thereof, and a motor synchronous drive unit 45 for controlling the rotation of the motor 41. Rotating disk 4
Reference numeral 3 includes an opening 44a that allows light to pass therethrough, and a light-shielding portion 44b that shields the light. The optical path from the lens 21 to the image pickup unit 22 along the rotation of the rotating disk 43 is arranged along the opening 44a and the light-shielding portion 3. By alternately crossing with 44b, light is intermittently shielded.

Next, the image pickup section 22 is set in a state of operating with the pulse train shown in FIGS. 12A2 and 12A3, and the subject optical image is picked up by the image pickup section 22 during the vertical synchronizing signal period.
Then, the motor 41 in FIG. 13 is driven by the drive signal generated by the motor synchronous drive section 45 from the image pickup section 22.
The rotary disk 43 is rotated by driving the rotary disk 43. As a result, in response to the vertical synchronizing signal shown in FIG. 14A, the optical path from the lens 21 to the image pickup section 22 is intermittently shielded by the rotation of the rotary disk 43, and the intermittent shutter state shown in FIG. Become. The intermittent shutter sets the intermittent number and interval according to the movement of the subject light image and the light amount.

That is, as the motor 41 and the rotary disc 43 rotate, the subject optical image passing through the opening 44a of the rotary disc 43 is intermittently sent to the image pickup unit 22 and output from the image pickup unit 22 as a video signal. The light image of the subject is intermittently captured by the imaging unit 22, and the intermittent shutter image shown in FIG. 12A is obtained. By doing so, even if the movement of the subject light image is fast, it is displayed as a continuous intermittent image, so that it can be taken out as a still image. This still image is
Since the periphery of the photodiode PD shown in FIG. 10 can be obtained by the CMOS image pickup unit having a simple structure, a clear still image with good image quality can be obtained.

The present invention is not limited to the above-described embodiment, and for example, the pixel circuit shown in FIG. 10 is used for each pixel of the pixel constituent parts 110 to 113 shown in FIG. Although the peripheral circuit can be incorporated in the CMOS structure on the same wafer plane as shown in FIG. 1, the peripheral circuit need not be incorporated in the CMOS structure. However,
The pixel circuit shown in FIG. 10 is a CMO on the same wafer plane.
When incorporated in the S structure, the shutter drive pulse control unit is not required in the peripheral circuit.

When the mechanical shutter mechanism including the rotating disk 43 shown in FIG. 13 performs the intermittent shutter, the pixel circuit is not limited to that shown in FIG. 10, and the pixel circuit having the circuit configuration shown in FIG. 2 is used. It can also be used in circuits. Furthermore, the pixel configuration unit is not limited to one in which the number of pixels in the horizontal direction of the standard HDTV image is twice, and the number of pixels in the vertical direction is twice, and the pixel configuration unit is divided into four. M times the number of pixels in the vertical direction and n times the number of pixels in the vertical direction (one of m and n is an integer of 2 or more, the other is an integer of 3 or more)
The number of pixels may be m.n divided pixels in the horizontal direction, and the number of pixels may be m.n. Furthermore, in the above-described embodiment, it has been described that the pixels are arranged in a two-dimensional matrix, but they may be arranged in a one-dimensional linear form.

[0076]

As described above, according to the present invention,
The pixel structure section, the image data shaping section, the drive pulse control section, and the shutter drive pulse control section are each configured with a CMOS structure so that they are all built-in as a CMOS structure on the same plane of the wafer. It is possible to realize a video signal generator having high performance such as electric power and high speed, which does not require peripheral circuits and can be easily driven. In particular, by outputting the read signal in the shutter period, the memory control of the video signal processing circuit in the subsequent stage becomes easy, and the short-time exposure and the long-time exposure can be easily performed.

Further, according to the present invention, it is possible to obtain a high-resolution video signal having a number of pixels M × N times the number of pixels of a standard high-definition television (HDTV) image. Still images can be obtained.

Further, according to the present invention, since long-time exposure is possible, a practical image can be obtained even when the irradiation amount of the subject light image is extremely small such as the starry sky.

Further, according to the present invention, by devising the method of applying the drive pulse and eliminating the need for the shutter signal transistor for resetting the charge of the photodiode, the number of transistors around the photodiode can be made smaller than the conventional one. The structure around the photodiode can be simplified, noise can be less likely to mix in, and charge can be less easily discharged.In addition, even when the area of the image pickup unit is reduced, the wiring part is not complicated. Because it can be suppressed as much as possible,
High-quality video signals can be generated with a compact structure.

According to the present invention, the reset transistor and the transfer transistor are simultaneously turned on for a first predetermined period to generate a reset pulse and a transfer pulse for resetting the storage section and the photodiode, and then the transfer transistor. Only the second switch is turned on for the second predetermined period to generate a transfer pulse that transfers the electric charge accumulated in the photodiode to the accumulating unit, so that the fast shutter operation is performed, so that the subject light image is clear even in a moving image. It is possible to obtain a still image with good image quality.

Further, according to the present invention, the mechanical shutter mechanism intermittently accumulates the electric charge of the subject light image in the photodiode, so that a continuous intermittent image signal can be generated even if the subject light image operates quickly. Because it can occur
Even if the subject light image in the vertical synchronizing signal period, the vertical blanking period, and the intermittent period of the vertical synchronizing signal period is in a moving image state, a clear still image with good image quality can be intermittently obtained.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a video signal generator of the present invention.

FIG. 2 is a first pixel circuit which constitutes a pixel configuration unit in FIG.
It is a circuit diagram of an embodiment of.

FIG. 3 is a diagram showing a pulse example of a shutter operation of FIG.

FIG. 4 is a diagram showing an example of a long-time shutter operation of FIG.

5 is a block diagram of an example of a camera system including the video signal generator of FIG.

6 is a block diagram of an example of an image data shaping unit in FIG.

FIG. 7 is a pixel configuration of a main part in FIG. 5 and FIG.
It is a figure which shows the memory operation example of the horizontal / standard conversion part in the inside.

FIG. 8 is a diagram showing an example of a memory operation of a horizontal / standard conversion unit at the time of short-time exposure in FIG.

9 is a diagram showing a memory operation example of a horizontal / standard conversion unit at the time of long-time exposure in FIG.

FIG. 10 is a circuit diagram of a second embodiment of a pixel circuit that constitutes the pixel configuration unit in FIG.

11 is a diagram illustrating the shutter operation of FIG.

FIG. 12 is a diagram showing images at an intermittent shutter and a continuous shutter of the present invention.

FIG. 13 is a configuration diagram of an example of a mechanical shutter device in the device of the present invention.

14 is a diagram showing the mechanical shutter operation of FIG. 13 in relation to a vertical synchronizing signal.

FIG. 15 is a block diagram of an example of a conventional video signal generator.

[Explanation of symbols]

10 Video signal generator 12 Drive pulse controller 13 Shutter drive pulse controller 14 Image data shaping section 22 Imaging unit 23 A / D converter 25 Horizontal / standard converter 26 Parallel / serial converter 31 Black level fixing circuit 32 gain / offset adjustment circuit 33 A / D converter 34 Output signal shaping circuit 41 motor 43 rotating disk 44a opening 44b Light-shielding part 45 Motor synchronous drive unit 110-113 pixel configuration unit Tr1 MOS field effect transistor for shutter Tr2 amplification MOS field effect transistor Tr3 Row selection MOS field effect transistor Tr4 transfer MOS field effect transistor Tr5 reset MOS field effect transistor PD photodiode

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 4M118 AA04 AA10 AB01 BA14 CA02                       DD11 DD12 FA06 FA14 FA33                       GA10                 5C024 CX39 CX54 CY47 DX02 GY31                       GZ41

Claims (8)

[Claims] 1. A pixel configuration unit that captures a subject light image with a photodiode and converts it into image data that is an electric signal, and noise removal and signal level adjustment shaping processing for the image data output from the pixel configuration unit. And an image data shaping section for outputting as a video signal to the outside, and a reset pulse, a transfer pulse and a row selection pulse are generated based on a horizontal synchronizing signal, a vertical synchronizing signal and a reset signal and supplied to the pixel forming section. The drive pulse control section and the shutter drive pulse control section that generates a shutter signal based on shutter control signal data and supplies the shutter signal to the pixel configuration section are formed as a CMOS structure on the same plane of the wafer. Video signal generator. 2. The pixel configuration unit is M times the number of pixels in the horizontal direction of a standard high definition television image (M is an integer of 2 or more).
And the number of pixels N times the number of pixels in the vertical direction (N is an integer of 2 or more) is M · N divided by M
The image data shaping unit includes N divided pixel constituent units, outputs a total of MN image data in parallel from the MN divided pixel constituent units, and the image data shaping unit divides the MN divided units. It is characterized in that noise reduction and signal level adjustment shaping processing are separately applied to MN image data output in parallel from the pixel configuration unit and output in parallel as MN video signals to the outside. The video signal generator according to claim 1. 3. Each of the pixels forming the pixel structure section has a photodiode that accumulates electric charges according to the amount of incident light when a subject light image is irradiated, and a transfer transistor that transfers the electric charges accumulated in the photodiode. A storage unit for storing the charges of the photodiode transferred via the transfer transistor, an amplification transistor for amplifying the charges stored in the storage unit, and a charge amplified by the amplification transistor. A row selection transistor that is turned on and output by the row selection pulse, a reset transistor that resets the storage unit, and a shutter signal transistor that resets the accumulated charge of the photodiode by the shutter signal, The shutter drive pulse control unit controls all pixels within the blanking period of the vertical synchronization signal. After the transistors for shutter signals are turned on and the accumulated charges in the photodiodes of all pixels are simultaneously set to zero, a shutter signal for simultaneously turning off the transistors for shutter signals of all pixels is periodically generated, and the drive pulse control is performed. The unit turns on the transfer transistor immediately before the shutter signal transistor turns on after the reset pulse that turns on the reset transistor is turned on while the shutter signal transistor is off, and The transfer pulse that turns off the transfer transistor is generated immediately before the blanking period of the vertical synchronization signal, and the charge accumulated in the photodiode during the period when the shutter signal transistor is off is turned on. After transferring to the storage unit via the transfer transistor, The row selection pulse for sequentially turning on the row selection transistors is output at a read timing determined at a read position of each pixel in a video period outside the blanking period of the vertical synchronization signal. 1. The video signal generator according to 1 or 2. 4. The shutter drive pulse control unit is 1
Within the vertical sync signal period or within multiple vertical sync signal periods,
4. The video signal generator according to claim 1, wherein the shutter signal for turning off the shutter signal transistor is generated. 5. A subject optical image is converted into a video signal which is an electric signal and output by a plurality of pixel circuits forming an image pickup section and drive pulse generation means for supplying various drive pulses to the plurality of pixel circuits. In the video signal generating device, each of the plurality of pixel circuits includes a photodiode that accumulates charges corresponding to the amount of incident light when a subject light image is irradiated, and a transfer transistor that transfers the charges accumulated in the photodiode. A storage unit that stores the charges of the photodiode transferred via the transfer transistor, an amplification transistor that amplifies the charges stored in the storage unit, and a charge that is amplified by the amplification transistor. A row selection transistor that is turned on and output by a row selection pulse, and a reset transistor that resets the storage unit The drive pulse generating means turns on the reset transistor for a first predetermined period to generate a reset pulse for resetting the storage unit, and then turns on the transfer transistor for a second predetermined period. , Generating a transfer pulse for transferring the electric charge accumulated in the photodiode to the accumulating section to all pixel circuits at the same time, and then performing a read operation determined at a read position of each pixel in a video period. A video signal generating device having a configuration for generating the row selecting pulse for sequentially turning on the row selecting transistor at a timing. 6. A subject light image is converted into a video signal, which is an electric signal, and output by a plurality of pixel circuits forming an image pickup section and drive pulse generation means for supplying various drive pulses to the plurality of pixel circuits. In the video signal generating device, each of the plurality of pixel circuits includes a photodiode that accumulates charges corresponding to the amount of incident light when a subject light image is irradiated, and a transfer transistor that transfers the charges accumulated in the photodiode. A storage unit that stores the charges of the photodiode transferred via the transfer transistor, an amplification transistor that amplifies the charges stored in the storage unit, and a charge that is amplified by the amplification transistor. A row selection transistor that is turned on and output by a row selection pulse, and a reset transistor that resets the storage unit The drive pulse generating means is configured to simultaneously turn on the reset transistor and the transfer transistor for a first predetermined period to generate a reset pulse and a transfer pulse for resetting the storage section and the photodiode, Only the transfer transistor is turned on for a second predetermined period to generate a transfer pulse for transferring the electric charge accumulated in the photodiode to the accumulating unit, for all pixel circuits at the same time. In the video period, the video signal generator is configured to generate the row selection pulse that sequentially turns on the row selection transistor at a read timing determined by a read position of each pixel in the video period. 7. The drive pulse generating means generates only the reset pulse or the reset pulse and the transfer pulse with a certain period from the beginning of a blanking period of a vertical synchronization signal as the first predetermined period, The transfer pulse is generated with the period from the predetermined time point immediately after the first predetermined time period has elapsed to immediately before the end of the vertical synchronization signal retrace line period as the second predetermined period, and the retrace line period of the vertical synchronization signal is generated. 7. The video signal generating device according to claim 5, wherein the row selection pulse is sequentially generated in an external video period. 8. A mechanical shutter mechanism for intermittently irradiating the photodiode with the subject light image on the incident light side of the photodiodes of all pixel circuits, wherein the drive pulse generating means is the mechanical shutter mechanism. 6. The reset pulse and the transfer pulse are generated so as to intermittently transfer and accumulate charges according to the light quantity of the subject light image accumulated in the photodiode to the accumulation unit. 8. The video signal generator according to any one of items 1 to 7.