JP2010011392A - Imaging apparatus and solid-state imaging device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an imaging apparatus and a solid-state imaging device matching scan timing of a front-curtain electronic shutter to running characteristics of a curtain shutter without causing any side effect such as inviting deterioration in image quality or missing a shutter chance in the imaging apparatus. <P>SOLUTION: In the imaging apparatus or the solid-state imaging device, that the imaging apparatus incldues, a vertical scan control section 220 for controlling pixel reset in a pixel array includes a curtain shutter synchronizing mode for performing reset scan on pixels of a plurality of rows being adjacent within one horizontal scan term. The vertical scan control section 220 includes a means wherein, during such a mode, M rows in a pixel array 210 is divided into K sets (K is a natural number smaller than M) constituted of a plurality of adjacent rows so as to complete the pixel reset scan on the plurality of rows divided into the sets within one horizontal scan term, respectively, and the number of rows in each set can be arbitrarily selected so as to match pixel reset scan with running characteristics of a second-curtain shutter. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device such as a MOS type or an imaging device using a solid-state imaging device such as a MOS type, and particularly relates to a technique suitable for a single-lens reflex camera as an imaging device.

  Digital cameras that replace silver halide camera films with solid-state image sensors have been the mainstream of the camera market for a long time. Thanks to the digitalization, not only a dedicated camera called “camera” but also a camera function has been added to mobile phones and computers, making it usable for everyone. The market has been rapidly expanding in recent years, supported by improvements in image quality and functions, and lower prices that go backwards.

Single-lens reflex cameras are characterized by the ability to use a series of interchangeable lenses on the premise of the same optical design, and are designed to enjoy image creation with the camera, but on the other hand, their size and weight are large This is a foothold for further market expansion. For example, a single-lens reflex camera has a curtain shutter as one of the features. However, if both the front curtain and the rear curtain are provided, there is a drawback that the mechanism becomes large, so the exposure start timing of the solid-state imaging device is determined. There is a proposal of a solid-state image pickup device equipped with a front-curtain electronic shutter function that replaces this by the pixel reset scanning timing of the solid-state image pickup device itself without using the front curtain shutter, or a camera using the same (for example, Patent Document 1). ).
Japanese Patent Laid-Open No. 11-41523

  According to Patent Document 1, by increasing the clock frequency for performing the pixel reset scanning of the solid-state imaging device only for the pixel reset scanning period, the time required for the pixel reset scanning of all rows of the solid-state imaging device is set as the running time of the curtain shutter. The technique of matching is disclosed (FIG. 2B of Patent Document 1; reprinted as FIG. 11 in this specification).

  Also, even when the curtain shutter travel speed is not constant, the time required for the pixel reset scan of all the solid-state image sensors is adjusted by modulating the clock frequency for performing the pixel reset scan of the solid-state image sensor. A technique of adjusting to the traveling time is disclosed (FIG. 3B of Patent Document 1; reprinted as FIG. 12 in this specification).

  In order to clarify the problems included in the technology disclosed herein, the difference in the pixel reset scanning period depending on whether or not the curtain shutter is used will be described.

  When the curtain shutter is not used, the pixel reset scanning of the solid-state imaging device is performed one row at a time in one horizontal scanning period (hereinafter referred to as 1H) as in the pixel readout scanning, thereby making the exposure time of each row uniform. (FIG. 13A). Therefore, the time taken to scan one screen of the solid-state imaging device is determined by the pixel readout rate. Although the speed of pixel readout has been increased, the number of pixels continues to increase, so that the output rate of all pixel readout in a large solid-state imaging device used for a single-lens reflex camera is considered not to change much. For example, in a solid-state imaging device whose rate is 5 frames per second, that is, a pixel readout scanning period for one screen is 200 ms, the pixel reset scanning period when the curtain shutter is not used is also 200 ms.

  On the other hand, the traveling time for the curtain shutter to cross the entire imaging surface is, for example, 4 ms, and it can be seen that the order is greatly different (FIG. 13B).

  Now, looking at the number of pixels of commercial cameras, compact cameras already exceed 10 million pixels, and single-lens reflex cameras that are assumed to be the subject of the present invention are expected to exceed 20 million pixels in the near future. . Therefore, for example, a solid-state imaging device having a vertical and horizontal ratio of 4 to 3 and having 5200 (V) × 3900 (V) and 20 million or more effective pixels will be described below as a model case.

  One frame cycle of the model case requires roughly 4000 rows of horizontal scanning cycles including the vertical blanking period.

200ms ÷ 4000 lines = 50μs
4ms ÷ 4000 lines = 1μs

  In other words, the maximum time that can be used for the pixel reset scanning when the curtain shutter is not used is 50 μs per row, while the pixel reset scanning when the curtain shutter is used is only 1 μs per row on average. In addition, because of the non-linearity due to the mechanical response of the curtain shutter, the reset scanning in the first half of the shutter operation becomes longer, but the pixel reset scanning period is significantly shorter than 1 μs in each row in the second half. Since the pixel reset usually requires about 1 μs, a charge remaining due to insufficient reset of the pixel causes an image quality problem of afterimage.

  In Patent Document 1, as described with reference to FIG. 10 (represented as FIG. 14 in this specification) in paragraphs 0077 and 0088, the pixel reset pulse is sequentially applied line by line. There is no description of measures for shortening the horizontal scanning period as viewed from the reset scanning and further shortening as the line advances.

  In order to solve this, it is only necessary to extend a reset period for one row by allowing a plurality of reset scans to overlap as shown in FIG. However, in order to match the reset scanning with the running characteristics of the curtain shutter, there arises a driving problem that the clock frequency needs to be modulated at the rising and falling timings of the pixel reset pulse. Further, if reset scanning by clock modulation is performed with the pixel reset pulse width being constant in order to make the characteristics of each row uniform, it becomes impossible to enter the driving for falling until the rising of all rows is completed. For this reason, the time from the start of reset of the first row (rise of reset pulse) to the end of reset of the last row (fall of reset pulse) is 8 ms or more, which is twice the curtain shutter travel time. In this case, a sufficient pixel reset pulse width is as long as 4 ms with a few μs (if the curtain shutter speed is slow, this time becomes even longer). This means that when viewed from the camera system, the response from pressing the release button of the camera to capturing an image is delayed, and a photo opportunity is missed.

  Therefore, the present invention provides an image pickup apparatus and a solid-state image pickup device that can match the scanning timing of the front curtain electronic shutter with the running characteristics of the curtain shutter without causing side effects such as degradation of image quality or missing a photo opportunity. The purpose is to provide.

  In order to achieve the above object, an imaging apparatus according to the present invention is an imaging apparatus having a solid-state imaging element and a mechanical shutter that controls the end of exposure of the solid-state imaging element. A pixel array in which pixels are arranged in M rows and N columns (M and N are natural numbers), and a vertical scanning control unit that controls pixel reset and pixel reading of the pixel array. A curtain shutter synchronization mode for performing reset scanning of pixels in a plurality of rows adjacent to the scanning period. In the curtain shutter synchronization mode, the completion of the pixel exposure period is substantially reduced by light shielding in the rear curtain operation of the mechanical shutter. And dividing the M rows of the pixel array into K sets (K is a natural number smaller than M) composed of one or more adjacent rows, a plurality of rows of pixel reset scanning divided into each set are performed. Performed in respectively one horizontal scanning period, so as to match the pixel reset scanning the traveling characteristics of the rear curtain shutter, it features more optional number of rows each set.

  In order to achieve the above object, a solid-state imaging device according to the present invention includes a pixel array in which a plurality of pixels are arranged in M rows and N columns (M and N are natural numbers), a pixel reset of the pixel array, and a pixel A solid-state imaging device including a vertical scanning control unit that controls reading, wherein the vertical scanning control unit has a curtain shutter synchronization mode that performs reset scanning of pixels in a plurality of rows adjacent to one horizontal scanning period, and In the curtain shutter synchronization mode, when the M rows of the pixel array are divided into K groups (K is a natural number smaller than M) composed of one or a plurality of adjacent rows, each pixel reset scan is performed in one horizontal scanning period. The number of rows in each group can be arbitrarily selected.

  Thus, in the curtain shutter synchronization mode, the completion of the pixel exposure period is substantially performed by light shielding in the rear curtain operation of the mechanical shutter, and the M rows of the pixel array are made up of one or a plurality of adjacent rows. In the case of a set (K is a natural number smaller than M), each of the plurality of rows of pixel reset scans divided into each set is performed in one horizontal scan period, and each pixel reset scan is adjusted to match the running characteristics of the trailing shutter. Since the number of rows in the set can be arbitrarily selected, the scanning timing of the front curtain electronic shutter can be matched to the running characteristics of the curtain shutter without causing side effects such as degradation of image quality and missing photo opportunities.

  The present invention can avoid a problem that a reset pulse width necessary for image quality is insufficient in a solid-state imaging device that realizes high-speed pixel reset scanning in accordance with curtain shutter running characteristics. In addition, even in the curtain shutter synchronization mode, the same pixel reset scanning timing as in the native mode can be used in the curtain shutter synchronization mode without using the method of clock frequency modulation, so that it is easy to design a solid-state imaging device having two modes. Similarly, because the clock frequency is not modulated, there is no extra restriction on the timing relationship between the rise and fall of the pixel reset pulse, and the time from the start of pixel reset in the first row to the end of pixel reset in the last row is reduced. Since a solid-state imaging device that can be suppressed to the same level as the curtain shutter travel time can be realized, it is possible to provide a camera system that does not miss a photo opportunity.

  Therefore, the practical value of the present invention in which digital cameras such as digital single-lens reflex cameras have prevailed is extremely high.

A configuration of an imaging apparatus according to an embodiment of the present invention is shown in FIG.
As shown in the figure, the imaging device (camera) is a single-lens reflex camera or the like, and is roughly composed of an optical system 100, a solid-state imaging device (image sensor) 200, an image signal processing unit 300, and a control unit 400. ing.

  The optical system 100 is located on the optical path between the lens 101 and the solid-state image sensor 200, and the lens 101 that collects light from the subject and forms an image on the pixel array of the solid-state image sensor 200. A mechanical shutter 102 (hereinafter referred to as curtain shutter) that controls the amount of light guided upward is provided.

  The solid-state imaging device 200 selects a pixel array 210 in which unit pixels including a photosensitive element such as a photodiode and a MOS transistor are arranged in a two-dimensional array, and selects the pixels of the pixel array 210 in units of rows, A vertical scanning control unit 220 that controls reading, an A / D conversion circuit 230 that performs A / D conversion on the pixel signals read from the pixel array 210, a column digital memory 240 that holds the A / D converted pixel signals, A horizontal scanning unit 250 that selects each column of the column digital memory 240 and drives reading of the held digital pixel signal is provided.

  The image signal processing unit 300 receives a digital pixel signal output from the solid-state imaging device 200 and performs a DSP (processing such as gamma correction, color interpolation processing, spatial interpolation processing, and auto white balance necessary for camera signal processing. (Digital Signal Processor). In some cases, conversion to a compression format such as JPEG, recording in a memory, display signal processing on a liquid crystal screen provided in the camera, and the like may be performed.

  The control unit 400 controls the optical system, the solid-state imaging device, and the image signal processing unit in accordance with various settings designated by a user I / F (not shown), and a microcomputer that integrates the entire operation of the imaging apparatus. It is. As the user I / F, for example, a zoom magnification change and a real-time instruction such as a release button are received as inputs, and the zoom magnification change of the lens 101, the running of the curtain shutter 102, and the reset scanning of the solid-state imaging device 200 are controlled. In particular, from the viewpoint of the present invention, it is assumed that a camera system designer writes a control parameter related to reset scanning in accordance with the running characteristics of the curtain shutter into a reset scanning register (to be described later) via the user I / F. .

  A part of the solid-state imaging device 200 related to the reset scanning of the vertical scanning control unit 220 including the connection with the pixel array 210 will be described with reference to FIG. Note that a pixel readout scanning circuit included in the vertical scanning control unit 220 and a circuit connected to and connected to the pixel readout only are omitted in this drawing.

  The vertical scanning control unit 220 controls the RSi signal for controlling the On / Off of the pixel reset transistor and the On / Off of the pixel transfer transistor every horizontal scanning period (1H) which is a cycle time for reading out pixels for one row. A horizontal synchronization signal generation circuit 221 that generates an RSg signal or a TXg signal that is an original signal common to each row of the TXi signal that controls Off, and a pixel reset scanning circuit that performs selective scanning for resetting pixels in each row of the pixel array 210 222 and a reset scanning register 223 for designating control parameters of the pixel reset scanning circuit.

  Hereinafter, the pixel reset scanning timing in the case where the curtain shutter is not used will be described with reference to FIG.

  The original signals RSg and TXg output from the horizontal synchronizing signal generation circuit 221 are signals that become active once in one horizontal scanning period. From the pixel reset scanning circuit, SEL1, SEL2,. . . The row selection signal SELi that is sequentially output is basically a signal that becomes active for one horizontal scanning period, and after performing a logical product with the above-mentioned original signals RSg and TXg, the waveform shaping buffer (or signal amplitude conversion) Are also sequentially output as RSi and TXi.

  The reset is effective for the pixel during the period when RSi and TXi are simultaneously “H”. However, as described in “Problems to be Solved by the Invention”, in the assumed camera system, 1 The horizontal scanning period is, for example, 50 μs, and the period necessary for “H” of RSi and TXi is about 1 μs.

  Here, as described with reference to FIG. 3, a mode in which reset scanning of pixels for only one row in one horizontal scanning period is referred to as “native mode” in this specification. On the other hand, since the curtain shutter is used, a mode in which the pixel reset scanning is synchronized with the curtain shutter scanning timing is referred to as a “curtain shutter synchronization mode”.

  Next, pixel reset scanning timing in the curtain shutter synchronization mode will be described with reference to FIG. Similarly, the original signals RSg and TXg output from the horizontal synchronizing signal generation circuit 221 are signals that become active once in one horizontal scanning period, and basically have the same one horizontal scanning period. The width and timing are the same. However, in the curtain shutter synchronization mode, a plurality of lines can be reset simultaneously and the number of lines can be changed according to the line address according to the setting of the reset scanning register as will be described later. FIG. 4 shows the state as a timing waveform. Among the row selection signals SELi output from the pixel reset scanning circuit, after resetting SEL1 and SEL2 one by one, SEL3 and SEL4 become active at the same time. It can be seen that the third and fourth lines are reset simultaneously.

  In other words, considering the operation of the vertical scanning control unit 220 of the present invention for all the M rows of the pixel array, the M rows of the pixel array are divided into K sets (K is a natural number smaller than M) including one or a plurality of adjacent rows. Separately, pixel reset scanning of a plurality of rows in each group is performed in one horizontal scanning period, and pixel reset scanning in all K groups is performed in a K horizontal scanning period. The number of rows in each group can be arbitrarily selected so that the pixel reset scanning is shortened to M and the running characteristics of the rear curtain shutter are matched.

  In FIGS. 3 and 4, RSi is shown as a waveform for each row as in TXi. However, for RSi, all rows are activated during the pixel reset period, and only TXi is scanned vertically. It is also possible to perform control such as.

  In FIG. 2, in order to facilitate understanding of the pixel arrangement, a photodiode (hereinafter referred to as PD) that converts incident light into electric charge and a floating diffusion (hereinafter referred to as FD) of the electric charge of the photodiode. The configuration of one pixel in the i row and j column includes a transfer transistor that controls the transfer of the FD and PD by the signal TXi, a reset transistor for resetting the FD and PD by the signal RSi, and an SF transistor that reads the potential of the FD to the pixel output line Pj. Although shown in the figure, the present invention can be applied to a pixel configuration including a selection transistor for selecting an output, or a pixel configuration in which a plurality of pixels share one FD or one reset transistor. Applicable.

  3 and 4 is a power source of the pixel. In the case of the pixel configuration shown in FIG. 2, voltage control may be performed at the time of reading. Since the power supply potential may be maintained during reset scanning, it is not directly related to the present invention.

Next, the details of the reset scanning register 223 will be described with reference to FIG.
As shown in the figure, the reset scanning register 223 is a register file, and includes K−1 registers from “simultaneous reset row number change point 1” to “simultaneously reset row number change point K−1”, K registers from “pixel reset row number 1” to “simultaneous pixel reset row number K” are provided.

  The “simultaneous reset row number change point i” is a register that designates a row corresponding to a break point when the pixel reset scan is viewed as a line graph. The “simultaneous pixel reset row number i” is a register for designating the number of rows to be simultaneously reset in one horizontal scanning period. Similarly, the correspondence to the line graph is a parameter corresponding to the inclination of each line.

  Hereinafter, a specific operation by the vertical scanning control unit 220 will be described with reference to FIG. 6 which is a flowchart of broken line approximation.

  First, at the start of vertical scanning, a counter value indicating a pixel reset row is initialized (to zero) (step a0 in FIG. 6; the same applies hereinafter). Next, if the condition determination (step a1) of (counter value ≦ “simultaneous reset row number change point 1”) is satisfied, the counter value is incremented by “simultaneous pixel reset row number 1” (step a2), Counter value + 1− “simultaneous pixel reset row number 1”) A reset signal is simultaneously output from the (counter value) row to the (counter value) row (step a3).

  When the condition of a1 is not satisfied and the condition determination (step a4) of (counter value ≦ “simultaneous reset row number change point 2”) is satisfied, the counter value is set to “simultaneous pixel reset row number 2”. "Counter value + 1-" Simultaneous pixel reset row number 2 ") and simultaneously output a reset signal from the (counter value) row to the (counter value) row (step a6).

  Further, when the condition of (counter value ≦ “simultaneous reset row number change point K−2”) is not satisfied, and the condition determination of (counter value ≦ “simultaneous reset row number change point K−1”) (step a7) ), The counter value is incremented by “simultaneous pixel reset row number K−1” (step a8), and (counter value + 1− “simultaneous pixel reset row number K−1”) from the row (counter value) ) A reset signal is simultaneously output up to the line (step a9).

  If the counter value is larger than “simultaneous reset row number change point K−1”, the counter value is incremented by (simultaneous pixel reset row number K) (step a10), and (counter value + 1− “simultaneous pixel reset row”). The reset signal is output from the (number K ") line to the (counter value) line (step a11).

  Finally, after waiting for the horizontal scanning start timing (step a12), it is determined whether or not the vertical scanning is completed. If not, the horizontal scanning cycle is repeated (steps b1 and b2). If the vertical scanning is completed, the pixel reset scanning as the front curtain electronic shutter is completed.

  Hereinafter, the operation of the vertical scanning control unit 220 in the curtain shutter synchronization mode will be described using FIGS. 7A and 7B and assuming more specific register setting values.

  In FIG. 7A, the vertical axis corresponds to each row of the pixel array, the horizontal axis corresponds to time, the left end of the horizontally long box of each row indicates the pixel reset end timing c1 of each row, and the right end indicates each row. The read timing c3 is shown. The exposure time c4 of the solid-state imaging device starts from the pixel reset end timing c1 of each row and ends at the rear curtain shutter timing c2 crossing the center of the drawing.

  For example, as shown in FIG. 7B, the setting values of the simultaneous reset row number changing points 1, 2, and 3 are set to 4, 12, and 27, respectively, and the setting values of the simultaneous pixel reset row numbers 1, 2, and 3 are set to 1. When the counter value is set to 2, 5, since the condition of step a1 is satisfied when the counter value is from the first line to the fourth line, each line is reset according to the number of simultaneous pixel reset lines 1 (= 1) (step 1). a2, a3).

  Since the counter value satisfies the condition of step a4 when the counter value is from the fifth line to the twelfth line, two lines are simultaneously reset according to the number of simultaneous pixel reset lines 2 (= 2) (steps a5 and a6).

  When the counter value is from the 13th line to the 27th line, the condition of step a7 is satisfied. Therefore, the reset is performed 5 lines at a time according to the number of simultaneous pixel reset lines 3 (= 5) (steps a8 and a9).

  The timing of the front curtain electronic shutter by pixel reset is increased by increasing the number of simultaneous pixel reset rows to 1 row, 2 rows, and 5 rows while keeping the pixel reset cycle constant (one horizontal scanning period). Can be approximated to the non-linear running characteristics of the rear curtain shutter.

  If the value of the “simultaneous pixel reset row number 1” register is 1, and the value of the “simultaneous reset row number change point 1” register is M (maximum number of rows of the solid-state imaging device), other reset scan register setting values Regardless of the operation, the operation is in the “native mode”. Further, if the value of the “simultaneous reset row number change point 1” register remains M and the value of the “simultaneous pixel reset row number 1” register is 4, reset is performed for every four rows from the beginning to the end of the pixel reset scanning. (There is no break point and the slope is constant).

  Hereinafter, a method of performing reset scanning while changing the number of rows simultaneously selected by the pixel reset scanning circuit 222 in accordance with information in the reset scanning register 223 will be described with reference to FIGS. 8 and 9.

  First, at the start of pixel reset scanning, the row address counter 61 is initialized (set to zero) by an rst_v signal received from the control unit 400. As shown in the control flow of FIG. 6, the decoder is masked at this stage.

  Next, the address range determination circuit 62 compares the data (count) of the row address counter 61 with the value set in the “simultaneously resetting row number change point” register (determines which address range is present). As a result, select_num which is one of the values 1 to K is output, and the selector 63 outputs the value of the “simultaneous pixel reset row number” register corresponding to select_num as select_data.

  The simultaneous row number clock pulse generation circuit 64 outputs clk_s as clock pulses count_clk for the number of input simultaneous pixel reset rows (select_data). For example, as shown in FIG. 9, when select_data is 1, one pulse is output, and when it is 2, two pulses are output as count_clk.

  Each time the count_clk pulse is input, the row address counter 61 increments the value and outputs it as a counter value (count).

  Each time the count value is input, the address decoder 65 decodes the input count value as a row address, activates any one of the corresponding line_sel1 to line_selM (“H” level), and the reset row selection circuit 66 “H” is written in the corresponding latch. This latch is called a reset selection latch.

  The Hi level is fixedly connected to the data input terminal of the reset selection latch, and any of line_sel1 to line_selM which is the output of the address decoder 65 is connected to the clock input terminal. The “H” level is written when this signal becomes active.

  All the row addresses corresponding to the number of rows to be simultaneously reset in one horizontal scanning period are sequentially decoded, and 1 is written in all the reset selection latches of the corresponding row of the reset row selection circuit 66. By taking the logical product of the latch value and the TXg or RSg generated from the horizontal synchronizing signal generation circuit 221 (see FIG. 2), the reset row selection circuit 66 makes all the selections that hold 1 in the reset selection latch. Perform row pixel reset. Finally, the reset selection latch is reset ("L" level writing) by the rst_h signal received from the control unit 400, thereby completing the reset scanning for one horizontal scanning period. Next, as shown in the control flow of FIG. 6, the process from the address comparison by the address range determination circuit 62 is repeated until the process for one frame is completed.

  By performing the above procedure, reset scanning can be performed while changing the number of rows selected by the pixel reset scanning circuit 222 at the same time.

Since the row addresses to be reset at the same time are sequentially decoded, the timing of writing 1 to the reset row selection circuit (reset selection latch) varies depending on the row, and as shown by the waveforms of SEL5 and SEL6 in FIG. The row selection signals themselves are not simultaneous. However, as clk_s input to the simultaneous row number clock pulse generation circuit 64, for example, a clock of about 40 MHz can be used. Therefore, when the number of simultaneous rows is, for example, 100 rows,
25 ns x 100 lines = 2.5 μs
As described above, when one horizontal scanning period is 50 μs, it can be said to be sufficiently short. Even if one horizontal scanning period is shorter than this, it is possible to avoid variation in reset timing between rows by providing a margin for the active timing of RSg and TXg.

  Furthermore, this variation can be fundamentally eliminated by changing the configuration of the reset row selection circuit 66 of the pixel reset scanning circuit shown in FIG. FIG. 10 shows a circuit configuration (modified example) in which only the reset row selection circuit of the pixel reset scanning circuit is changed. In the reset row selection circuit 67, the number of latches is increased by one to form a two-stage configuration, and after all decode signals are set in the preceding latch, once in one horizontal scanning period, the value is set in the succeeding latch by controlling the lat_cp_h signal , The timing at which the row selection signal SELi, which is the output of the subsequent latch, becomes active can be aligned.

  Here, if the latch of the previous stage is reset and then the value is copied to the latch of the subsequent stage by controlling the lat_cp_h signal, the latch of the subsequent stage can be reset. Therefore, the latch of the subsequent stage does not necessarily need a reset terminal.

  As described above, according to the imaging device in the present embodiment and the modification, in the curtain shutter synchronization mode, the pixel exposure period is substantially completed by the light shielding in the rear curtain operation of the mechanical shutter. When the M rows are K sets (K is a natural number smaller than M) consisting of one or a plurality of adjacent rows, pixel reset scanning of each row divided into each set is performed in one horizontal scanning period, The number of rows in each group can be arbitrarily selected so that the pixel reset scan matches the running characteristics of the rear curtain shutter, so that the front curtain electronic shutter does not cause side effects such as image quality degradation or missing photo opportunities. The scanning timing can be matched to the running characteristics of the curtain shutter.

  Note that the present invention can be applied regardless of the detailed configuration of the pixel. For example, the present invention also includes modifications obtained by making various modifications conceivable by those skilled in the art without departing from the spirit of the present invention. Further, the present invention can be applied without depending on the circuit system of the signal output path from the pixel, including the presence / absence of A / D conversion.

  In the present embodiment, the reset scanning register 223 is included in the vertical scanning control unit 220. However, the reset scanning register 223 may be included in another block as long as it is in the solid-state imaging device 200 of the present embodiment. For example, when the image signal processing unit 300 and the control unit 400 are mounted on the same silicon substrate as the solid-state imaging device 200 of the present embodiment, the reset scanning register 223 is included in the image signal processing unit 300 and the control unit 400. Also good.

  Further, in the present embodiment, the case where the number of simultaneous reset lines and the line address that changes as the reset scanning parameter has been described, but for example, the increment of the number of simultaneous reset lines instead of the number of simultaneous reset lines itself. The effect of the present invention is not changed by using as a parameter.

Also, for general purposes, the function Line = SHUT (t) representing curtain shutter travel characteristics
Is input to t as an input, and time 1, 2,... As values corresponding to 1H, 2H,. .. May be calculated as SHUT (1), SHUT (2),... And the number of simultaneous rows may be calculated from Linei + 1−Linei. This is not necessarily realized by an arithmetic unit, and a value may be output by referring to a lookup table.

  When the present invention is applied, as shown in FIG. 7, focusing on a set of a plurality of rows that are simultaneously reset, exposure starts at the same timing, but strictly speaking, exposure by the curtain shutter ends. Since the timing differs between the rows, it can be seen that there is a difference in the exposure time between the rows.

  However, as can be seen from FIG. 7, the difference is within 1H. As described above, for example, when the number of scanning rows of a solid-state imaging device having 10 to 20 million effective pixels is about 3000 to 4000 rows and the exposure time is 1 V (corresponding to one frame), the exposure of each row The maximum amount error is 1/3000 to 1/4000, that is, about 0.03%, which is negligible. When the exposure time is 1/30 · V (about 1/100 second in the case of a camera of 3 frames / second), this is about 1% and cannot be ignored, but the error in the exposure time of each row is caused by the reset scanning register 223. Since it is known as the set value, the value is shared with the image signal processing unit 300 in the subsequent stage, the image signal processing unit 300 obtains a correction gain for the signal output of each row, and can be easily corrected by multiplying it. In addition, since the correction gain value is close to unity gain, there is almost no error due to correction.

  The present invention, as an imaging device and a solid-state imaging device, can adjust the scanning timing of the front curtain electronic shutter to the running characteristics of the curtain shutter, particularly without causing side effects such as degradation of image quality and missing photo opportunities. As a MOS type imaging device and a MOS type solid-state imaging device that can be used, specifically, it can be used as a digital camera such as a single-lens reflex camera.

1 is a system configuration diagram of an imaging apparatus of the present invention. It is a detailed block diagram of the vertical scanning control part and pixel arrangement | sequence in the solid-state image sensor of this invention. It is a figure which shows the pixel reset scanning timing of native mode. It is a figure which shows the pixel reset scanning timing of curtain shutter synchronous mode of this invention. It is a figure which shows the reset scanning register which performs the parameter setting which concerns on the reset scanning of this invention. It is a figure which shows the control flow of the pixel reset scanning in the polygonal line approximation of this invention. It is a figure which shows the example of a setting of the reset scanning register of this invention, and the reset scanning timing by it. It is a figure which shows the structure of the pixel reset scanning circuit which concerns on the reset scanning of this invention. It is an example of the scanning waveform by the pixel reset scanning circuit of this invention. It is a figure which shows the different structure of the pixel reset scanning circuit which concerns on the reset scanning of this invention. It is a figure which shows the pixel reset scanning method by the conventional clock modulation, and is a method of raising a clock frequency only in a pixel reset period. It is a figure which shows the pixel reset scanning method by the conventional clock modulation, and is a method of changing a frequency within a pixel reset period. It is a figure which shows an example of the difference in the scanning timing by the presence or absence of curtain shutter use. It is a figure which shows the detail of the reset scan of the kth line of a pixel arrangement | sequence, and the pulse waveform in connection with it in the past. It is a figure for demonstrating the subject in the case of producing | generating the pixel reset pulse of several rows by clock modulation as a prior art.

Explanation of symbols

61 row address counter 62 address range determination circuit 63 selector 64 simultaneous row number clock pulse generation circuit 65 address decoder 66, 67 reset row selection circuit 100 optical system 101 lens 102 mechanical shutter (curtain shutter)
DESCRIPTION OF SYMBOLS 200 Solid-state image sensor 210 Pixel arrangement 220 Vertical scanning control part 221 Horizontal synchronizing signal generation circuit 222 Pixel reset scanning circuit 223 Reset scanning register 223-a Register group 223-b A register group which designates a synchronous reset row number change point Register group to be designated 230 A / D conversion circuit 240 Column digital memory 250 Horizontal scanning unit 300 Image signal processing unit 400 Control unit

Claims (5)

An imaging apparatus having a solid-state imaging device and a mechanical shutter that controls the end of exposure of the solid-state imaging device,
The solid-state imaging device includes a pixel array in which a plurality of pixels are arranged in M rows and N columns (M and N are natural numbers), and a vertical scanning control unit that controls pixel reset and pixel readout of the pixel array,
The vertical scanning control unit has a curtain shutter synchronization mode for performing reset scanning of pixels in a plurality of rows adjacent to one horizontal scanning period. In the curtain shutter synchronization mode, the completion of the pixel exposure period is determined by the mechanical shutter. Substantially performed by shading in the trailing curtain operation, the M rows of the pixel array are divided into K sets (K is a natural number smaller than M) divided into one or a plurality of adjacent rows. An image pickup apparatus, wherein a plurality of rows of pixel reset scanning are each performed in one horizontal scanning period, and the number of rows in each group is arbitrarily selected so that the pixel reset scanning is matched with the running characteristics of the rear curtain shutter.   The solid-state imaging device includes a register that holds the number of rows of each set that simultaneously performs pixel reset for each of a plurality of adjacent rows in the curtain shutter synchronization mode, and a row address that changes the number of simultaneous reset rows. 2. The image pickup apparatus according to claim 1, wherein reset scanning of the pixels is performed at a timing corresponding to the written register value. A solid-state imaging device including a pixel array in which a plurality of pixels are arranged in M rows and N columns (M and N are natural numbers), and a vertical scanning control unit that controls pixel reset and pixel readout of the pixel array,
The vertical scanning control unit has a curtain shutter synchronization mode for performing reset scanning of a plurality of rows of pixels adjacent to one horizontal scanning period. In the curtain shutter synchronization mode, the M rows of the pixel array are arranged in one or more mutually. A solid-state imaging device characterized by arbitrarily selecting the number of rows in each set for performing pixel reset scanning in one horizontal scanning period when divided into K sets (K is a natural number smaller than M) composed of adjacent rows. .   The solid-state imaging device includes a register that holds the number of rows of each set that simultaneously performs pixel reset for each of a plurality of adjacent rows in the curtain shutter synchronization mode, and a row address that changes the number of simultaneous reset rows. 4. The solid-state imaging device according to claim 3, wherein reset scanning of the pixel is performed at a timing corresponding to the written register value.   In the curtain shutter synchronization mode, the vertical scanning control unit divides the M rows of the pixel array into K sets (K is a natural number smaller than M) composed of one or a plurality of adjacent rows. 4. The solid-state imaging device according to claim 3, wherein the pixels are reset-scanned by making the rising timing and falling timing of the pixel reset scanning coincide with each other.

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