JP2003142965A - Variable gain amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a variable gain amplifier of low noise by simple constitution. SOLUTION: The amplifier is equipped with a field-effect transistor 1 for amplification, an input matching circuit 2 which is connected to the gate of the field-effect transistor 1 for amplification and an output matching circuit 3 which is connected to the drain of the transistor, and the drain of a field-effect transistor 5 for variable resistance whose source is grounded is connected between the drain of the transistor 1 and an output matching circuit 3 and a resistance 6 is connected in parallel between the source and drain of the field- effect transistor for variable resistance. The field-effect transistor 5 for variable resistance is turned on and off to vary the parallel resistance determined with the resistance 6, thereby varying the gain of the amplifier.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable gain amplifier used particularly in the microwave or millimeter wave band.

[0002]

2. Description of the Related Art FIG. 6 shows an example of a conventional variable gain amplifier. In the figure, 10 is a dual gate field effect transistor (hereinafter, the field effect transistor is abbreviated as FET), 2 is an input matching circuit connected to the gate of the dual gate FET 10, and 3 is output matching connected to the drain of the dual gate FET 10. Circuit.

Next, the operation of the conventional variable gain amplifier will be described. The source of the dual gate FET 10 is grounded, and is used after being converted into a desired impedance by the input matching circuit 2 and the output matching circuit 3. The dual-gate FET 10 has a second gate, unlike the normal FET, as the name implies. In addition to the normal bias supply to the gate and drain, the gain is varied by controlling the bias of the second gate. However, the dual gate FET has a high noise figure and a remarkable temperature characteristic. Further, a variable gain requires a highly accurate control voltage. In addition, since the noise figure is high, when the amplifiers are connected in multiple stages, the variable gain amplifier is connected to the subsequent stage and is rarely used in the first stage.

[0004]

[Problems to be Solved by the Invention] As described above,
In order to obtain variable gain in the conventional variable gain amplifier, there is a problem that a highly accurate control voltage power supply and a temperature compensating circuit are required and cannot be used in the first stage of the low noise amplifier.

The present invention has been made in view of such conventional problems, and an object of the present invention is to provide a variable gain amplifier which is small in size, has low noise, and is inexpensive.

[0006]

A variable gain amplifier according to a first aspect of the present invention comprises an amplification FET, an input matching circuit connected to the gate of the amplification FET, and an output connected to the drain of the amplification FET. A matching circuit is provided, and a variable resistor whose one end is grounded is connected between the drain of the amplification FET and the output matching circuit.

A variable gain amplifier according to a second aspect of the present invention comprises an amplifying FET, an input matching circuit connected to the gate of the amplifying FET, and an output matching circuit connected to the drain of the amplifying FET. A variable resistor whose one end is grounded is connected between the gate of the FET for use and the input matching circuit.

In the variable gain amplifier according to the third aspect of the present invention, the variable resistor is connected to the drain of a variable resistor FET whose source is grounded.

In the variable gain amplifier according to the fourth aspect of the invention, a resistor is connected in parallel between the source and drain of the variable resistance FET.

In the variable gain amplifier according to the fifth aspect of the invention, an inductance is connected in parallel between the source and drain of the variable resistance FET.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. FIG. 1 shows a variable gain amplifier according to the first embodiment. In the figure, 1 is an amplifying FET, 2 is an input matching circuit connected to the gate of the amplifying FET 1, 3 is an output matching circuit connected to the drain of the amplifying FET 1, and 4 is a source of the amplifying FET 1. The source inductance 5 is a variable resistance FET whose source is grounded and whose drain is connected between the drain of the amplification FET 1 and the output matching circuit 3.

Next, the operation of the variable gain amplifier of the first embodiment will be described. The loading of the inductance 4 on the source of the amplifying FET 1 is performed in order to stabilize the amplifier and bring the noise matching impedance and the reflection matching impedance close to each other. At this time, when the value of the inductance 4 is increased, a feedback circuit is formed between the drain and the gate, and a frequency band that can be stabilized and a frequency band that cannot be stabilized are generated due to the frequency characteristic of the inductance. Therefore, it is often difficult to realize stabilization only by loading the inductance 4 on the source, and in that case, it is necessary to load the drain or the gate with a resistor for stabilization. In the present embodiment, the variable resistance FET 5 serves as a resistance load for stabilization. When the value of the inductance 4 to be loaded on the source is determined, the range of the resistance value that can stabilize the amplifier is determined for that inductance value, and the optimum combination is usually selected for the required performance (noise figure, gain, etc.) of the amplifier. To be done. Here, with respect to the value of the determined inductance 4, the variable resistance FE is within a range of resistance value that can be stabilized.
When the resistance value of T5 is changed, the maximum available power gain of the amplifier is changed, and the gain of the amplifier can be changed. The maximum available power gain is a characteristic peculiar to the circuit used to represent the basic characteristics of the transistor, and is the power gain when the input and output of the transistor are matched. It is defined when the amplifier is stabilized (when the stability coefficient K ≧ 1), and the S
It is shown by the equation (1) from the parameters.

[0013]

[Equation 1]

Here, the stability coefficient K is expressed by equation (2).

[0015]

[Equation 2]

From equation (1), it can be seen that the S-parameter of the circuit changes as the resistance value of the variable resistance FET 5 changes, and the maximum available power gain changes as the value of the stability coefficient changes. When the resistance value of the variable resistance FET 5 is increased, the power consumed as heat by the resistance decreases,
The stability factor decreases and the gain increases. Conversely, when the resistance value of the variable resistance FET 5 is decreased, the power consumed by the resistance increases, so that the stability coefficient increases and the gain decreases.

According to this embodiment, the variable resistance FET 5 is used as the resistance for stabilizing the amplifier, and the variable resistance value is used to realize the variable gain. Since the dual gate FET is not used as in the conventional example, a highly accurate control voltage power supply and a temperature compensation circuit are unnecessary, and a variable gain amplifier with a simple configuration and a small size can be obtained at low cost. It also has a good noise figure and can be used in the first stage of a low noise amplifier.

Embodiment 2. FIG. 2 shows a variable gain amplifier according to the second embodiment. In the figure, 1 is an FET for amplification and 2 is
Is an input matching circuit connected to the gate of the amplifying FET1,
3 is an output matching circuit connected to the drain of the amplifying FET 1, 4 is a source inductance loaded to the source of the amplifying FET 1, 5 is grounded source, and a drain is provided between the gate of the amplifying FET 1 and the input matching circuit 2. It is a connected variable resistance FET.

The second embodiment is the same as the first embodiment, except that the amplification F
FET for variable resistance connected to the drain side of ET1
5 is connected to the gate side of the amplifying FET 1.
The operation of the variable resistance FET 5 is the same as that of the first embodiment, and the second embodiment can also perform the variable gain operation based on the same principle as that of the first embodiment.

Therefore, also in the present embodiment, as in the first embodiment, since the dual gate FET is not used, a variable gain amplifier having a simple structure, small size and low noise can be obtained at low cost.

Embodiment 3. FIG. 3 shows a variable gain amplifier according to the third embodiment. In the figure, 1 is an FET for amplification and 2 is
Is an input matching circuit connected to the gate of the amplifying FET1,
3 is an output matching circuit connected to the drain of the amplifying FET 1, 4 is a source inductance loaded to the source of the amplifying FET 1, 5 is grounded source, and a drain is connected between the drain of the amplifying FET 1 and the output matching circuit 3. The connected variable resistance FET 6 is a resistance connected in parallel between the source and drain of the variable resistance FET 5.

Next, the operation of the variable gain amplifier of the third embodiment will be described. The principle of variable gain is the same as in the first and second embodiments. Here, F for variable resistance
The operation of the variable resistance FET 5 and the resistance 6 in two cases of the ET 5 being in the OFF state and the ON state will be described with reference to FIG. The variable resistance FET 5 biases the drain and the source to the same potential, and turns on and off by the gate bias. FET5 for variable resistance is OFF
In the state, the variable resistance FET 5 is equivalently expressed by the capacitance 7. In this case, the variable resistance FET 5 has a high impedance, and the parallel circuit of the variable resistance FET 5 and the resistance 6 has substantially only the resistance value of the resistance 6. Variable resistance F
When ET5 is turned on, the variable resistance FET 5 is equivalently expressed by the resistance 8. At this time, a desired resistance value can be obtained by controlling the bias of the variable resistance FET 5 in the ON state. In the ON state, the resistance value of the parallel circuit of the variable resistance FET 5 and the resistance 6 becomes the parallel connection value of the resistance 6 and the equivalent resistance 8 of the variable resistance FET 5, and the resistance value becomes smaller than that in the case where the FET 6 is in the OFF state.
Therefore, the resistance value can be changed by turning the variable resistance FET 5 on and off, and the effect of changing the gain can be achieved. As for the value of the resistor 6, the variable resistor FET 5 is OF
The amplifier is set to the maximum value that can be stabilized in the F state. By setting the value of the resistor 6 in this manner, the amplifier is reliably stabilized even if the resistance value of the variable resistance FET 5 changes.

According to the present embodiment, the variable resistance FET
By connecting the resistor 6 in parallel between the source and drain of 5, it is possible to realize the variable gain by turning on and off the variable resistor FET 5 while ensuring the stabilization of the amplifier. By connecting the variable gain amplifiers in multiple stages and turning on and off the variable resistance FETs in each stage, digital gain control is also possible.

Further, although the case where the variable resistance FET 5 and the resistor 6 are connected to the drain side has been described in the present embodiment, the same effect can be obtained when the variable resistance FET 5 and the resistance 6 are connected to the gate side.

Fourth Embodiment FIG. 5 shows a variable gain amplifier according to the fourth embodiment. In the figure, 1 is an FET for amplification and 2 is
Is an input matching circuit connected to the gate of the amplifying FET1,
3 is an output matching circuit connected to the drain of the amplifying FET 1, 4 is a source inductance loaded to the source of the amplifying FET 1, 5 is grounded source, and a drain is connected between the drain of the amplifying FET 1 and the output matching circuit 3. Connected variable resistance FET, 6 is a resistance connected in parallel between the source and drain of variable resistance FET 5, and 9 is a variable resistance FET
This is an inductance connected in parallel between the source and drain of No. 5.

The operation of this embodiment is the same as that of the third embodiment. The present embodiment is particularly effective when the OFF-state capacitance 7 of the variable resistance FET 5 cannot be ignored when used at high frequencies.
Inductance 9 and variable resistor F connected in parallel with T5
This is to cancel the capacitance 7 of the ET 5 in the OFF state by causing them to resonate in parallel.

According to the present embodiment, the variable resistance FET
By connecting the inductance 9 between the source and drain of 5, it is possible to obtain a variable gain amplifier capable of varying the gain even at high frequencies.

Although the case where the variable resistance FET 5, the resistor 6 and the inductance 9 are connected to the drain side has been described in the present embodiment, the same effect can be obtained when the variable side FET 5 is connected to the gate side.

[0029]

According to the first or second aspect of the present invention, by using a variable resistor as the stabilizing resistor of the amplifier, the resistance value of the stabilizing resistor can be varied to realize variable gain, which is simple and easy. It is possible to obtain a variable gain amplifier which is small in size, has low noise, and is inexpensive.

According to the third aspect of the invention, the variable resistance is constituted by the variable resistance FET, so that a small-sized, low-noise and low-gain variable-gain amplifier can be obtained with a simple structure.

According to the fourth aspect of the invention, the variable resistance F
By connecting the ET and the resistor in parallel, the amplifier can be reliably stabilized, and the variable resistance FET can be turned ON / OFF to realize the variable gain.

According to the fifth aspect of the invention, the variable resistor F
By connecting an inductance in parallel with ET, a variable gain amplifier capable of varying the gain even at high frequencies can be obtained.

[Brief description of drawings]

FIG. 1 is a variable gain amplifier according to a first embodiment.

FIG. 2 is a variable gain amplifier according to a second embodiment.

FIG. 3 is a variable gain amplifier according to a third embodiment.

FIG. 4 is an operation explanatory diagram of a parallel circuit of a variable resistance FET and a resistance according to the third embodiment.

FIG. 5 shows a variable gain amplifier according to a fourth embodiment.

FIG. 6 is an example of a conventional variable gain amplifier using a dual gate FET.

[Explanation of symbols]

1. Amplification field effect transistor, 2. Input matching circuit,
3. Output matching circuit, 4. Source inductance, 5. Field effect transistor for variable resistance, 6. Resistance, 7. FET
5. OFF-state equivalent capacity of 8. Equivalent resistance of FET 6 in ON state, 9. Inductance, 10. Dual gate FET

Claims (5)

[Claims] 1. An amplifying field effect transistor, an input matching circuit connected to the gate of the amplifying field effect transistor, and an output matching circuit connected to the drain of the amplifying field effect transistor. A variable gain amplifier characterized in that a variable resistance whose one end is grounded is connected to the drain of a field effect transistor. 2. An amplifying field effect transistor, an input matching circuit connected to a gate of the amplifying field effect transistor, and an output matching circuit connected to a drain of the amplifying field effect transistor. A variable gain amplifier characterized in that a variable resistor whose one end is grounded is connected to the gate of a field effect transistor. 3. The variable gain amplifier according to claim 1, wherein the variable resistance is a variable resistance field effect transistor whose source is grounded. 4. The variable gain amplifier according to claim 3, wherein a resistor is connected in parallel between the source and the drain of the variable resistance field effect transistor. 5. The variable gain amplifier according to claim 4, wherein an inductance is connected in parallel between the source and the drain of the variable resistance field effect transistor.