JP2003142595A - Transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a switching transistor capable of performing a high-speed switching operation. SOLUTION: P type 1st, 2nd and 3rd base areas 18 to 20 are formed on an N type collector area 15. N type 1st, 2nd and 3rd emitter areas 21 to 23 are formed in the 1st, 2nd and 3rd base areas 18 to 20. The 1st base area 18 is electrically connected to the 2nd and 3rd emitter areas 22, 23. Consequently 1st and 2nd drive step transistors 12, 13 respectively composed of the 2nd and 3rd base areas 19, 20 and the 2nd and 3rd emitter areas 22, 23 and Darlington connected to a power step transistor composed of the collector area 15, the 1st base area 18 and the 1st emitter area 21 are constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor that uses Darlington-connected transistors and can be used as a power transistor or the like.

[0002]

2. Description of the Related Art As a power transistor, an audio amplifying transistor, and the like, a transistor in which a plurality of transistors are connected in a Darlington connection to increase a current amplification factor is used.

FIG. 6 shows a conventional power transistor 101.
The circuit diagram of is shown. As shown in FIG. 6, the power transistor 101 includes a drive stage transistor 102 and a power stage transistor 103, which are Darlington connected to each other.
And

FIG. 7 shows the power transistor 1 shown in FIG.
The element cross section of No. 01 is shown. As shown in FIG. 7, the power transistor 101 includes a collector contact region 105 that constitutes one surface of an N-type semiconductor substrate 104 and a semiconductor substrate 1.
Collector contact region 105, which constitutes the other surface 04
A collector region 106 made of an N-type semiconductor region having an impurity concentration lower than that of the first and second base regions 107, 108 made of a P-type semiconductor region formed in a surface region of the collector region 106; And first and second emitter regions 109, 1 made of N-type semiconductor regions formed in the second base regions 107, 108, respectively.
10 is provided.

The collector contact region 105 is electrically connected to the collector electrode 111 formed on one surface of the semiconductor substrate. The collector region 106 and the collector contact region 105 correspond to the drive stage transistor 102.
And the power stage transistor 103 function as a common collector.

The first base region 107 and the first emitter region 109 are electrically connected to the first base electrode 112 and the first emitter electrode 113 formed on the other surface of the semiconductor substrate 104, respectively. There is. A first base region 107, a first emitter region 109, a collector region 106 and a collector contact region 105,
The drive stage transistor 102 is constituted by

Second base region 108 and second emitter region 110 are electrically connected to second base electrode 114 and second emitter electrode 115, respectively, which are formed on the other surface of semiconductor substrate 104. There is. A second base region 108, a second emitter region 110, a collector region 106 and a collector contact region 105,
The power stage transistor 103 is constituted by.

The first emitter electrode 113 and the second base electrode 114 are electrically connected. This, drive stage transistor 102 and power stage transistor 10
Since 3 has a common collector, the drive stage transistor 102 and the power stage transistor 103 are in Darlington connection.

[0009]

In the power transistor 101 having the above structure, the minority carriers accumulated in the second base region 108 and the collector region 106 of the power stage transistor 103 at the time of transition from the ON state to the OFF state. Is faster than the drive stage transistor 102 (first base region 107) thereof, the faster the switching speed is, the better transistor characteristics are obtained.

Of the minority carriers accumulated in the second base region 108 and the collector region 106 constituting the power stage transistor 103, the drive stage transistor 1
Carriers accumulated on the side closer to 02 are extracted relatively quickly. However, the second base region 108 and the collector region 1 remote from the drive stage transistor 102
The carriers accumulated in 06 are relatively difficult to be pulled out.
As described above, since it takes a relatively long time to extract the carriers accumulated on the side far from the drive stage transistor 102, the switching speed of the entire power transistor 101 is reduced.

As described above, in the conventional transistor, it takes time to extract carriers from the power stage transistor, and it is difficult to obtain a sufficiently high switching speed. Therefore, there is a possibility that sufficiently high transistor characteristics cannot be obtained. It was

In view of the above circumstances, it is an object of the present invention to provide a transistor having good device characteristics. Another object of the present invention is to provide a transistor capable of high speed switching operation.

[0013]

In order to achieve the above object, the transistor according to the first aspect of the present invention is
A conductive type semiconductor substrate, a second conductive type first semiconductor region formed in a surface region of the semiconductor substrate, and a first conductive type second semiconductor region formed in the first semiconductor region. A first drive-stage transistor, a semiconductor substrate, a third semiconductor region of a second conductivity type formed in a surface region of the semiconductor substrate, and a third drive region formed in the third semiconductor region. A second drive stage transistor including a fourth semiconductor region of the first conductivity type, the semiconductor substrate, and the first semiconductor region and the third semiconductor in a surface region of the semiconductor substrate. A fifth semiconductor region of the second conductivity type formed so as to be sandwiched between both regions, and a sixth semiconductor region of the first conductivity type formed in the fifth semiconductor region. , The first drive stage transistor and And a power stage transistors Darlington-connected to at least one of the fine the second drive stage transistor, characterized in that.

According to the transistor of the first aspect of the above structure, the minority carriers accumulated in the fifth semiconductor region of the power stage transistor when the transistor is off are
It can be easily pulled out in a short time through the adjacent first and second drive stage transistors. This provides a transistor having a high switching speed and good device characteristics.

In the transistor having the above structure, it is preferable that the first semiconductor region and the third semiconductor region are formed at substantially the same distance from the fifth semiconductor region.

In the transistor having the above structure, it is desirable that the second semiconductor region and the fourth semiconductor region are formed substantially equidistant from the sixth semiconductor region.

In the transistor having the above structure, for example, the fifth semiconductor region is formed in a stripe shape,
For example, the first semiconductor region and the third semiconductor region are formed in a stripe shape parallel to the fifth semiconductor region.

In the transistor having the above structure, a plurality of the sixth semiconductor regions may be formed in the fifth semiconductor region. At this time, the number of the sixth semiconductor regions is, for example, 1 or more and 10 or less in the fifth semiconductor region.

To achieve the above object, a transistor according to a second aspect of the present invention is a semiconductor substrate of a first conductivity type that constitutes a collector region, and a second conductivity type formed in a surface region of the semiconductor substrate. A first drive stage transistor including a first base region of the first base region and a first conductivity type first emitter region formed in the first base region, and the semiconductor forming the collector region. A substrate and a second conductivity type second formed on a surface region of the semiconductor substrate;
Second drive stage transistor including a base region of the second base region and a second emitter region of the first conductivity type formed in the second base region, the semiconductor substrate, and the surface of the semiconductor substrate. A third base region of the second conductivity type formed so as to be sandwiched between both the first base region and the second base region, and a third base region formed in the third base region. A third emitter region of one conductivity type,
And a power stage transistor Darlington-connected to at least one of the first drive stage transistor and the second drive stage transistor.

According to the transistor of the second aspect having the above structure, the minority carriers accumulated in the third base region of the power stage transistor when the transistor is off are:
It can be easily pulled out in a short time through the adjacent first and second drive stage transistors. This provides a transistor having a high switching speed and good device characteristics.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Transistors according to embodiments of the present invention will be described below with reference to the drawings. In this embodiment, a transistor such as a power transistor including a plurality of Darlington-connected transistors will be described as an example.

FIG. 1 shows a circuit diagram of the transistor 11 according to this embodiment. 2 shows a structure of the transistor 11 shown in FIG. As shown in FIG. 1, the transistor 11 includes first and second drive stage transistors 12 and 13, and a power stage transistor 14.

The first and second drive stage transistors 12, 13 have a common emitter, collector and base.

The base of the power stage transistor 14 is connected to the common emitter of the first and second drive stage transistors 12, 13. In addition, its collector is connected to the first and second drive stage transistors 12, 1
3 connected to a common collector. In this way, the first and second drive stage transistors 12, 1
3 and the power stage transistor 14 are respectively Darlington connected.

FIG. 2 shows a structural example of the transistor 11 of the present embodiment shown in FIG. As shown in FIG. 2, the transistor 11 of the present embodiment includes a collector region 15 and a collector contact region 16. Collector area 15
Are composed of N-type semiconductor regions formed on the semiconductor substrate 17. The collector contact region 16 is composed of an N-type semiconductor region having a higher impurity concentration than the collector region 15.

Collector contact region 16 is formed by diffusing N-type impurities into an N-type silicon single crystal substrate. Alternatively, the collector contact region 16
May be formed as an N-type epitaxial growth layer on the N-type semiconductor substrate 17. Collector contact area 1
6 functions as a common collector region 15 for the first and second drive stage transistors 12 and 13 and the power stage transistor 14 together with the collector region 15.

In the surface region of the collector region 15, first, second and third base regions 18, 19, 20 which are P type semiconductor regions are formed. Also, the first and second
And inside the third base regions 18, 19, 20:
First, second and third emitter regions 21, 22 and 23 formed of N-type semiconductor regions are formed.

First, second and third base regions 18,
19 and 20 are formed by diffusing P-type impurities into the exposed surface of the N-type semiconductor region forming the collector region 15. First, second and third base regions 18, 1
9 and 20 are formed in an island shape in the collector region 15 so as to be separated from each other.

The semiconductor substrate 17 is formed in a rectangular shape as shown in FIG. The first base region 18 is provided, for example, substantially in the center of the semiconductor substrate 17, and the second and third base regions 19 and 20 are provided so as to face each other with the first base region 18 interposed therebetween. ing.
First, second and third base regions 18, 19, 20
Are provided at substantially equal intervals from each other.

The first base region 18 functions as the base region of the power stage transistor 14. The second and third base regions 19 and 20 function as the base regions of the first and second drive stage transistors 12 and 13, respectively.

First, second and third emitter regions 2
1, 22, 23 are formed by diffusing N-type impurities into the surface regions of the first, second and third base regions 18, 19, 20 of the semiconductor substrate 17, respectively.
First, second and third emitter regions 21, 22, 23
As shown in FIG. 3, are formed in stripes along the first, second and third base regions 18, 19, 20 substantially in parallel.

The first emitter region 21 is arranged substantially at the center of the first base region 18. The second and third emitter regions 22 and 23 are arranged slightly closer to the center of the second and third base regions 19 and 20, respectively. Second emitter region 22 and first emitter region 21
The distance between and is set to be substantially the same as the distance between the third emitter region 23 and the first emitter region 21, for example.

The first emitter region 21 functions as the emitter region of the power stage transistor 14. The second and third emitter regions 22 and 23 function as the emitter regions of the first and second drive stage transistors 12 and 13, respectively.

On the first base region 18, first and second power stage transistor base electrodes 24 and 25 are provided and electrically connected. The base electrodes 24 and 25 for the first and second power stage transistors are
Are provided on the surface regions of the first base region 18 on both sides of the emitter region 21. First and second drive-stage transistor base electrodes 26 and 27 are provided on and electrically connected to the second and third base regions 19 and 20, respectively.

A power stage transistor emitter electrode 28 is provided on the first emitter region 21 and is electrically connected thereto. Second and third emitter regions 22,
First and second drive-stage transistor emitter electrodes 29 and 30 are provided on 23, respectively, and are electrically connected to each other.

The first power stage transistor base electrode 24 and the first drive stage transistor emitter electrode 29 are electrically connected to each other by a first connection conductor 31. Further, the second power stage transistor base electrode 25 and the second drive stage transistor emitter electrode 30 are electrically connected to each other by the second connection conductor 32. The first and second connection conductors are formed on one surface of the semiconductor substrate 17 with the insulating film 33 interposed therebetween. A collector electrode 34 is formed on the other surface of the semiconductor substrate 17 (on the collector contact region 16).

In the transistor 11 shown in FIG. 2, a collector contact region 16 and a collector region 15,
A first base region 18, a first emitter region 21,
The power stage transistor 14 is constituted by.
Further, the collector contact region 16 and the collector region 15, the second base region 19, and the second emitter region 22 form the first drive stage transistor 12. Further, the collector contact region 16 and the collector region 15, the third base region 20, and the third emitter region 23 form a second drive stage transistor 13. As a result, the transistor 11 has a structure in which the first drive stage transistor 12 and the second drive stage transistor 13 are arranged on both sides of the power stage transistor 14.

As described above, since the power stage transistor 14 is formed by sandwiching the first and second drive stage transistors 12 and 13, minority carriers (in particular, holes) accumulated in the power stage transistor 14 are generated. , The first and second drive stage transistors 12, 1 easily
It becomes possible to be pulled out to the 3 side.

That is, the minority carriers (electrons) accumulated in the first base region 18 of the power stage transistor 14
Are recombined with holes in the first base region 18 and disappear, or are extracted to the collector electrode 34. At the same time, the minority carriers (holes) accumulated in the collector region 15 are easily extracted by the closer one of the second and third base regions 19 and 20 arranged with the first base region 18 in between. obtain.

In this way, the power stage transistor 1
The minority carriers accumulated in the first base region 18 and the collector region 15 of No. 4 can be extracted in a relatively short time through the two adjacent first and second drive stage transistors 12 and 13. As a result, the transistor 11 of the present embodiment can obtain a high switching speed.

As described above, according to the transistor of the present invention in which the first and second drive stage transistors 12 and 13 are arranged on both sides of the power stage transistor 14, respectively, the power stage transistor 14 is stored. Minority carriers can be easily extracted through the first and second drive stage transistors 12 and 13. As a result, a transistor capable of high-speed switching operation can be obtained.

The present invention is not limited to the above embodiment, but various modifications and applications are possible. Hereinafter, modifications of the above-described embodiment applicable to the present invention will be described.

In the above-described embodiment, the semiconductor substrate 17 is rectangular and each semiconductor region is formed in a stripe shape. However, the shape of the semiconductor substrate 17 is not limited to this, and may be any shape such as a circle or a polygon. Further, each semiconductor region may be formed in a shape such as a lattice. Further, in addition to the configuration in which one power stage transistor is sandwiched between two drive stage transistors, a configuration in which one power stage transistor is sandwiched between three or more, for example, four drive stage transistors is also possible.

In the transistor 11, the first and second drive stage transistors 12 and 13 are arranged on both sides of one power stage transistor 14. However, it is also possible to arrange the drive stage transistors on both sides of a multi-emitter type power stage transistor having a plurality of emitter regions. Here, the larger the number of emitter regions in the base region, the lower the extraction rate of minority carriers in the entire power stage transistor. Therefore, the number of emitter regions to be arranged is 1 or more and 10 or less, and preferably 1 or more and 6 or less.

FIG. 4 shows a structural example of the transistor 11 having three emitter regions 21a. In the transistor 11 shown in FIG. 4, the base region 18 of the power stage transistor 14 is formed as a single P-type semiconductor region, and three emitter regions 21 a are formed in this single base region 18.

Further, as shown in FIG. 5, a configuration in which drive stage transistors and power stage transistors are alternately arranged is also possible. Also in the configuration shown in FIG. 5, the drive stage transistor 35 is provided on both sides of the power stage transistor 14.
, And the minority carriers stored in the power stage transistor 14, in particular in the collector region, can easily be extracted in a short time via the adjacent drive stage transistor 35.

Further, in the above embodiment, the NPN type bipolar transistor is used. But,
A PNP type transistor may be used by configuring as a reverse conductivity type. Further, a field effect transistor may be used as the drive stage transistor and / or the power stage transistor.

In the above embodiment, the power transistor is described as an example, but the present invention can be applied to other transistors such as an audio amplifying transistor using a Darlington connected transistor.

[0049]

As described above, according to the present invention,
A transistor having good device characteristics is provided.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a transistor according to an exemplary embodiment of the present invention.

FIG. 2 is a diagram showing a cross-sectional configuration of a transistor according to the present embodiment.

FIG. 3 is a top view of the semiconductor substrate shown in FIG.

FIG. 4 is a diagram showing a cross-sectional structure of a transistor according to another embodiment of the present invention.

FIG. 5 is a diagram showing a cross-sectional configuration of a transistor according to another embodiment of the present invention.

FIG. 6 shows a circuit diagram of a conventional power transistor.

7 shows a cross-sectional structure of the power transistor shown in FIG.

[Explanation of symbols]

11 transistors 12 First drive stage transistor 13 Second drive stage transistor 14 power stage transistors 15 Collector area 16 Collector contact area 17 Semiconductor substrate 18 First Base Area 19 Second Base Area 20 Third Base Area 21 First Emitter Region 22 Second emitter region 23 Third Emitter Region

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5F003 AP00 BE09 BJ02                 5F064 CC02 CC30 DD01 DD31                 5F082 AA06 AA11 AA13 BA26 BA33                       BA48 BC03 DA02 FA02 GA02                       GA04

Claims (7)

[Claims] 1. A semiconductor substrate of a first conductivity type, a first semiconductor region of a second conductivity type formed in a surface region of the semiconductor substrate, and a first conductivity formed in the first semiconductor region. A second drive region transistor formed of a second type semiconductor region, a semiconductor substrate, a third semiconductor region of a second conductivity type formed in a surface region of the semiconductor substrate, A second drive stage transistor formed of a fourth semiconductor region of the first conductivity type formed in the third semiconductor region, the semiconductor substrate, and the first semiconductor in a surface region of the semiconductor substrate. A fifth semiconductor region of the second conductivity type formed so as to be sandwiched between both the region and the third semiconductor region, and a sixth semiconductor region of the first conductivity type formed in the fifth semiconductor region. A semiconductor region, and the first dry Stage transistor and the comprises a power stage transistors Darlington-connected to at least one of the second drive stage transistor, a transistor, characterized in that. 2. The first semiconductor region and the third semiconductor region are formed at substantially the same distance from the fifth semiconductor region, as claimed in claim 1. Transistor. 3. The second semiconductor region and the fourth semiconductor region are formed at substantially the same distance from the sixth semiconductor region, according to claim 1 or 2. The described transistor. 4. The fifth semiconductor region is formed in a stripe shape, and the first semiconductor region and the third semiconductor region are formed in a stripe shape parallel to the fifth semiconductor region. The transistor according to any one of claims 1 to 3, wherein: 5. The transistor according to claim 1, wherein a plurality of the sixth semiconductor regions are formed in the fifth semiconductor region. 6. The transistor according to claim 5, wherein one or more and ten or less of the sixth semiconductor regions are formed in the fifth semiconductor region. 7. A semiconductor substrate of a first conductivity type that constitutes a collector region, and a second substrate formed on a surface region of the semiconductor substrate.
A first drive stage transistor composed of a conductive type first base region and a first conductive type first emitter region formed in the first base region, and a collector region A semiconductor substrate, a second conductive type second base region formed in a surface region of the semiconductor substrate, and a first conductive type second emitter region formed in the second base region, A second drive stage transistor including: a semiconductor substrate; and a second substrate formed in a surface region of the semiconductor substrate so as to be sandwiched between both the first base region and the second base region. A third base region of conductivity type and a third emitter region of first conductivity type formed in the third base region, wherein the first drive stage transistor and the second drive Stage transition It comprises a power stage transistors Darlington-connected to at least one of data, a transistor, characterized in that.