JP2010219454A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor which achieve increase in the SOA (safe operating area) and favorable static property at the same time. <P>SOLUTION: A semiconductor device has: a collector layer (2) of a first conductivity type; a base layer (3) of a second conductivity type which is formed on the collector layer (2); an emitter layer (4) of the first conductivity type which is formed on the base layer (3) like islands; base contacts (11') through which the base layer (3) and base electrodes (11) are electrically connected; and emitter contacts (12') through which the emitter layer (4) and emitter electrodes (12) are electrically connected. The semiconductor device is further provided with trenches (6) which are formed between the base contacts (11') and the emitter contacts (12') in plan view. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a transistor structure and a semiconductor device in which semiconductor elements including transistors are integrated.

One of the performance indicators of a transistor applied to a power supply circuit or the like as a power semiconductor element is a specification item called a safe operating area SOA (Safe Operating Area). The SOA is an area showing allowable values of current and voltage that allow the transistor to operate normally without failure such as element destruction, and the power supply circuit using the transistor operates so that the transistor operates within the area indicated by the SOA. It is necessary to provide an external circuit. That is, expanding the SOA is one of means for improving the reliability of the transistor and simplifying the power supply circuit.

As a method of expanding the SOA, a method of providing a ballast resistor between the base region and the emitter region is known. As a conventional method of providing a ballast resistor, for example, a method of forming a region called a floating emitter in the base region and a method of forming a low impurity concentration region in a current path between the base region and the emitter region are disclosed. (Patent Document 1).

By forming the ballast resistor in this way, the base current flowing from the base region to the emitter region can be limited, current concentration at the emitter contact can be prevented, and the SOA can be enlarged.

JP 2000-216166 A

By the way, the floating emitter that forms the ballast resistor is an ineffective region that is not directly involved in the transistor operation. By forming the floating emitter, the effective area of the emitter is reduced, and the static capacitance of the transistor such as hFE (current amplification factor) characteristics is reduced. There was a problem that the characteristics deteriorated. Further, since the ballast resistor in the method of Patent Document 1 is formed by lateral diffusion of impurities, the effective area of the emitter is similarly reduced, and it is difficult to control the resistance value of the ballast resistor. there were. That is, SOA expansion and transistor characteristics are in a trade-off relationship, and it is difficult to achieve both.

The present invention has been made to solve the above problems. Accordingly, the present invention is to provide a transistor that simultaneously achieves SOA expansion and good static characteristics.

In order to solve the above problems and achieve the above object, a transistor of the present invention includes a first conductivity type collector layer, a second conductivity type base layer formed on the collector layer, and a base layer. An emitter layer of a first conductivity type formed in an island shape; a base contact electrically connected to the base layer and the base electrode; and an emitter contact electrically connected to the emitter layer and the emitter electrode; A semiconductor device comprising:
A trench is formed between the base contact and the emitter contact in plan view.

In order to solve the above problems and achieve the above object, a method for manufacturing a transistor of the present invention includes a step of forming a second conductivity type base layer on a first conductivity type collector layer, Forming a first conductivity type emitter layer in an island shape, forming a base contact electrically connecting the base layer and the base electrode, and electrically connecting the emitter layer and the emitter electrode. Forming a connected emitter contact, and a method of manufacturing a semiconductor device comprising:
A step of forming a trench between the base contact and the emitter contact in plan view is provided.

According to the above configuration, it is possible to provide a transistor that simultaneously achieves SOA expansion and good static characteristics.

It is a figure which shows the cross-section of the transistor which concerns on Example 1 of this invention. It is a figure which shows the planar structure of the transistor which concerns on Example 1 of this invention. It is a figure which shows the manufacturing method of the transistor which concerns on Example 1 of this invention. It is a figure which shows the cross-section of the transistor which concerns on Example 2 of this invention.

Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

1 and 2 are a sectional view and a plan view showing the structure of a transistor according to a first embodiment of the present invention.

The transistor according to this embodiment includes an n + conductivity type substrate 1, an n− conductivity type collector layer 2 formed on the substrate 1, and a p conductivity type base layer formed on the collector layer 2. 3 and an n + conductivity type emitter layer 4 formed in an island shape on the base layer 3.

Further, the transistor according to this embodiment includes an oxide film 5 formed on the base layer 3 and the emitter layer 4 and having a predetermined opening, a plurality of trenches 6 extending from the surface of the base layer 3 toward the inside, and a plurality of trenches 6. A trench oxide film 7 (electric resistance region) formed in the trench 6, a base electrode 11 electrically connected to the base layer 3, an emitter electrode 12 electrically connected to the emitter layer 4, and a collector layer 2 And a collector electrode 13 electrically connected to.

In the transistor according to the present embodiment, a base contact 11 ′ that is a junction between the base layer 3 and the base electrode 11, an emitter contact 12 ′ that is a junction between the emitter layer 4 and the emitter electrode 12, and the trench oxide film 7 are As shown in FIGS. 2A to 2C, they are arranged in stripes or dots as viewed in a plan view. In other words, the trench 6 is disposed between the base contact 11 ′ and the emitter contact 12 ′ in plan view. According to such a configuration, the base layer 3 sandwiched between the trenches 6 functions as a resistance region (ballast resistor).

FIG. 3 is a process sectional view showing a method of manufacturing a transistor according to the first embodiment of the present invention.

First, a substrate 1 having n + conductivity type is prepared, a collector layer 2 having n− conductivity type is epitaxially grown on the substrate 1, p-type impurities such as boron are diffused from the surface of the collector layer 2, and the p conductivity type is increased. The base layer 3 is formed (FIG. 3A).

Next, a mask 20 having a predetermined opening is formed on the collector layer 2 and the base layer 3, and a trench 6 is formed by anisotropic etching such as reactive ion etching (RIE) (FIG. 3B). . The mask 20 can be formed by patterning an oxide film by, for example, well-known photolithography.

Next, in order to remove the damage caused by the anisotropic etching, a sacrificial oxide film is formed in the trench 6, and after removing the sacrificial oxide film and the mask 20 by wet etching, a thermal oxidation process is performed to form the oxide film 5 and A trench oxide film 7 is formed (FIG. 3C). The oxide film 5 and the trench oxide film 7 can also be formed by a chemical vapor deposition (CVD) method or the like. Further, the step of forming the sacrificial oxide film and the step of removing the sacrificial oxide film and the mask 20 can be omitted.

Next, a predetermined opening is formed in the oxide film 5 by well-known photolithography, and an n-type impurity such as phosphorus is diffused from the opening into the base layer 3 to form an emitter layer 4 having an n + conductivity type ( FIG. 3 (d)).

Then, a predetermined opening is formed in the oxide film 5 by well-known photolithography, and a base electrode 11, an emitter electrode 12, and a collector electrode 13 made of aluminum are formed by, for example, a sputtering process (FIG. 3E).

In the transistor manufacturing method according to the present embodiment, the trench 6 and the trench oxide film 7 can be formed after the step of forming the emitter layer 4.

The transistor according to this example has the following effects.
(1) Since the base layer 3 sandwiched between the trenches 6 functions as a ballast resistor, the safe operation area SOA (Safe Operating Area) of the transistor can be expanded.
(2) Since the ballast resistor can be formed in the depth direction of the base layer 3, the ineffective region can be greatly reduced as compared with the conventional transistor, and the effective area of the emitter can be increased. Therefore, it can suppress that the static characteristic of a transistor falls.
(3) Since the ballast resistor can be formed in the depth direction of the base layer 3, the transistor cells can be highly integrated and the chip area can be reduced.
(4) Since the resistance value of the ballast resistor can be adjusted by the distance and the depth of the trench 6, a desired ballast resistor can be formed with higher precision than in the conventional transistor method.

FIG. 4 is a sectional view showing the structure of a transistor according to the second embodiment of the present invention.

The transistor according to the second embodiment of the present invention is substantially the same as the transistor according to the first embodiment except that the modified emitter layer 4 ′ and the trench 6 ′ are formed. The deformed emitter layer 4 ′ is adjacent to the trench 6 ′ by lateral diffusion of n-type impurities in the step of forming the emitter layer 4 of the first embodiment. The trench 6 ′ is formed deeper than the emitter layer 4 ′.

The transistor according to the present example is manufactured by the same manufacturing method as that of the transistor according to the first example. The trench 6 ′ and the trench oxide film 7 are formed by the step of forming the base layer 3 and the step of forming the emitter layer 4 ′. It is obtained by forming between.

The transistor according to the present embodiment has the following effects in addition to the same effects as the transistor according to the first embodiment.
(1) Since the junction surface between the base layer 3 and the emitter layer 4 ′ is not exposed on the surface of the transistor, the hFE (current amplification factor) characteristics and the base can be obtained even when a conductive material or charge adheres to the surface of the transistor.・ Effects of breakdown voltage between emitters can be reduced.
(2) Since the trench 6 ′ is formed deeper than the emitter layer 4 ′, it is possible to reliably suppress the diffusion of the emitter layer 4 ′ toward the base contact 11 ′.
(3) Since the step of forming the trench 6 ′ and the trench oxide film 7 is performed between the step of forming the base layer 3 and the step of forming the emitter layer 4 ′, the lateral diffusion of the emitter layer 4 ′ is performed in the trench. Stop at 6 '. Therefore, there is no need to consider the lateral extension of the emitter layer 4 ', and the transistor cells can be highly integrated.

Although an example of the embodiment of the present invention has been described above, the present invention is not limited to the specific embodiment, and various modifications can be made within the scope of the gist of the present invention described in the claims. Can be changed. For example, instead of the trench oxide film 7, a semi-insulating material such as a low concentration semiconductor layer or metal oxide may be applied as the resistance region of the present invention. Although an npn transistor has been described as an embodiment of the present invention, the structure and manufacturing method of the present invention can be applied to a pnp transistor.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Collector layer 3 Base layer 4, 4 'Emitter layer 5 Oxide film 6, 6' Trench 7 Trench oxide film 11 Base electrode 12 Emitter electrode 13 Collector electrode

Claims (6)

A collector layer of a first conductivity type, a base layer of a second conductivity type formed on the collector layer, an emitter layer of a first conductivity type formed in an island shape on the base layer, and the base layer A semiconductor device having a base contact when the base electrode is electrically connected, and an emitter contact where the emitter layer and the emitter electrode are electrically connected,
A semiconductor device comprising a trench formed between the base contact and the emitter contact in plan view.
The semiconductor device according to claim 1, further comprising an electric resistance region formed inside the trench.
The semiconductor device according to claim 1, wherein the emitter layer is formed adjacent to the trench.
4. The semiconductor device according to claim 2, wherein the electrical resistance region is formed of an oxide.
Forming a second conductivity type base layer on the first conductivity type collector layer; forming a first conductivity type emitter layer in an island shape on the base layer; and the base layer and the base electrode; A method of manufacturing a semiconductor device, comprising: a step of forming a base contact when electrically connected to each other; and a step of forming an emitter contact to which the emitter layer and the emitter electrode are electrically connected,
A method of manufacturing a semiconductor device, comprising: a step of forming a trench between the base contact and the emitter contact in plan view.
The method of manufacturing a semiconductor device, wherein the step of forming the trench is performed between the step of forming the base layer and the step of forming the emitter layer in an island shape.

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