JP3249032B2 - Compound semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to communication equipment, and
The present invention relates to a compound semiconductor device used for a high-frequency circuit of the HF band or higher.

[0002]

2. Description of the Related Art In recent years, a compound semiconductor device formed on a compound semiconductor substrate has attracted attention as a semiconductor device used for a high-frequency circuit of communication equipment.

Hereinafter, a conventional compound semiconductor device will be described. FIG. 10 is a perspective view schematically showing a conventional compound semiconductor device. In the figure, reference numeral 2 denotes a compound semiconductor substrate, reference numeral 18 denotes an N-type semiconductor region, and reference numeral 19 denotes a P-type semiconductor region.
Reference numeral 20 denotes an ohmic electrode to the N-type semiconductor region 18, and reference numeral 21 denotes an ohmic electrode to the P-type semiconductor region 19. Assuming that the length of the long side and the short side of the N-type semiconductor region 18 are a and b, respectively, when the semiconductor device is viewed from the surface, the area S of the N-type semiconductor region 18 is ab, and the peripheral length L is 2 a + b). Therefore, the ratio L / S of the peripheral length L to the area S is 2 (1 / a +
1 / b).

Here, the short side b of the N-type semiconductor region 18 is made to have a very small rectangular shape, and 1 / b is increased so that the ratio L
It is known that the value of / S is set to a relatively large value. That is, in the case of a semiconductor device having a small ratio L / S, when a forward bias is applied to the PN junction, the current becomes N
Since it does not flow to the central portion of the N-type semiconductor region 18 but flows only to the peripheral portion of the N-type semiconductor region 18,
The central part simply acts as a parasitic capacitance. However, by miniaturizing the short side of the N-type semiconductor region 18, the center portion is narrowed, so that the injection current flows efficiently through the entire N-type semiconductor region 18. As a result, the central portion of the N-type semiconductor region 18 functions not as a mere parasitic capacitance but as an intrinsic region of the semiconductor device, so that high-frequency characteristics can be realized. The order of the N-type semiconductor region 18 and the P-type semiconductor region 19 may be reversed.
May have a rectangular shape.

[0005]

However, when the ratio L / S between the short side and the long side of the N-type semiconductor region 18 in the conventional compound semiconductor device is increased, for example, the emitter injection efficiency in a bipolar transistor is increased. The phenomenon was observed that the temperature decreased. As a result of conducting an experiment to determine the cause, a decrease in the injection efficiency and an increase in the N-type semiconductor region 1 were observed.
It was found that the relationship between the orientation of each side of No. 8 and each side was very large. For example, in a bipolar semiconductor device using a heterojunction, when the long side direction of the rectangular N-type semiconductor region 18 is [01-1], the relationship between the base current density and L / S is represented by a broken line in FIG. It changes along the characteristic line shown. That is, as the ratio L / S increases, the base current density increases. The cause is presumed to be the following phenomenon.

[0006] Minority carriers injected from one of the two semiconductor regions forming the PN junction into the other diffuse into the region having a low carrier concentration in the other semiconductor region. It recombine and disappear at the surface level of the surface region of the region. As described above, when one of the two regions forming the PN junction is miniaturized and the ratio L / S of the peripheral length L to the area S is increased in order to reduce the center portion and obtain high-frequency characteristics, The crystallographic orientation in the long side direction coincides with the direction in which piezo charges are likely to be generated by stress in the other semiconductor region, and the piezo charges may cause minority carriers to move to the surface region. In such a case, the minority carriers that have moved to the surface region are apt to recombine at the surface level, so that the recombination current is dominant and the injection efficiency is extremely reduced.

However, conventionally, in a GaAs device having, for example, a (100) plane as a main surface, since a cleavage plane is a {011} plane, a crystal is scribed along the {011} plane to take out a rectangular chip. It is common to do so. In this case, the direction of the long side direction of the rectangular PN junction is often [01-1], and if this direction coincides with the direction in which minority carriers are likely to be moved to the surface region, the injection efficiency is deteriorated. become.

Further, such a phenomenon that the injection efficiency is reduced generally occurs when a rectangular member having extremely different short side lengths and long side lengths is mounted on a compound semiconductor substrate. In addition, it has been found that even when a region made of a different kind of semiconductor material is provided, even if it does not necessarily have a rectangular member, if a piezo charge is generated at the boundary surface, it can occur. .

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to control the movement direction of minority carriers by piezo charges in a semiconductor region, so that carriers in the semiconductor region recombine at surface levels. An object of the present invention is to provide a compound semiconductor device capable of realizing high injection efficiency by taking measures for reducing the probability of performing the injection.

[0010]

Means for Solving the Problems To achieve the above object, a solution taken by the present invention is that a direction of minority carrier diffusion is affected by piezo charges in a semiconductor region, so that carriers in the semiconductor region have a surface level. The purpose is to reduce the probability of recombination with the position.

A first compound semiconductor device according to the present invention is:
As described in claim 1, a first semiconductor region in which minority carriers diffuse and move on a part of a compound semiconductor substrate having a (100) plane as a main surface, and a first semiconductor region formed on the first semiconductor region.
A second half having a lattice constant different from that of the first semiconductor region;
In the compound semiconductor device having a conductive region, said first
(2) The semiconductor region has a planar shape of a right-angled quadrilateral,
, The direction of the long side or short side almost generates piezo charge
To match the crystallographic orientation of the first semiconductor region not to be
It is formed in.

With this configuration, one of the two parallel sides of the second semiconductor region has the [010] direction, and the other group has the [001] direction. Even if stress is the [010] direction or the [001] in a plane perpendicular to the direction from said second semiconductor region and the surrounding member first semiconductor region of the first semiconductor region, the first semiconductor <br/> Piezoelectric charge hardly occurs in the region due to the stress. Therefore, the minority carriers injected into the first semiconductor region diffuse and move without being guided to the surface region side by the influence of the piezo charge. That is, it is possible to suppress a decrease in the injection efficiency due to the recombination of the minority carriers injected into the first semiconductor region with the surface states.

[0013] As described in claim 2, the second half
The conductor region is formed by forming the long side or the short side of the rectangular
Formed so as to be parallel to the [010] direction of the semiconductor substrate
Preferably.

[0014] As described 請 Motomeko 3, the first half
The conductor region is formed of a first conductivity type semiconductor having a surface parallel to the (100) plane, and the second semiconductor region is formed of the first semiconductor .
The second conductivity type semiconductor can be formed so as to form a rectangular PN junction with the semiconductor region.

According to this structure, the PN is transferred from the second semiconductor region.
The minority carriers injected into the first semiconductor region via the junction are prevented from diffusing into the surface region due to the influence of the piezo charge, and a decrease in the minority carrier injection efficiency is suppressed.

[0016] The second region, as described in claim 4, it is preferable that the short sides of the right angles quadrilateral is formed in miniaturized rectangular.

With this configuration, the ratio of the central portion serving as the parasitic capacitance of the compound semiconductor device becomes extremely small, so that the high-frequency characteristics are significantly improved and the decrease in the injection efficiency is suppressed.

Further, as described in claim 5, the upper title compound semiconductor device is a bipolar transistor, said first semiconductor region as a base region of the bipolar transistor, the emitter of the bipolar transistor said second semiconductor region The collector region of the bipolar transistor may be formed below the base region.

According to this configuration, the minority carriers injected from the emitter region of the bipolar transistor into the base region are prevented from diffusing into the surface region due to the piezo charge in the base region. Therefore, a decrease in emitter injection efficiency is suppressed.

[0020] As described 請 Motomeko 6, and the compound semiconductor device with a bipolar transistor, the first half
The structure may be such that a conductor region is a base region of the bipolar transistor, the second semiconductor region is a collector region of the bipolar transistor, and an emitter region of the bipolar transistor is formed below the base region.

According to this structure, the generation of piezo charges is suppressed in the base region in contact with the collector region, so that the probability that minority carriers injected from the emitter region into the base region recombine at the surface level is reduced, A decrease in emitter injection efficiency is suppressed.

[0022] As described 請 Motomeko 7, the second half
The conductor region may be constituted by an electrode that contacts the first semiconductor region.

With this configuration, the first semiconductor directly under the electrode member is provided.
In the body region, a decrease in the minority carrier injection efficiency is suppressed.

According to a second compound semiconductor device of the present invention,
As described in claim 8, (1) of the compound semiconductor substrate
The first semiconductor regions having different lattice constants from each other on the (00) plane.
Forming a region and a second semiconductor region, wherein the first semiconductor region
Having a PN junction where the second semiconductor region and the second semiconductor region are in contact with each other
In the compound semiconductor device, the PN junction is formed in a plane
The shape consists of two long sides and two short sides that are orthogonal to each other.
And the long side or short side of the PN junction is
Parallel to the [010] direction of the compound semiconductor substrate,
In addition, the direction of the long side or the short side almost generates piezo charge
The crystallographic orientation of the first semiconductor region not generated
It is formed as follows.

With this configuration, one of the two parallel sides of the right-angled quadrilateral PN junction has a direction of [01].
The direction of the other set coincides with the [001] direction in the [0] direction. Therefore, even if a stress due to a strain or the like generated between the first region and the second region forming the PN junction occurs in any of the semiconductor regions, the piezo caused by the stress acting on the PN junction is generated. Because the generation of electric charge is suppressed,
Minority carriers injected into any of the regions via the PN junction can be diffused without being affected by the piezo charge, and the diffusion toward the surface region is suppressed.
Therefore, a decrease in the injection efficiency due to the recombination of the minority carriers at the surface level is suppressed.

[0026] As described 請 Motomeko 9, the shape of the PN junction, a short side can be miniaturized rectangular.

With this configuration, the parasitic capacitance at the PN junction is reduced, high frequency characteristics can be obtained, and a decrease in injection efficiency due to recombination of minority carriers with the surface level can be suppressed. .

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view schematically showing a crystallographic orientation relationship between a semiconductor substrate and a cathode region of the compound semiconductor device according to the first embodiment. In the figure,
Reference numeral 1 denotes a cathode region (P diode of a diode) which is a second rectangular region having a planar shape including a long side and an extremely small short side.
Reference numeral 2 denotes a compound semiconductor substrate, reference numeral 3 denotes a (100) plane of the compound semiconductor substrate 2, reference numeral 4 denotes a (0-1-1) plane of the compound semiconductor substrate 2, reference numeral 5 denotes a compound semiconductor. The (01-1) plane of the substrate 2 is shown. As shown in the figure, the cathode region 1 is formed such that the direction of the long side thereof is in the [010] direction (or the [001] direction) of the compound semiconductor substrate 2. However, since the crystallographic orientations of the cathode region 1 and the compound semiconductor substrate 2 match, the PN junction between the cathode region 1 and an anode region described later has a rectangular shape and the direction of the long side is [ 01
0] direction (or [001] direction). If the direction of the long side is the [010] direction, the direction of the short side is the [001] direction, and the direction of the long side is [00].
In the [1] direction, the direction of the short side is the [010] direction.

FIG. 2 is a sectional view showing the structure of the compound semiconductor device on a plane orthogonal to the long side of the cathode region 1 shown in FIG. As shown in the figure, a region facing the cathode region 1 of the compound semiconductor substrate 2 is an anode region 6 (N-type region of a diode) as a first region, and a PN region is provided between the cathode region 1 and the anode region 6. A junction Rpn is formed. A cathode electrode 7 is provided on the cathode region 1, and an anode electrode 8 is provided on the back surface of the compound semiconductor substrate 2, which is to be the anode region 6, and a part of the cathode electrode 7 extends from the surface of the compound semiconductor substrate 2. , An insulating film 9 is provided. That is,
This compound semiconductor device functions as a diode.

The operation of the compound semiconductor device of the present embodiment configured as described above will be described below. When a forward bias is applied to the semiconductor device of the present embodiment, minority carriers injected from the cathode region 1 via the PN junction Rpn diffuse in the anode region 6.
At this time, the crystallographic orientation in the long side direction of the cathode region 1 is matched with the [010] direction (or the [001] direction) of the compound semiconductor substrate 2 as shown in FIG. Even if the stress of the insulating film 9 acts, almost no piezo charge is generated as in the above-described conventional case. Therefore, the minority carriers injected into the anode region 6 are:
Without being affected by the piezo charge, it diffuses in the anode region 6 according to the difference in carrier concentration, that is, toward the anode electrode 8. As a result, the anode region 6
The recombination of minority carriers in the surface region is suppressed, and high injection efficiency can be obtained.

Although the same applies to each embodiment described later, the compound semiconductor substrate 2 is not necessarily a substrate such as GaAs, but may be a GaAs layer or the like epitaxially grown on an insulator.

(Second Embodiment) Next, a second embodiment will be described with reference to the drawings. Also in this embodiment, the crystallographic orientation relationship between the compound semiconductor substrate and the cathode region of the compound semiconductor device is the same as the relationship shown in FIG. 1 in the first embodiment. The cathode region 1 is the same in that the long side direction is formed in the [010] direction (or the [001] direction) of the compound semiconductor substrate 2. FIG.
Is a cross-sectional view of the compound semiconductor device according to the present embodiment. This compound semiconductor device has basically the same cross-sectional shape as the cross-sectional shape shown in FIG. 2 in the first embodiment. However, in the present embodiment, the lattice constant of the material forming the cathode region 1 is different from the lattice constant of the material forming the compound semiconductor substrate 2. That is, the PN junction Rpn is formed by a so-called hetero junction.

The operation of the compound semiconductor device of the second embodiment configured as described above will be described below. When a forward bias is applied to the compound semiconductor device of the second embodiment, the PN junction Rpn
Minority carriers diffuse through the anode region 6. At this time, by setting the long side direction of the cathode region 1 to the [010] direction (or the [001] direction), the minority carriers are transferred to the cathode region 1 in contact with the anode region 6 by the same operation as in the first embodiment. Further, the inside of the anode region 6 is diffused without being affected by piezo charges caused by the stress of the insulating film 9. In particular, in the present embodiment, since the PN junction Rpn is composed of a hetero junction, the stress acting on the PN junction Rpn and its peripheral portion is large. Recombination of minority carriers is suppressed, and high injection efficiency can be obtained.

Third Embodiment Next, a third embodiment will be described. FIG.
FIG. 11 is a perspective view schematically showing a crystallographic orientation relationship between a compound semiconductor substrate and an emitter region of the compound semiconductor device according to the embodiment. 2, reference numeral 2 denotes a compound semiconductor substrate, reference numeral 3 denotes a (100) plane of the compound semiconductor substrate 2, reference numeral 4 denotes a (0-1-1) plane of the compound semiconductor substrate 2, and reference numeral 5 denotes a compound semiconductor substrate. Numeral 10 indicates a rectangular emitter region having a planar shape composed of long sides and extremely small short sides. Here, similarly to the orientation relationship shown in FIG. 1, the crystallographic orientation in the long side direction of the emitter region 10 is the [010] direction (or [00]
1] direction).

FIG. 5 is a cross-sectional view taken along a plane perpendicular to the long side of the emitter region 10 of the compound semiconductor device shown in FIG. As shown in FIG. 1, a collector region 13 is formed on the compound semiconductor substrate 2, a base region 12 as a first region is formed on the collector region 13, and a second region is formed on the base region 12. An emitter region 10 is formed as two regions. An emitter electrode 14 is formed on the emitter region 10, a base electrode 15 is formed on the base region 12 on both sides of the emitter region 10, and a collector electrode 16 is formed in a recess provided in the collector region 13. Are formed. Then, an insulating film 9 is deposited on the entire surface. The emitter region 10, the base region 12, and the collector region 13 are formed on the compound semiconductor substrate 2 by M
N-type Al grown by OCVD or MBE
It is composed of GaAs, p-type GaAs and n-type GaAs, respectively. However, the base region 12 may be made of AlGaAs in which the mixed crystal ratio of Al is inclined.

In this embodiment, the emitter region 10
The emitter width which is the length in the short side direction of the emitter region 10
The emitter length, which is the length in the long side direction, is, for example, 2 μm and 20 μm, respectively, in order to realize good high-frequency characteristics.
It can be about μm. Also, the emitter region 1
0, base region 12 and collector region 13
Another material system in which the band gap of the emitter region 10 is larger than the band gap of the base region 12 may be used.

The operation of the third embodiment configured as described above will be described below. When a bias is applied to the semiconductor device of the third embodiment, the emitter region 1
Minority carriers injected from 0 diffuse inside the base region 12. At this time, the direction of the long side of the emitter region 10 is set to [010] (or [00] of the compound semiconductor substrate 2).
1) direction), the minority carrier becomes
The electrons reach the collector region 13 without being affected by piezo charges caused by the stress of the emitter region 10 and the insulating film 9 in contact with the base region 12. This operation will be described later in detail. As a result, p with a fast recombination rate
Recombination of minority carriers in the external base region of type GaAs is suppressed, and a high current amplification factor can be obtained.

(Fourth Embodiment) Next, a fourth embodiment will be described. FIG. 6 is a perspective view schematically showing a crystallographic orientation relationship between the compound semiconductor substrate and the collector region of the compound semiconductor device according to the fourth embodiment. Reference numeral 2 denotes a compound semiconductor substrate, reference numeral 3 denotes a (100) plane of the compound semiconductor substrate 2, reference numeral 4 denotes a (0-1-1) plane of the compound semiconductor substrate 2, and reference numeral 5 denotes a (01) surface of the compound semiconductor substrate 2. Reference numeral 13 denotes a rectangular collector region having a plane shape composed of long sides and extremely small short sides. The collector region 13 is arranged so that the long side direction is the [010] direction (or the [001] direction).

FIG. 7 is a sectional view of the compound semiconductor device taken along a plane orthogonal to the long side of collector region 13 shown in FIG. As shown in FIG. 1, an emitter region 10 is selectively formed on the compound semiconductor substrate 2 by injection separation, and a base region 12 as a first region is formed on the emitter region 10.
Are formed, and a collector region 13 as a second region is formed on the base region 12. Also,
A collector electrode 16 is formed on the collector region 13, a base electrode 15 is formed on the base region 12 on both sides of the collector region 13, and an emitter electrode 14 is formed on a recess provided in the emitter region 10. Have been.
Then, an insulating film 9 is deposited on the entire surface. The emitter region 10, base region 12, and collector region 13 are n-type GaAs, p-type GaAs, and n-type Al grown on the compound semiconductor substrate 2 by MOCVD or MBE.
Each is constituted by a GaAs crystal. However, the base region 12 may be made of AlGaAs in which the mixed crystal ratio of Al is inclined. Collector area 1
Collector width, which is the length in the short side direction of 3, collector region 1
The collector length, which is the length in the long side direction, is, for example, 2 μm, 2 μm,
It can be about 0 μm. Further, in order to improve the emitter injection efficiency, the base electrode 15 of the base region 12 is formed.
The region immediately below is increased in resistance by ion implantation, and only the region below the collector electrode 16 of the emitter region 10 is involved in the operation as the intrinsic region of the semiconductor device. Therefore, the effective shape of the emitter region 10 is the collector electrode 1
It becomes a rectangle like the shape of No. 6. Note that the emitter region 1
0, base region 12 and collector region 13
Another material system in which the band gap of the emitter region 10 is larger than the band gap of the base region 12 may be used.

The operation of the bipolar semiconductor device according to the fourth embodiment configured as described above will be described below. When a bias is applied to the bipolar semiconductor device of the fourth embodiment, minority carriers injected from the emitter region 10 diffuse inside the base region 12. However, by setting the crystallographic orientation of the collector region 13 in the long side direction to the [010] direction or the [001] direction, minority carriers are generated due to stress in the emitter region 10 and the insulating film 9 in contact with the base region 12. It reaches the collector region 13 without being affected by the piezo charge. As a result, recombination of minority carriers in the external base region of p-type GaAs having a high recombination speed is suppressed, and a high current amplification factor can be obtained.

Next, the difference between the operation of the minority carrier in each of the above embodiments and the operation of the minority carrier in the conventional structure will be described.

FIG. 8A is a sectional view showing the operation of minority carriers in the compound semiconductor device of the present invention.
FIG. 2B is a cross-sectional view showing the operation of minority carriers in a conventional compound semiconductor device. FIGS. 8A and 8B show common operations in the structure of the compound semiconductor device of each of the above embodiments. For convenience, the operation of minority carriers injected from the emitter region into the base region will be described here. (Corresponding to the third embodiment). In the structure of the conventional compound semiconductor device, the side (in this case, the long side) of the emitter region that generates a stress in the base region is in the [01-1] direction. Generates a piezo charge. Then, due to the influence of the piezo charge, the probability that the minority carriers injected into the base region diffuse into the surface region of the base region and recombine at the surface level increases. Therefore, as shown by the broken line in FIG. 9, when the short side of the emitter region or the like above the PN junction is miniaturized and the ratio L / S is increased, minority carriers are guided to the surface region to promote recombination. Since the region where the piezo charge is generated is enlarged, the base current increases and the emitter injection efficiency decreases. On the other hand, in the present invention, the long side of the emitter region is in the [010] direction (or the [001] direction).
Therefore, almost no piezo charge is generated in the base region. Therefore, as shown in FIG. 8A, the minority carriers injected into the base region are diffused according to the carrier concentration without being affected by the piezo charge.
It will diffuse to the collector region side. That is, FIG.
As shown by the solid line, when the ratio L / S is low, the base current (higher injection efficiency) is smaller than that of the conventional structure, and the base current is almost constant even when the ratio L / S is increased. It can be seen that a decrease in emitter injection efficiency can be effectively prevented.

In the present invention, the dimensions of the second regions such as the emitter region and the cathode region or the dimensions of the PN junction are not limited to the examples described in the above embodiments. However, it is preferable that the short side length is about 0.5 to 6 μm and the long side is about 1 to 50 μm in order to exhibit high high frequency characteristics.

[0044]

According to the first compound semiconductor device of the present invention,
For example, on the first semiconductor region where minority carriers diffuse and move,
Forming a second semiconductor region, and forming the second semiconductor region in a planar shape
Is a right-angled quadrilateral and the direction of the long side or short side
But a first semiconductor region that hardly generates piezoelectric charges
Was formed to match the crystallographic orientation of
Reduction of minority carrier injection efficiency due to charge effects
Suppression can be achieved.

According to the second compound semiconductor device of the present invention,
For example, if the compound semiconductor substrate is directly in a plane parallel to the (100) plane,
First adjacent ones to form a square quadrilateral PN junction
Compound semiconductor provided with semiconductor region and second semiconductor region
In the body device, the long side or short side of the PN junction is
Make it parallel to the [010] direction of the conductor board, and
The direction of the short side is changed to the first which generates almost no piezo charge.
Because the crystallographic orientation of the semiconductor region was matched,
Reduction of injection efficiency due to recombination at rear surface states
Suppression can be achieved.

[Brief description of the drawings]

FIG. 1 is a perspective view schematically showing a crystallographic orientation relationship between a compound semiconductor substrate and a cathode region of a compound semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view showing a structure of the compound semiconductor device according to the first embodiment in a plane orthogonal to a long side of a cathode region.

FIG. 3 is a cross-sectional view in a plane orthogonal to a long side of a cathode region of a compound semiconductor device according to a second embodiment.

FIG. 4 is a perspective view schematically showing a crystallographic orientation relationship between a compound semiconductor substrate and an emitter region of a compound semiconductor device according to a third embodiment.

FIG. 5 is a cross-sectional view of a plane perpendicular to a long side of an emitter region of a compound semiconductor device according to a third embodiment.

FIG. 6 is a perspective view schematically showing a crystallographic orientation relationship between a compound semiconductor substrate and a collector region of a compound semiconductor device according to a fourth embodiment.

FIG. 7 is a cross-sectional view in a plane orthogonal to a long side of a collector region of a compound semiconductor device according to a fourth embodiment.

FIG. 8 is a cross-sectional view for explaining the difference between the operation of minority carriers according to the structure of the present invention and the operation of minority carriers according to the conventional structure.

FIG. 9 is a diagram showing the difference between the conventional compound semiconductor device and the compound semiconductor device of the present invention in the change characteristic of the base current with respect to the change in the ratio L / S.

FIG. 10 is a perspective view showing a general structure of a conventional compound semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 cathode region (second region) 2 compound semiconductor substrate 3 (100) surface 4 (0-1-1) surface 5 (01-1) surface 6 anode region (first region) 7 anode electrode 8 cathode electrode 9 insulating film Reference Signs List 10 Emitter region (second region) 12 Base region (first region) 13 Collector region (second region) 14 Emitter electrode 15 Base electrode 16 Collector electrode

Continuation of the front page (56) References JP-A-5-136159 (JP, A) JP-A-63-48863 (JP, A) JP-A-8-139101 (JP, A) JP-A-5-243258 (JP) JP-A-5-243257 (JP, A) JP-A-2-83933 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/737 H01L 21/331 H01L 29/73 H01L 29/205 H01L 29/04 H01L 29/861

Claims (9)

(57) [Claims] 1. A (100) to a part of the compound semiconductor substrate to the surface main surface, a first semiconductor <br/> region minority carrier diffusion movement, the first being formed on the first semiconductor region semiconductor
In a compound semiconductor device comprising a second semiconductor region having a lattice constant different from that of the region, the second semiconductor region has a planar shape of a rectangular quadrangle.
And the direction of the long side or the short side
Coincides with the crystallographic orientation of the first semiconductor region which is not generated
A compound semiconductor device characterized by being formed as follows . 2. The compound semiconductor device according to claim 1, wherein
hand, In the second semiconductor region, a long side or a short side of the quadrangle is
It is parallel to the [010] direction of the compound semiconductor substrate.
Compound semiconductor device characterized by being formed as follows:
Place. 3. A compound semiconductor device according to claim 1 or 2, wherein said first semiconductor region is composed of a first conductivity type semiconductor having parallel surfaces (100) plane, the second semiconductor region Is a compound semiconductor device formed of a second conductivity type semiconductor so as to form a rectangular PN junction with the first semiconductor region. The semiconductor device of claim 3, wherein said second semiconductor region, a compound semiconductor device, characterized in that the short sides of the right angles quadrilateral is formed in miniaturized rectangular. 5. The semiconductor device according to claim 3 , wherein the compound semiconductor device is a bipolar transistor, the first semiconductor region is a base region of the bipolar transistor, and the second semiconductor region is A compound semiconductor device, being an emitter region of the bipolar transistor, wherein a collector region of the bipolar transistor is formed below the base region. 6. The semiconductor device according to claim 1, wherein said compound semiconductor device is a bipolar transistor, said first semiconductor region is a base region of said bipolar transistor, and said second semiconductor region is said bipolar transistor. A compound semiconductor device, being a collector region of a transistor, wherein an emitter region of the bipolar transistor is formed below the base region. 7. The compound semiconductor device according to claim 1, wherein said second semiconductor region is an electrode contacting said first semiconductor region. 8. The method according to claim 8 , wherein the (100) plane of the compound semiconductor substrate is
First semiconductor region and second semiconductor having different lattice constants from each other
A first semiconductor region and a second semiconductor region;
Compound semiconductor device having PN junction where regions contact each other
In the above, the PN junction has two planar shapes orthogonal to each other.
And a long side or a short side of the PN junction is formed of the compound semiconductor substrate.
Of the long side or the short side
First semiconductor that generates almost no piezo charge
A compound semiconductor device formed to match a crystallographic orientation of a region . 9. The compound semiconductor device according to claim 8 , wherein the shape of the PN junction is a rectangular shape whose short sides are miniaturized.