JP2003142405A - Method for manufacturing semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacturing such a semiconductor substrate that has no acute angel part at an edge and can improve yield. SOLUTION: For example, the single crystallinity of the edge 1A of a wafer 1 is destroyed through ion implantation or sand blasting to form a damage layer 11 on the surfacial layer of the wafer edge 1A. Then a silicon epitaxial layer 2 is allowed to grow on the wafer 1. The silicon epitaxial layer 2 is not epitaxially grown thereon (it becomes polysilicon 2A), so that the epitaxial layer 2 can be prevented from being an acute angle at the edge of the wafer 1. In place of the damage layer 11, a polysilicon layer, an amorphous silicon layer or a silicon oxide layer may be formed on the edge 1A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate including a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, and more particularly to a semiconductor which does not have a sharp edge portion and can improve the yield. TECHNICAL FIELD The present invention relates to a technique for manufacturing a substrate.

[0002]

2. Description of the Related Art As shown in FIGS. 22 and 23, for example, a conventional silicon substrate 21P used in a power device is used.
Is manufactured, for example, by forming an epitaxial layer 2 on a silicon wafer (hereinafter, also simply referred to as “wafer”) 1 whose main surface 1S has a plane orientation of (100). Depending on the type of power device, a very thick epitaxial layer 2 of several tens to 200 μm may be required.

[0003]

Conventional silicon substrate 2
According to the manufacturing method of 1P, when the thick film epitaxial layer 2 is formed, the (111) plane is generated in the vicinity of the edge portion 1A of the wafer 1 due to the anisotropy or plane orientation dependence of the epitaxial growth on the crystal orientation. To do. At this time, as shown in FIG. 24, due to the plane orientation dependence of the epitaxial growth, the edge portion 1A of the <011> orientation has (111)
The surface appears. This is because the (111) plane has a slow epitaxial growth rate. In this way, the edge portion 1 of the silicon wafer 1 which has been chamfered (beveled) beforehand
A changes to an acute angle during the growth of the epitaxial layer 2 (see FIG. 23). Note that such an acute angle portion is likely to occur when the epitaxial layer 2 is thicker than about 20 μm.

In the conventional method of manufacturing the silicon substrate 21P, there is a problem that the above-mentioned acute angle portion causes chipping or cracking of the silicon substrate 21P in the device manufacturing process. Such chipping or cracking causes a decrease in yield.

The present invention has been made in view of the above points, and is a semiconductor substrate including a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer,
An object of the present invention is to provide a method for manufacturing a semiconductor substrate which does not have a sharp edge portion and can improve the yield.

[0006]

A method of manufacturing a semiconductor substrate according to claim 1 is a method of manufacturing a semiconductor substrate including a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, wherein (a) at least A step of preparing one semiconductor wafer, and (b) a step of forming an epitaxial growth prevention layer for preventing epitaxial growth on an edge portion of the at least one semiconductor wafer,
(c) after the step (b), a step of growing an epitaxial layer on the at least one semiconductor wafer.

A method of manufacturing a semiconductor substrate according to a second aspect is the method of manufacturing a semiconductor substrate according to the first aspect,
The step (b) includes the step (b) -1) of breaking the single crystallinity of the surface layer of the edge portion of the at least one semiconductor wafer to form a damaged layer as the epitaxial growth prevention layer.

A method of manufacturing a semiconductor substrate according to a third aspect is the method of manufacturing a semiconductor substrate according to the second aspect,
The step (b) -1) includes the step (b) -1-1) of forming the damaged layer by using at least one of an ion implantation method and a sandblast method.

A method of manufacturing a semiconductor substrate according to a fourth aspect is the method of manufacturing a semiconductor substrate according to the first aspect,
The step (b) includes (b) -2) a step of forming a non-single crystal layer as the epitaxial growth prevention layer on the edge portion of the at least one semiconductor wafer.

A method of manufacturing a semiconductor substrate according to a fifth aspect is the method of manufacturing a semiconductor substrate according to the fourth aspect,
The non-single-crystal layer includes a polycrystalline layer or an amorphous layer.

A method of manufacturing a semiconductor substrate according to a sixth aspect is the method of manufacturing a semiconductor substrate according to the first aspect,
The step (b) includes (b) -3) forming an oxide layer as the epitaxial growth prevention layer on the edge portion of the at least one semiconductor wafer.

A method of manufacturing a semiconductor substrate according to a seventh aspect is the method of manufacturing a semiconductor substrate according to the sixth aspect,
The step (b) -3) includes (b) -3-1) the step of forming the oxide layer on the entire surface of the at least one semiconductor wafer;
3-2) a step of protecting the vicinity of the edge portion of the at least one semiconductor wafer with a jig, and (b) -3-3) the at least one semiconductor wafer protected by the jig. Removing the oxide layer on one or both major surfaces of the wafer.

A method of manufacturing a semiconductor substrate according to claim 8 is the method of manufacturing a semiconductor substrate according to claim 7,
In the step (b) -3-2), the oxide layer on the main surface is formed by at least one of (b) -3-2-1) dry etching method, wet etching method and vapor etching method. The step of removing is included.

A method of manufacturing a semiconductor substrate according to claim 9 is the method of manufacturing a semiconductor substrate according to any one of claims 1 to 6, wherein the at least one semiconductor wafer is a plurality of semiconductors. Including the wafer, the step (a)
Includes (a) -1) a step of preparing and stacking the plurality of semiconductor wafers.

A method of manufacturing a semiconductor substrate according to a tenth aspect is a method of manufacturing a semiconductor substrate including a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, the method comprising: (d) preparing a semiconductor ingot; A step of forming a non-single-crystal layer on a side surface of the semiconductor ingot, and (f) slicing the semiconductor ingot having the non-single-crystal layer, and having the non-single-crystal layer at an edge portion. The method comprises the steps of obtaining at least one semiconductor wafer, and (g) growing an epitaxial layer on the at least one semiconductor wafer.

A method of manufacturing a semiconductor substrate according to claim 11 is a method of manufacturing a semiconductor substrate including a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, wherein (h) the epitaxial layer is formed on the semiconductor wafer. A step of growing, (i) a step of chamfering an edge portion of the epitaxial layer, (j) a step of polishing the epitaxial layer on the main surface of the semiconductor wafer, and (k) the step (j) And heat treating the epitaxial layer in an atmosphere of at least one of hydrogen and an inert gas.

A method of manufacturing a semiconductor substrate according to claim 12 is a method of manufacturing a semiconductor substrate including a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, wherein (l) the epitaxial layer is formed on the semiconductor wafer. A step of growing, (m) a step of chamfering the edge portion of the epitaxial layer, (n) a step of polishing the epitaxial layer on the main surface of the semiconductor wafer, and (o) after the step (n) Growing a new epitaxial layer on the epitaxial layer.

A method of manufacturing a semiconductor substrate according to claim 13 is the method of manufacturing a semiconductor substrate according to claim 11 or 12, wherein the step (h) or the step (l) is performed before the step (h). No mirror polishing treatment is performed on the semiconductor wafer.

The method of manufacturing a semiconductor substrate according to claim 14 is a method of manufacturing a semiconductor substrate comprising a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, wherein (p) the semiconductor wafer is mirror-polished. Without performing a process, a step of growing an epitaxial layer on the semiconductor wafer, (q) a step of chamfering the edge portion of the epitaxial layer, (r) the epitaxial layer on the main surface of the semiconductor wafer And a step of polishing.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION <First Preferred Embodiment> A method of manufacturing a silicon substrate (or a semiconductor substrate) 21 to 23 according to a first preferred embodiment will be described with reference to the sectional views of FIGS. Note that, in FIG. 2 and the like, a portion A surrounded by a broken line in FIG. 1 is shown in an enlarged manner.

First, a silicon single crystal wafer (or semiconductor wafer; hereinafter also simply referred to as "wafer") 1
Are prepared (see FIG. 1). Then, for example, by a ion implantation method or a sandblast method, a side edge portion or an edge portion of the wafer 1 (hereinafter, also referred to as “wafer edge portion”) 1A
By destroying the single crystallinity of the wafer edge portion 1
A damage layer (or an epitaxial growth prevention layer) 11 is formed on the surface layer of A (see FIG. 2). Then, a silicon epitaxial layer (hereinafter, also simply referred to as “epitaxial layer”) 2 is grown on the wafer 1 to obtain a silicon substrate 21 including the wafer 1 and the epitaxial layer 2 and in the state shown in FIG.

That is, while the epitaxial layer 2 is epitaxially grown on the main surface 1S of the wafer 1 (hereinafter also referred to as "wafer main surface"), the damaged layer 1
In No. 1, since the single crystallinity is broken, the epitaxial layer 2 does not grow epitaxially on the damaged layer 11 and becomes polysilicon (see polysilicon 2A in FIG. 3). That is, since the damaged layer 11 prevents the epitaxial growth in the process of forming the epitaxial layer 2, the damaged layer can suppress the generation of the (111) plane due to the plane orientation anisotropy of the epitaxial growth.
It is possible to prevent the epitaxial layer 2 from being sharpened at the wafer edge portion 2A. As described above, according to the manufacturing method using the damaged layer 11, it is possible to manufacture the silicon substrate 21 having no acute-angled edge portion,
With such a silicon substrate 21, it is possible to suppress a decrease in yield due to chipping or cracking of the acute angle portion, that is, to improve the yield.

A general silicon substrate including the silicon substrate 21 is manufactured in the order of wafer slicing, chamfering (beveling), lapping, etching, mirror polishing (mechanical polishing) and epitaxial growth. Therefore, the step of forming the damaged layer 11 can be performed after the chamfering step of the wafer 1, after the lapping step, and after the etching step.

The damaged layer 11 is formed, for example, by the following method. That is, as shown in FIG. 4, a plurality of wafers 1 are prepared and the main surfaces 1S thereof are faced to each other and stacked. Then, the plurality of wafers 1 stacked in this manner
For example, while rotating about a direction perpendicular to the main surface 1S of the wafer as a rotation axis, ion implantation is collectively (integrally) performed on the plurality of wafer edge portions 1A. Alternatively, similarly, as shown in FIG. 5, sandblasting is collectively performed on the plurality of wafer edge portions 1A while rotating the plurality of stacked wafers 1. The damaged layer 11 may be formed by using both the ion implantation method and the sandblast method.

By stacking a plurality of wafers 1 in this manner, the damage layer 11 can be formed only on the wafer edge portion 1A while protecting each wafer main surface 1S. Furthermore, since the damaged layer 11 can be formed on a plurality of wafers 1 at the same time, the damaged layer 1 can be formed with high productivity.
1 can be formed.

Ion species 51 in the ion implantation method (see FIG.
As a reference), for example, silicon, an inert gas element such as argon, oxygen, nitrogen, carbon, or the like can be used. Note that a general dopant element such as boron, phosphorus, arsenic, or antimony and its compound (for example, BF ₂ ) can be used as the ion species 51 as long as they do not affect the diffusion layer of the device. Is. Further, as the sandblast material 52 (see FIG. 5) in the sandblasting method, for example, silica abrasive grains, alumina abrasive grains, or silicon carbide abrasive grains can be used.

Further, FIGS. 4 and 5 show the case where the incident angles of the ion species 51 and the sandblast material 52 are constant, but the ion implantation and the ion implantation are performed at a plurality of incident angles or while changing the incident angles. Sandblasting may be performed.

In view of the epitaxial growth prevention function of the damage layer 11, it is possible to prevent the epitaxial growth by the non-single crystal layer (or the epitaxial growth prevention layer) 12 shown in FIGS. The same effect can be obtained. Here, the non-single-crystal layer includes, for example, a polycrystalline layer, an amorphous layer, and the like, and is a layer having a low single crystal level as a whole.

Specifically, as shown in FIG. 6, similar to the step of forming the damaged layer 11, a plurality of wafers 1 are superposed, and while the plurality of superposed wafers 1 are rotated, for example, a CVD method is used. A non-single crystal layer (for example, a polysilicon layer or an amorphous silicon layer) 12 is collectively formed on a plurality of wafer edge portions 1A by using the above. At this time, since the CVD method involves heating the wafer 1, it is more preferable to carry out the step of forming the non-single-crystal layer 12 after etching the wafer 1 with higher cleanliness (after lapping). After that, the silicon substrate 22 having no sharp edge portion (see FIG. 7) is formed by the same process as in the case of the damage layer 11.
Reference) can be produced.

Further, the epitaxial growth can be prevented by the silicon oxide layer (or the epitaxial growth prevention layer) 13 (hereinafter also simply referred to as “oxide layer”) 13 shown in FIG. 8 and FIG. 9, and like the damage layer 11. The effect of is obtained. Specifically, in the same manner as described above, while rotating the plurality of stacked wafers 1, for example, C
Multiple wafer edge parts 1A using VD method or thermal oxidation method
Then, the oxide layer 13 is formed collectively. After that, damage layer 1
The silicon substrate 23 (see FIG. 9) having no sharp edge portion can be manufactured by the same process as in the case of 1.

<Second Embodiment> In the second embodiment, another method of manufacturing the above-described silicon substrate 23 (see FIG. 9) will be described with reference to FIGS. 10 and 11. First, the oxide layer 13 is deposited on the entire surface of the wafer 1 after mirror polishing, or the entire surface is thermally oxidized to form the oxide layer 13 (see FIG. 10). After that, as shown in the sectional view and the plan view of FIG. 10, the wafer 1 is set on the jig 53.

The jig 53 has a device forming area except for the central portion of one wafer main surface 1S, more specifically, the entire outer peripheral area (area having a width of 1 to 2 mm from the outer peripheral edge) of the main surface 1S. The wafer 1 is accommodated by exposing the region including the wafer 1.
That is, the jig 53 includes a portion near the wafer edge portion 1A (specifically, includes at least the side surface of the wafer 1, and in this case, the side surface and the entire outer peripheral area of both wafer main surfaces 1S) and the other wafer main portion. It covers the surface 1S. Further, the jig 53 sandwiches and fixes the wafer 1 in the thickness direction in the entire outer peripheral region of both wafer main surfaces 1S.

In particular, the jig 53 is a wafer 1 so that a portion of the wafer 1 (the upper oxide layer 13) that is not exposed from the jig 53 does not come into contact with etching gas or the like in the step of removing the oxide layer 13 described later. Holds 1. That is, the jig 53 protects the portion near the wafer edge portion 1A from the etching process, in other words, provides the etching resistance.

At least one of the oxide layer 13 on the above-mentioned one main surface 1S of the wafer 1 with the jig 53 attached is selected from, for example, a dry etching method, a wet etching method using a hydrofluoric acid solution, and an etching method using a hydrofluoric acid vapor. (And therefore may be combined with each other) (see FIG. 1
(See section 1). As a result, the one main surface 1S is exposed while the oxide layer 13 can be left in the vicinity of the edge portion 1A.

Thereafter, the wafer 1 is taken out of the jig 53, and the epitaxial layer 2 is grown on the one main surface 1S of the wafer 1 to manufacture the silicon substrate 23 having no sharp edge portion. it can. In addition,
For example, the jig 53 may be designed so that both wafer main surfaces 1S are exposed and the oxide layer 13 on both wafer main surfaces 1S may be removed. In such a case, as shown in FIG. The oxide layer 13 remains only in this region, and the silicon substrate 23 in the state shown in FIG. 9 is obtained.

At this time, in the manufacturing method according to the second embodiment, since a simple method of setting the wafer 1 on the jig 53 is used, compared with the case where the vicinity of the edge portion 1A of the wafer 1 is protected by a resist, for example. Therefore, the number of steps and the number of steps are small, so that the silicon substrate can be manufactured at low cost.

<Third Embodiment> A method of manufacturing a silicon substrate 24 according to a third embodiment will be described with reference to FIGS. First, as shown in the perspective view of FIG. 12, a silicon single crystal ingot (or a semiconductor ingot; hereinafter also simply referred to as “ingot”) 3 is prepared. Then, as shown in the perspective view of FIG. 13, the aforementioned non-single-crystal layer 12 is formed on the side surface 3A of the ingot 3.

Then, the ingot 3 is sliced and subjected to wafer processing such as chamfering, lapping, etching and mirror polishing, so that the edge portion 1B is formed of the non-single crystal layer 12 as shown in the sectional view of FIG. Wafer 1
Is obtained.

The diameter of the ingot 3 is processed to be slightly smaller than the diameter of the cut wafer 1.
Specifically, in consideration of the general edge chamfering width being about 0.5 mm, it is reduced by about 1 to 2 mm.

After that, the silicon epitaxial layer 2 is grown on the wafer 1 having the non-single crystal layer to obtain the silicon substrate 24 in the state shown in the sectional view of FIG.

According to the above manufacturing method, the non-single-crystal layer 12
Causes the epitaxial layer 2 to move to the wafer edge portion 1B.
It is possible to prevent sharpening. That is, it is possible to manufacture the silicon substrate 24 which does not have a sharp edge portion and can improve the yield as a result.

<Regarding Embodiments 1 to 3> As described above, according to the manufacturing method according to Embodiments 1 to 3, the silicon substrates 21 to 24 having no acute-angled edges are manufactured. You can

At this time, if there are pinholes in the oxide layer 13, the epitaxial layer 2 may grow abnormally from the pinholes and dust may be generated in the device manufacturing process. However, the damage layer 11 and the non-single-crystal layer 12 may be generated. According to the above, such dust is unlikely to occur.

Further, according to the damaged layer 11, the polysilicon 2A deposited during the formation of the epitaxial layer 2 is less likely to peel off than the non-single-crystal layer 12, so that a silicon substrate having higher mechanical strength is manufactured. be able to.

Incidentally, the non-single crystal layer 12 can be formed in any of the first and third embodiments. However, in the manufacturing method according to the third embodiment, chamfering is performed after being cut out from the ingot 3 (hence, the non-single crystal layer 12 is chamfered), whereas in the manufacturing method according to the first embodiment, The chamfering process is completed before the formation of the crystal layer 12.
Therefore, the non-single crystal layer 12 according to the third embodiment is
Since it is processed more smoothly than the non-single-crystal layer 12 according to the first embodiment, it is less likely to peel off from the polysilicon 2A on the non-single-crystal layer 12. That is, the non-single-crystal layer 1 of the third embodiment
When 2 is used, a silicon substrate having higher mechanical strength can be manufactured.

The damaged layer 11 is formed by breaking the single crystallinity of the surface layer of the wafer edge portion 1A, whereas the non-single crystal layer 12 is formed by deposition in the manufacturing method according to the third embodiment. . Moreover, the non-single crystal layer 12 is formed thicker than the surface layer. Therefore, the damaged layer 11 is less likely to be peeled from the single crystal portion than the non-single crystal layer 12 according to the third embodiment, that is, a silicon substrate having higher mechanical strength can be manufactured.

From these points of view, the silicon substrate 22 manufactured using the non-single-crystal layer 12 of the first embodiment is more practical than the silicon substrate 23 manufactured using the oxide layer 13. Can be said. Next, it can be said that the silicon substrate 24 manufactured using the non-single-crystal layer 12 of the third embodiment is more practical, and the silicon substrate 21 manufactured using the damaged layer 11 is the most practical.

<Embodiment 4> Now, Japanese Patent Laid-Open No. 6-232
Japanese Patent Publication No. 057 discloses a manufacturing method in which an epitaxial layer is grown on a wafer, and then chamfering of the edge portion of the epitaxial layer and mirror polishing of the main surface are performed. Even by such a manufacturing method, it is possible to obtain a silicon substrate whose edge shape is not acute.

However, in this manufacturing method, since the epitaxial layer is mirror-polished, polishing damage causes
In some cases, the breakdown voltage characteristic of the gate oxide film of the device built in the silicon substrate may be defective.

Therefore, in the fourth embodiment, a method of manufacturing a silicon substrate which eliminates such a defect and obtains a favorable gate oxide film breakdown voltage characteristic will be described with reference to the cross-sectional views of FIGS. 16 to 21. .

First, as shown in FIG. 16, an epitaxial layer 2 is formed on a wafer 1 which has been subjected to lapping, etching and mirror polishing. At this time, an acute angle portion is generated in the edge portion of the epitaxial layer 2 corresponding to the wafer edge portion 1A. The surface shape of the main surface 1S of the wafer 1 after the etching is reflected on the (exposed) main surface of the epitaxial layer 2, and the surface shape is schematically illustrated in FIG. 16 and FIGS. 17 and 18 described later. ing.

After that, as shown in FIG. 17, the edge portion of the epitaxial layer 2 is chamfered to remove the above acute angle portion, and then the epitaxial layer 2 on the wafer main surface 1S is removed as shown in FIG. Mirror polishing.

In particular, after mirror-polishing the epitaxial layer 2, as shown in FIG. 19, a heat treatment (baking) is performed in a hydrogen or inert gas atmosphere at a temperature of about 1000.degree.
Carry out. Note that the heat treatment may be performed in a mixed atmosphere of hydrogen gas and an inert gas.

The silicon substrate 25 (see FIG. 20) manufactured by such a manufacturing method does not have a sharp edge portion at the edge portion due to the chamfering process of the edge portion of the epitaxial layer 2. Moreover, since the polishing damage in the polishing process is reduced and removed by the heat treatment process, the silicon substrate 2
No. 5 has the epitaxial layer 2 of good film quality, which can improve the gate oxide film breakdown voltage characteristic. As a result, the silicon substrate 25 can improve the yield.

Alternatively, instead of the heat treatment described above, FIG.
As shown in FIG. 5, a silicon substrate 26 having an epitaxial layer of good film quality can be obtained by forming a new epitaxial layer 4 on the epitaxial layer 2 after mirror polishing, and the silicon substrate 26 is the same as the silicon substrate 25. Has the same effect.

In this manufacturing method, the polishing amount of the epitaxial layer 2 is set in consideration of the new thickness of the epitaxial layer 4. For example, when the design value of the total thickness of the epitaxial layer 2 and the new epitaxial layer 4 after mirror polishing is 100 μm, the epitaxial layer 2 is polished to be slightly thinner than the above design value (for example, to be 98 μm), By forming a new epitaxial layer 4, the above 10
An epitaxial layer of 0 μm is formed.

By the way, since the epitaxial layer 2 is mirror-polished in the above-mentioned manufacturing method and the manufacturing method disclosed in the above-mentioned Japanese Patent Laid-Open No. 6-232057 (see FIG. 18), a wafer to be formed before the epitaxial layer 2 is formed. The mirror surface polishing process No. 1 can be omitted. That is, after lapping and etching the wafer 1, the growth step of the epitaxial layer 2 is performed without mirror polishing the wafer 1. Thereby, the silicon substrates 25, 26 and the like can be manufactured at low cost.

Incidentally, (I) the epitaxial layer 2 is polished,
A manufacturing method of performing heat treatment in an atmosphere of hydrogen or an inert gas after the polishing, a manufacturing method of polishing (II) the epitaxial layer 2 and forming a new epitaxial layer 4 after the polishing, and (III) a wafer The manufacturing method of omitting the mirror polishing of No. 1 can be combined with the manufacturing method of the above-described first to third embodiments.

[0059]

According to the invention of claim 1, the epitaxial growth prevention layer can prevent the epitaxial layer from being sharpened at the edge portion of the semiconductor wafer. That is, it is possible to manufacture a semiconductor substrate which does not have an acute-angled portion in the edge portion and as a result can improve the yield.

According to the second aspect of the invention, since the single crystallinity is destroyed in the damaged layer (surface layer at the edge of the semiconductor wafer), the epitaxial layer does not grow epitaxially on the damaged layer in the step (c) (poly Siliconize). Therefore, the damaged layer can provide a specific example of the epitaxial growth prevention layer. At this time, according to the damaged layer, a more practical semiconductor substrate can be manufactured as compared with the case where an oxide layer or a polysilicon layer is used as the epitaxial growth prevention layer.

According to the invention of claim 3, the single crystallinity of the surface layer of the edge portion of the semiconductor wafer can be destroyed by the ion implantation method and / or the sandblast method.
A damage layer can be embodied.

According to the invention of claim 4, in step (c), the epitaxial layer is not epitaxially grown on the non-single crystal layer (polysilicon is formed). Therefore, the non-single-crystal layer can provide a specific example of the epitaxial growth prevention layer.

According to the invention of claim 5, a non-single-crystal layer can be embodied.

According to the invention of claim 6, the epitaxial layer does not grow epitaxially on the oxide layer in the step (c) (it becomes polysilicon). Therefore, the oxide layer can provide a specific example of the epitaxial growth prevention layer.

According to the invention of claim 7, the oxide layer on one or both main surfaces of the semiconductor wafer is removed while the vicinity of the edge portion of the semiconductor wafer is protected, so that the main surface used for device formation is exposed. On the other hand, the oxide layer can be left in the vicinity of the edge portion. That is, step (b)-
A concrete example of 3) can be provided. At this time, since the step (b) -3-2) is a simple step of setting the semiconductor wafer on a jig, the number of steps and the process time are longer than those in the case where the vicinity of the edge of the semiconductor wafer is protected by a resist, for example. The semiconductor substrate can be manufactured in a small number and therefore at a low cost.

According to the invention of claim 8, step (b) -3-
A concrete example of 2) can be provided.

According to the invention of claim 9, the step (b) is carried out for a plurality of superposed semiconductor wafers, so that the epitaxial growth prevention layer is provided only on the edge portion while protecting the main surface of each semiconductor wafer. Can be formed.
Moreover, since the epitaxial growth prevention layer can be simultaneously formed on a plurality of semiconductor wafers, a highly productive manufacturing method can be provided.

According to the invention of claim 10, the step (g)
In, the epitaxial layer does not grow epitaxially on the non-single-crystal layer (it becomes polysilicon). Therefore, the non-single-crystal layer can prevent the epitaxial layer from sharpening at the edge portion of the semiconductor wafer. That is, it is possible to manufacture a semiconductor substrate which does not have an acute-angled portion in the edge portion and as a result can improve the yield.

According to the invention of claim 11, the step (i)
It is possible to manufacture a semiconductor substrate that does not have a sharp edge portion by the step (j) by the step (k)
It is possible to manufacture a semiconductor substrate provided with an epitaxial layer having a good film quality, in which polishing damage is reduced / removed. As a result, it is possible to manufacture a semiconductor substrate capable of improving the yield.

According to the invention of claim 12, the step (m)
It is possible to manufacture a semiconductor substrate that does not have a sharp edge portion by the step (o) and the step (n)
It is possible to manufacture a semiconductor substrate including an epitaxial layer having a better film quality than the epitaxial layer damaged by polishing. As a result, it is possible to manufacture a semiconductor substrate capable of improving the yield.

According to the thirteenth aspect of the present invention, since the epitaxial layer is grown without performing the mirror polishing step after etching (after lapping) which is generally performed, the semiconductor substrate can be manufactured at a lower cost. can do.

According to the invention of claim 14, the step (q)
As a result, it is possible to manufacture a semiconductor substrate which does not have a sharp edge portion and can improve the yield. Moreover, in the step (p), since the epitaxial layer is grown without performing the mirror polishing step after etching (after lapping) which is generally performed, the semiconductor substrate which can improve the above-mentioned yield is cheaper. Can be manufactured.

[Brief description of drawings]

FIG. 1 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 2 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 3 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 4 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 5 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 6 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 7 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 8 is a sectional view for illustrating the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 9 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the first embodiment.

FIG. 10 is a sectional view and a plan view for explaining the method for manufacturing the silicon substrate according to the second embodiment.

FIG. 11 is a sectional view for explaining the method for manufacturing the silicon substrate according to the second embodiment.

FIG. 12 is a perspective view for explaining the method for manufacturing the silicon substrate according to the third embodiment.

FIG. 13 is a perspective view for explaining the method for manufacturing the silicon substrate according to the third embodiment.

FIG. 14 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the third embodiment.

FIG. 15 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the third embodiment.

FIG. 16 is a sectional view for explaining the method for manufacturing the silicon substrate according to the fourth embodiment.

FIG. 17 is a sectional view for explaining the method for manufacturing the silicon substrate according to the fourth embodiment.

FIG. 18 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the fourth embodiment.

FIG. 19 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the fourth embodiment.

FIG. 20 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the fourth embodiment.

FIG. 21 is a cross-sectional view for explaining the method for manufacturing the silicon substrate according to the fourth embodiment.

FIG. 22 is a cross-sectional view for explaining the conventional method for manufacturing a silicon substrate.

FIG. 23 is a cross-sectional view for explaining the conventional method for manufacturing a silicon substrate.

FIG. 24 is a plan view of a silicon wafer for explaining a location where an acute angle portion is generated.

[Explanation of symbols]

1 Silicon wafer (semiconductor wafer), 1A, 1B
Edge portion, 1S main surface, 2 epitaxial layer, 3
Silicon ingot (semiconductor ingot), 3A side surface, 4 epitaxial layer (new epitaxial layer), 11 damaged layer (epitaxial growth prevention layer), 12 non-single crystal layer (epitaxial growth prevention layer), 13 oxide layer (epitaxial growth prevention layer), 2
1-26 Silicon substrate (semiconductor substrate), 53 jig.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hideki Naruoka             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Nobumi Hattori             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. (72) Inventor Hidekazu Yamamoto             2-3 2-3 Marunouchi, Chiyoda-ku, Tokyo             Inside Ryo Electric Co., Ltd. F term (reference) 5F045 AB02 AB03 AB04 AF03 BB15                       HA01 HA05 HA13 HA14

Claims (14)

[Claims] 1. A method of manufacturing a semiconductor substrate comprising a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, comprising: (a) preparing at least one semiconductor wafer; and (b) the at least 1 A step of forming an epitaxial growth prevention layer for preventing epitaxial growth on the edge portion of one semiconductor wafer; and (c) a step of growing an epitaxial layer on the at least one semiconductor wafer after the step (b). A method of manufacturing a semiconductor substrate, comprising: 2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the step (b) includes (b) -1) single crystallinity of a surface layer of the edge portion of the at least one semiconductor wafer. And a step of forming a damaged layer as the epitaxial growth prevention layer by breaking the above. 3. The method of manufacturing a semiconductor substrate according to claim 2, wherein the step (b) -1) uses at least one of (b) -1-1) an ion implantation method and a sandblast method. Forming the damage layer,
Manufacturing method of semiconductor substrate. 4. The method of manufacturing a semiconductor substrate according to claim 1, wherein the step (b) includes (b) -2) the epitaxial growth prevention layer on the edge portion of the at least one semiconductor wafer. A method for manufacturing a semiconductor substrate, including the step of forming a non-single-crystal layer as described above. 5. The method of manufacturing a semiconductor substrate according to claim 4, wherein the non-single-crystal layer includes a polycrystalline layer or an amorphous layer. 6. The method of manufacturing a semiconductor substrate according to claim 1, wherein the step (b) includes (b) -3) forming the epitaxial growth prevention layer on the edge portion of the at least one semiconductor wafer. A method of manufacturing a semiconductor substrate, the method including the step of forming an oxide layer. 7. The method of manufacturing a semiconductor substrate according to claim 6, wherein the step (b) -3) includes: (b) -3-1) oxidizing the entire surface of the at least one semiconductor wafer. A step of forming a layer, (b) -3-2) a step of protecting the vicinity of the edge portion of the at least one semiconductor wafer with a jig, (b) -3-3) using the jig Said at least 1 in a protected state
And a step of removing the oxide layer on one or both main surfaces of a plurality of semiconductor wafers. 8. The method of manufacturing a semiconductor substrate according to claim 7, wherein the step (b) -3-2) includes (b) -3-2-1) a dry etching method and a wet etching method. A method of manufacturing a semiconductor substrate, comprising a step of removing the oxide layer on the main surface by at least one of a vapor etching method. 9. The method of manufacturing a semiconductor substrate according to claim 1, wherein the at least one semiconductor wafer includes a plurality of semiconductor wafers, and the step (a) includes (a) -1) A method of manufacturing a semiconductor substrate, including a step of preparing and stacking the plurality of semiconductor wafers. 10. A method of manufacturing a semiconductor substrate comprising a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, comprising: (d) a step of preparing a semiconductor ingot; and (e) a side surface of the semiconductor ingot. Forming a non-single-crystal layer, and (f) slicing the semiconductor ingot having the non-single-crystal layer to obtain at least one semiconductor wafer having the non-single-crystal layer at an edge portion, (g) growing an epitaxial layer on the at least one semiconductor wafer. 11. A method of manufacturing a semiconductor substrate comprising a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, comprising: (h) growing an epitaxial layer on the semiconductor wafer; and (i) the epitaxial layer. A step of chamfering the edge portion of (j) a step of polishing the epitaxial layer on the main surface of the semiconductor wafer, and (k) the epitaxial layer after step (j) with hydrogen and an inert gas. And a step of performing heat treatment in at least one atmosphere. 12. A method of manufacturing a semiconductor substrate comprising a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, comprising: (l) growing an epitaxial layer on the semiconductor wafer; and (m) the epitaxial layer. A step of chamfering the edge portion of (b), (n) a step of polishing the epitaxial layer on the main surface of the semiconductor wafer, and (o) a new epitaxial layer grown on the epitaxial layer after the step (n) A method of manufacturing a semiconductor substrate. 13. The method of manufacturing a semiconductor substrate according to claim 11, wherein the semiconductor wafer is not mirror-polished before the step (h) or the step (l). , Method for manufacturing semiconductor substrate. 14. A method of manufacturing a semiconductor substrate comprising a semiconductor wafer and an epitaxial layer arranged on the semiconductor wafer, comprising: (p) performing a mirror polishing treatment on the semiconductor wafer, A step of growing an epitaxial layer on the semiconductor substrate, (q) a step of chamfering an edge portion of the epitaxial layer, and (r) a step of polishing the epitaxial layer on the main surface of the semiconductor wafer, Production method.