JP2003141884A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable optimizing easily page size and block size in which write, read-out, and erasure of a semiconductor memory are performed simultaneously in accordance with use. SOLUTION: Page size of write and read-out can be selected freely by inputting a command from the outside by a user using an element having a plurality of standard sub-cell-array, or by adding few processes in a stage of shipping, in system design, the maximum system performance can be achieved by optimizing units of write, read-out, and erasure in accordance with use. Thereby, a profitable result can be obtained also in interchangeability of element between generations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to an electrically rewritable semiconductor memory device.

[0002]

2. Description of the Related Art As one of conventional electrically rewritable semiconductor memory devices (EEPROM), a NAND cell type EE is used.
PROM (Electrically Erasable and Programmable R
ead Only Memory) has been proposed.

In this EEPROM, for example, a plurality of memory cells having an n-channel MOSFET structure in which a floating gate as a charge storage layer and a control gate are laminated are arranged in series so that adjacent memory cells share a source and a drain. They are connected and are connected to bit lines with this as one unit. One NAND in memory cell array
Plan views and equivalent circuits of the cell portion are shown in FIGS. 19 (a) and 19 (b).

20A and 20B are respectively shown in FIG.
It is an AA and BB sectional drawing of (a). P-type silicon substrate (or p-type well) 5 surrounded by element isolation oxide film 6
In the memory cell array, a memory cell array including a plurality of NAND cells is formed. In the case shown in FIG. 19, eight memory cells M _{1 to} M ₈ are connected in series to form one NAND cell.

As shown in FIG. 20B, a floating gate 14 is formed on the substrate 5 in each memory cell via a gate insulating film 7. As shown in FIGS. 19A and 20A, the floating gate 14 includes a plurality of floating gates 14 ₁ .
14 ₂ , ..., 14 ₈ . The n ⁺ -type diffusion layers 8 serving as the sources and drains of these memory cells are connected in series so that adjacent ones are shared.

As shown in FIGS. 19A and 20A, the first select gate 14 formed simultaneously with the floating gate and the control gate of the memory cell on the drain side and the source side of the NAND cell, respectively. ₉ and 16 ₉ and second select gates 14 ₁₀ and 16 ₁₀ are provided. The substrate 5 on which the NAND cell is formed is covered with a CVD oxide film 10 and a bit line 11 is arranged thereon. An oxide film 9 insulates the floating gate 14 from the control gate 16.

These control gates 16 are continuously connected to corresponding control gates of NAND cells adjacent to each other in the row direction to form word lines shown as CG ₁ to CG _{8 in} FIG. In addition, select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 1
6 ₁₀ are also continuously connected in the row direction, and the selection line S
It becomes G ₁ and SG ₂ . It should be noted that the select gates 14 ₉ , 16 ₉ and 14 ₁₀ , 16 ₁₀ are both 1 in a desired portion not shown.
The second layer and the second layer are electrically connected.

FIG. 21 shows an equivalent circuit of a memory cell array in which such NAND cells are arranged in a matrix. The source line is connected to a reference potential wiring made of Al, polycrystalline silicon, or the like via a contact for every 64 bit lines, for example. This reference potential wiring is connected to the peripheral circuit. The control gate of the memory cell and the first and second selection gates are continuously connected in the row direction.

As shown in FIG. 21, a set of memory cells connected to a normal control gate is called a page, and a first select line and a second select line connected to a set of drain-side and source-side select gates. 1NAN the set of pages between lines
It is called a D block or simply one block.

For example, one page has 256 bytes (256
× 8) composed of memory cells. This is called page size. Writing is simultaneously performed to the memory cells for one page. One block is, for example, 2048 bytes (20
It is composed of 48 × 8) memory cells. Memory cells for one block are erased at the same time.

Regarding the structure and operation of the row decoder for selecting the select gate and the control gate, see Japanese Patent Application No. 6-21803.
1 in detail.

FIG. 22 is a block diagram of a NAND flash memory. In the conventional NAND flash memory, data is written and read in page units and erased in block units as described above. As shown in FIG. 22A, when the cell array is not divided, 256 bytes of memory cells connected to one word line form one page. As shown in FIG. 22B, when the cell array is divided into two, for example, among the divided cell arrays, the memory cells connected to the word lines of one cell array form one page.

The operation of the NAND type EEPROM is as follows, for example. Data is written in order from the memory cell farther from the bit line. The boosted write voltage V _PP (= 20) is applied to the control gate of the selected memory cell.
V) is applied, and an intermediate potential (= about 10 V) is applied to the control gates and the first selection gates of other non-selected memory cells.
Is applied. 0V (“0”) depending on the data on the bit line
Write) or an intermediate potential ("1" write) is applied.

At this time, the potential of the bit line is transmitted to the selected memory cell. When the data is “0”, a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are tunnel-injected from the substrate to the floating gate, and the threshold voltage moves in the positive direction. When the data is "1", the threshold voltage does not change.

Data erasing is performed in block units at substantially the same time. That is, all the control gates and select gates of the block to be erased are set to 0V, and the boosted potential V _PPE (about 20V) is applied to the p-type well and the n-type substrate. V _PPE is also applied to the control gates and select gates of blocks that are not erased. By applying the voltage in this way, the electrons of the floating gate of the memory cell are emitted to the well, and the threshold voltage moves in the negative direction.

The data read operation is performed as follows.
After precharging the bit lines, the bit lines are brought into a floating state, the control gates of the selected memory cells are set to 0V, and the control gates and selection gates of the other memory cells are set to the power supply voltage V.
_{With CC} (for example, 3 V) and the source line set to 0 V, it is detected in the bit line whether or not a current flows through the selected memory cell.

That is, if the data written in the memory cell is "0" (threshold _Vth > 0 of the memory cell), the memory cell is turned off, so that the bit line keeps the precharge potential, but "1". "(Threshold _Vth <0 of memory cell)
Then, the memory cell is turned on and the bit line drops from the precharge potential by ΔV. The data of the memory cell is read by detecting these bit line potentials with a sense amplifier.

[0018]

Conventional NAND type EE
In a semiconductor memory device including a PROM, a write operation is simultaneously performed on memory cells connected to the same word line (control gate). Therefore, the larger the number of memory cells (page size) connected to the same word line, the faster the writing speed per byte.

However, as the page size increases, the erase size (block size) also increases, and the number of blocks included in one chip decreases. As a result, in a case of storing a large amount of small-capacity data such as storing data only in a part of one block which is a unit of erasing, as the page size and the block size are increased, There has been a problem that the number of data that can be stored in the memory decreases.

If the page size and block size change as the memory capacity of the non-volatile semiconductor memory device increases, the intergenerational compatibility of the memory is lost. Therefore, there is a problem that the design of the system using the memory has to be changed every generation if the page size or the block size changes.

[0021]

In a semiconductor memory device according to the present invention, electrically rewritable memory cells are arranged in a matrix, and a plurality of memory cell pages, which are units composed of a plurality of memory cells, are provided. In a semiconductor memory device including a sub cell array including the sub cell array and a memory cell array including the plurality of sub cell arrays, a plurality of memory cell pages in the same sub cell array are simultaneously selected in reading or writing. It is characterized by

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of a semiconductor memory device according to the first embodiment of the present invention.
In the first embodiment, the memory cell array is divided into four sub cell arrays A, A, B, C, and D.

In FIG. 1, SA _A , SA _B , SA _C , S
A _D is a data circuit of each sub cell array, which selects a bit line to input write data or holds data read from a memory cell at the time of writing and reading. In particular, data may be written or read directly to the outside without providing a data circuit. RD _A , RD _B , RD _C and RD _D are row decoders, and select a control gate and a selection gate.

FIG. 2 shows the data circuit SA _x (x: A,
B, C, D) are specific examples. For example, bit line BL ₀ ,
The sense amplifier SA ₂ to which BL _0Z is connected and its peripheral circuit are shown. This sense amplifier SA ₂ also serves as a data latch circuit. The sense amplifier SA ₂ is activated by the sense amplifier activation signals Φ _N and Φ _P.

A transistor Q31 is connected between the node N1 of the sense amplifier SA ₂ and the data line / IO,
A transistor Q is provided between the node N2 and the data line IO.
32 is connected. These transistors Q31 and Q32 are used for the column selection signal CSL ₂ supplied from the column decoder.
Controlled by.

The nodes N 1 and N of the sense amplifier SA ₂
Transistors Q33 and Q34 controlled by the equalize signal Φ _E are connected between the two. A power supply Vcc / 2 is supplied to the interconnection point of these transistors Q33 and Q34. Transistor Q by equalizing signal Φ _E
When 33 and Q34 are turned on, the nodes N1 and N2 are connected to the power source Vcc.
Equalized to / 2.

A transistor Q35 controlled by the bit line selection signal SS ₂ and a sense amplifier selection signal S _A are provided between the bit line BL ₀ and the node N 1 of the sense amplifier SA _2.
A transistor Q36 controlled by is connected.
In addition, the bit line BL _0Z and the node N of the sense amplifier SA ₂
A transistor Q37, which is controlled by the bit line selection signal SS ₂ is between 2, transistor Q38 is connected to be controlled by a sense amplifier selection signal S _B.

A transistor Q39 controlled by the precharge signal PR _A1 is connected between the interconnection point of the transistors Q35 and Q36 and the power supply terminal 31. The power supply terminal 31 is supplied with the precharge voltage V _A1 .
The transistor Q39 precharges the bit line BL ₀ according to the precharge signal PR _A1 .

A transistor Q40 controlled by a precharge signal PR _B1 is connected between the interconnection point of the transistors Q37 and Q38 and the power supply terminal 32. The power supply terminal 32 is supplied with the precharge voltage V _B1 .
The transistor Q40 precharges the bit line BL _0Z according to the precharge signal PR _B1 .

Transistors Q41 and Q42 are connected between the interconnection point of the transistors Q35 and Q36 and the power supply terminal 33. The verify voltage V _rA is supplied to the power supply terminal 33. The gate of the transistor Q41 is connected to the node N1, to the gate of the transistor Q42 is supplied with a verify signal VRFY _A.

Transistors Q43 and Q44 are provided between the interconnection point of the transistors Q37 and Q38 and the power supply terminal 34.
Are connected. The verify voltage V is applied to the power supply terminal 34.
_rB is supplied. The gate of the transistor Q43 is connected to the node N2, and the verify signal VRFY _B is supplied to the gate of the transistor Q44.

<Read Operation> Now, the read operation will be described with reference to a timing chart.

FIG. 3 is a timing chart for reading the data written in the memory cell MC ₁ of FIG. First, the precharge signals PR _A1 and PR _{B1 change} from V _SS to V _CC (time t ₀ ), and the bit line BL ₀ changes to V _A1 (for example, 1.
7 V), and the (dummy) bit line BL _0Z is precharged to V _B1 (for example, 1.5 V) (time t ₁ ).

PR after precharge_A1, PR_B1But
V_SSAnd the bit line BL₀, BL _0ZIs floating
It becomes a state. After this, the row decoder selects
A desired voltage is applied to the gate (time t₂). control
Gate CG_1AIs 0V, CG_2A~ CG_8AIs V_CC(Eg 3
V), SG_2AIs 3V, SG_1AIs 3V.

When the data written in the memory cell MC ₁ is “0”, the threshold voltage of the memory cell is positive, so that no cell current flows and the potential of the bit line BL ₀ remains 1.7V. . When the data is "1", the cell current flows and the potential of the bit line BL ₀ drops to 1.5 V or less. During this time, the (dummy) bit line BL _0Z is kept at the precharge potential of 1.5V.

Thereafter, at time t ₃ , Φ _P is 3 V and Φ _N is 0.
V, the CMOS flip-flop FF is inactivated, and Φ _E becomes 3 V at time t ₄ , so that C of SA ₂
The MOS flip-flop FF is equalized so that the nodes N1 and N2 become V _CC / 2 (for example, 1.5 V). At time t ₅ , SS ₂ , S _A , and S _B become 3V, and after the bit line and the sense amplifier are connected, Φ _N changes from 0V to 3V, Φ _P
Changes from 3V to 0V, and bit line BL ₀ and bit line BL
The potential difference of _0Z is amplified (time t ₆ ).

That is, if "0" is written in the memory cell MC ₁ , the node N 1 of SA ₂ is 3V and the node N is
2 is to 0V, and if "1" to the memory cell MC ₁ is written, the node N1 is 0V, the node N2 becomes 3V. After that, when the column selection signal CSL ₂ changes from 0V to 3V, the data latched in the CMOS flip-flop is output to IO and / IO (time t ₇ ).

<Write Operation> Here, the write operation will be described with reference to a timing chart. FIG. 4 shows a memory cell MC
FIG. 6 is a timing chart when ₁ is written. Memory cell M
The data written to C ₁ is the sense amplifier circuit (S in FIG. 2).
Latched to A ₂ ). In other words, when "0" is written, the node N1 is 0V, N2 is 3V, and when "1" is written, the node N1 is 3V and N2 is 0V.

When the write operation is started, first, time t₁To S
G_1ATo V_SS, SG_2A, CG_1A~ CG _8ATo V_CCTo B
Line BL₀Is the sense amplifier circuit SA₂Latched in
V according to the data_CCOr V_SSGiven a potential of (0V)
It Thereby, for example, the memory cell MC₁"0" writing on
In case of imprinting, bit line BL₀To 0V
Morisell MC₁Will be set to 0V. Me
Morisell MC₁Bit when writing "1" to
Line BL₀To V_CC(Eg 3V) and memory cell MC₁
Channel of V_CC-V_thWill be charged to. Selective
SG_1AIs 0V, SG_1ASelect M with the gate electrode
The OS transistor is off.

When "0" is written in the memory cell MC ₁ , the channel of the memory cell is kept at 0V.
The channel of the memory cell in which "1" is written becomes floating. At time t ₂ , the control gates CG _{1A to} CG _8A are set to V _CC.
To an intermediate potential V _M (about 10 V). Then,
Since the channel of the memory cell MC _{1 in} which "1" is written is in a floating state, V _CC -V _th rises to an intermediate potential (about 10 V) due to capacitive coupling between the control gate and the channel. Memory cell MC for writing "0"
The channel of ₁ is 0V because the bit line is 0V.

At the time t ₃ after the channel of the memory cell in which "1" is written is boosted from V _CC -V _th to the intermediate potential.
The control voltage CG _1A from the intermediate potential V _M to the write voltage V
Boost to _PP (20V). Then, the channel of the memory cell MC _{1 in} which "1" is written has an intermediate potential (10 V).
However, since the control gate CG _1A is V _PP (about 20 V), these memory cells are not written, but the channel of the memory cell MC _{1 in} which “0” is written is 0 V, and the control gate is V _PP (about 20 V). Therefore, electrons are injected from the substrate to the floating gate and "0" writing is performed. After the writing is completed, the control gate, the selection gate, and the bit line are sequentially discharged to complete the writing operation.

After the writing is completed, a write verify operation for checking whether or not the writing is sufficiently performed is performed.

FIG. 5 shows a timing diagram of the write verify operation. First, the precharge signals PR _A1 and PR _B1 are changed from V _SS to V _CC (time t ₄ ), and the bit line BL ₀ is V
_A1 (for example 1.7V), and (dummy) bit line BL
_0Z is precharged to V _B1 (for example, 1.5 V) (time t ₅ ).

PR when precharge ends_A1, PR_B1But
V_SSAnd the bit line BL₀, BL _0ZIs floating
It becomes a state. After this, the row decoder selects
A desired voltage is applied to the gate (time t₆). control
Gate CG_1AIs 0V, CG_2A~ CG_8AIs V_CC(Eg 3
V), SG_2AIs 3V, SG_1AIs 3V. Memory cell
MC₁If the data written to is 0,
Since the cell threshold voltage is positive, no cell current flows,
Line BL₀Potential remains at 1.7V. The data is
In the case of "1", the cell current flows and the bit line BL₀Electric power
The rank goes down to less than 1.5V.

After bit line discharge, verify signal VRFY
_{When A} becomes 3V (time t ₇ ) and the data written in the memory cell MC ₁ is “1”, the bit line BL
₀ is charged near 3V. Here, the voltage level of the charging performed by the verify signal may be 1.5 V or more of the precharge voltage of the bit line BL _0Z . During this time, the (dummy) bit line BL _0Z has a precharge potential of 1.5V.
Kept in.

After that, at time t ₈ , Φ _P is 3 V and Φ _N is 0.
V, the CMOS flip-flop FF is inactivated, and Φ _E becomes 3 V at time t ₉ , so that C of SA ₂
The MOS flip-flop FF is equalized so that the nodes N1 and N2 become V _CC / 2 (for example, 1.5 V). At time t ₁₀ , SS ₂ , S _A and S _B become 3V, and after the bit line and the sense amplifier are connected, Φ _N changes from 0V to 3V, Φ _P
Changes from 3V to 0V, and bit line BL ₀ and bit line BL _0Z
The potential difference is amplified and the rewritten data is latched by the sense amplifier (time t ₁₁ ).

FIG. 6 shows a circuit configuration of the sub cell array A. The word lines of each block forming the sub cell array A are shown as CG _1A to CG _8A . In FIG. 6, for the sake of convenience of explanation, reference numerals are given to the word lines in the block 1A.
A set of memory cells each having a control gate connected to each word line corresponds to one page, and each page is described as (Page 1A) to (Page 8A) overlapping with the code of the word line.

The sub-cell array A is similarly composed of blocks 0 _A , 1 _A , 2 _A , etc., each consisting of eight pages, and the circuit configuration of the sub-cell arrays B, C, D is simply shown in FIG. It corresponds to the case where A in the inside is replaced with B, C, and D.

The sub cell array shown in FIG. 1 is composed of columns of 256 bytes each. That is, the number of bit lines (number of columns) per sub cell array is 256 ×
(8). In the first embodiment, as described below, the number of memory cell pages simultaneously selected can be made variable during writing and reading.

For example, when the memory cell pages 1 _A included in one sub cell array A are selected at the same time, FIG.
The read and write page sizes are 25 as shown in
It is 6 bytes. On the other hand, when the memory cell pages 1 _A and 1 _B included in the sub cell arrays A and B are selected at the same time and the memory cell pages 1 _C and 1 _D included in the sub cell arrays C and D are selected at the same time, read and write operations are performed. The page size is 512 bytes.

In addition, the memory cell pages 1 _A , 1 _B and 1 _C included in the sub cell arrays A, B and C can be simultaneously selected to make the page size 768 bytes.
The memory cell pages 1 _A , 1 _B , 1 _C and 1 _D included in the sub cell arrays A, B, C and D can be simultaneously selected to make the page size 1024 bytes.

When two sub-cell arrays are activated at the same time during writing and reading, erasing may be performed for each sub-cell array or may be performed for two sub-cell arrays at the same time.

That is, by using a memory cell array divided into sub cell arrays, the number of memory cell pages can be changed by simultaneously selecting memory cell pages belonging to a plurality of sub cell arrays at the time of writing and reading as described above. can do. At this time, the simultaneously selected memory cell pages have different word lines, and the simultaneously selected memory cell pages can be set by the word lines.

The process of writing, reading, and erasing data in the first embodiment will be described in more detail. As shown in FIG. 1, the states of writing, reading, and erasing when the page size is 256 bytes are shown in FIGS.
It is shown in FIG. A ₀ , A ₁ , ..., A ₂₅₅ in FIGS.
Each represent 1-byte data.

In the first embodiment, eight data input / output lines (I / O buses) with the outside of the chip are formed. In FIG. 7 etc., it is shown by one line for simplicity.

Writing is performed as shown in FIGS.
256 bytes (A ₀, A₁, ..., A
₂₅₄, A₂₅₅) Data is, for example, in the sub cell array A
CG _1AWrite to memory cell selected by (page 1A)
If it happens, the next 256 bytes are CG_2ATo choose
The next 256 bytes in the memory cell (page 2A) are CG
_3AThe memory cell (page 3A) selected by
Byte is CG_4AMemory cell (page 4A) selected by
As shown by the arrow in FIG. 7,
It is written in the memory cell in the sub cell array A.

Reading is performed as shown in FIGS.
That is, if the memory cell (page 1A) selected by CG _1A in the sub cell array A shown in FIG. 6 is read, the memory cell selected by CG _2A (page 2A) is read next, and the CG is next read. _The memory cell selected by _3A (page 3A) is read, the memory cell selected by CG _4A (page 4A) is read next, and so on from the memory cell in the sub-cell array A as shown by the arrow in FIG. Read out.

Data writing and reading are performed here by the data circuit SA _A belonging to the sub cell array _A (see FIG. 1).
It may be done via the Internet or directly with the outside. Erasing may be performed in each block unit of each sub-array as shown by the broken line in FIG. 9, or may be performed simultaneously in blocks in a plurality of sub-arrays.

Write, read, and erase processes when the page size is 1024 bytes are shown in FIGS.
Shown in 2. A ₀ , A ₁ , ..., A ₁₀₂₃ in FIGS.
Each represent 1-byte data. There are eight data input / output lines (I / O bus) with the outside of the chip. When the page size is 1024 bytes, the sub cell array A, the sub cell array B, the sub cell array C, and the sub cell array D are simultaneously selected.

Writing is performed as shown in FIG. 256 bytes from the start address (A ₀ , A ₁ , ..., A ₂₅₅ )
To the data circuit SA _A (see FIG. 1) in the sub-array A, the next 256 bytes to the data circuit SA _B , the next 256 bytes to the data circuit SA _C , and the next 256 bytes to the data circuit SA _D. store. Then, based on the data of the data circuit, the memory cell selected by CG _1A (page 1
A), memory cells selected by CG _1B (page 1B), C
Writing is simultaneously performed to the memory cell selected by G _1C (page 1C) and the memory cell selected by CG _1D (page 1D). Therefore, the write operation is about 4 times faster than the case where the page size is 256 bytes.

Next, the read operation will be described with reference to FIGS. As shown in FIG. 13A, when the page size is 256 bytes, random read is always necessary before serial read of each page. Therefore 102
When reading 4-byte data, four random reads and four serial reads are required.

On the other hand, when the page size is 1024 bytes, CG _1A , CG _1B , CG _1C and CG _1D are selected at the same time, so random read is only required once. That is 1
After random reading, page 1A, 1 without interruption
B, 1C, and 1D data can be output to the outside. Therefore, even in the case of reading, the read operation is speeded up by increasing the page size. At this time, the write and read operations of the pages 1A, 1B, 1C, and 1D can be performed simultaneously with the outside directly without passing through the data circuit.

Next, the erase operation will be described with reference to FIG. When deleting data in 1024-byte units,
Page 1A, page 1B, page 1C, page 1D are erased simultaneously. That is, block 1A, block 1
Since B, block 1C, and block 1D are erased at the same time, the number of memory cells erased at the same time is four times that in the case where the page size is 256 bytes.

The page size is 256 bytes and 102
Although the write, read, and erase operations have been described for the case of 4 bytes, the page size may be doubled by making two sub cell arrays activated at the same time, or three sub cell arrays are activated at the same time. In this way, the page size may be tripled.

Further, as shown in FIG. 7, when all the data of 1024 bytes is written in the block 1A included in the sub cell array A, only the block 1A is erased as shown in FIG. Good, erase unit is 2
The size can be reduced to 56 bytes × 8 (CG _{1A to} CG _8A ). By reducing the page size to 256 bytes, the number of memory cells to be erased at the same time can be reduced.

That is, when the page size is increased, writing and reading are speeded up, but the number of memory cells to be erased simultaneously increases. Therefore, in an application where the capacity of one data is small (for example, 256 bytes or less), it is better to reduce the erase unit by reducing the page size. The volume of one data is large (for example, 10
For use in Kbytes, it is advantageous to increase the page size to speed up writing and reading.

Next, as a second embodiment, writing,
A control method for varying the read page size will be described.

For example, in the first mode, page 1A in sub cell array A in FIG. 1 is selected, in the second mode, pages 1A and 1B in sub cell arrays A and B are selected, and in the third mode. , Pages 1A, 1B, and 1C in the sub cell arrays A, B, and C are selected, and in the fourth mode, page 1 in the sub cell arrays A, B, C, and D is selected.
If A, 1B, 1C, and 1D are selected, 256 bytes, 512 bytes, 768 bytes, and 1024 bytes of data can be simultaneously written and read by selecting the first to fourth modes. You can

The page size may be controlled by a command from outside the flash memory. If control by commands is possible, the user of the flash memory can freely change the page size according to the application.

Further, pages having different page sizes on one chip may simultaneously exist in the memory cell array. For example, as shown in FIG. 14, when the write data is 256 bytes or less (data 1 in FIG. 14), the page size is written to page 1A (CG _1A ) as 256 bytes, and the write data is, for example, 768 bytes ( Figure 1
The data 2) of 4 may be written in page 1B (CG _1B ), page 1C (CG _1C ), and page 1D (CG _1D ) with a page size of 768 bytes.

As shown in FIG. 15, after writing data of 256 bytes or less (data 3 of FIG. 15) to page 1A (CG _1A ) with a page size of 256 bytes, for example, data of 1024 bytes (data 4 of FIG. 15). ) As the page size of 1024 bytes and page 1B (C
G _1B ), page 1C (CG _1C ), page 1D (C
G _1D ) and page 2A (CG _{2A in} FIG. 6) may be written.

There are various modes of changing pages and writing methods. Also, the page size may be fixed when the chip is shipped. The page size can be changed by changing the address setting method. The address can be easily changed by cutting the fuse provided in a part of the address decoder circuit in the chip or changing the pattern of the metal wiring (Al or the like).

Therefore, for example, each page size is 2
56 bytes, 512 bytes, 768 bytes, and 1024 bytes are all designed in the same way, and fuses in the chip are cut off before the chip is shipped, or only the metal wiring pattern is changed to make chips with different page sizes. You may In this case, the design of the semiconductor memory device is the same regardless of the page size, so that the cost can be significantly reduced as compared with the case of designing chips of various page sizes.

Next, as a third embodiment of the present invention, speeding up of the write operation when writing data to the sub cell array via the data circuit will be described. In the write operation, as soon as the write data is input to the data circuit of one sub cell array, the data may be written to the sub cell array.

That is, when writing data as shown in FIG. 10, first, write data of page 1A is input to the data circuit SA _A of the sub cell array A shown in FIG. When the data input to the data circuit SA _A is completed, the write data of the page 1B is next input to the data circuit SA _B of the sub cell array B, while the data from the data circuit SA _A to the page 1A of the sub cell array A is input. The writing operation may be started.

Similarly, when the input of the write data to the page 1B of the sub cell array B to the SA _B is finished, the write data to the page 1C is input to the data circuit SA _C of the sub cell array C at the same time. Writing to page 1B of sub cell array B may be performed.

SA of write data of sub cell array C
_When the input to _C is completed, page 1 of sub cell array D
At the same time when the write data to _D is input to SA _D , page 1C of the sub cell array C may be written.
SA of write data of page 1D of sub cell array D
_When the input to _D is completed, if writing to another sub cell array, for example, page 1A of the sub cell array A is completed, the data circuit SA of the sub cell array A is written.
_The write data may be input to _A to write the next page (page 2A) of the sub cell array A.

After the write data is input to the data circuit in this manner, while writing data is input to another data circuit, writing is performed in the column in which the write data has already been input to the data circuit, thereby speeding up writing. can do.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

The page size can be easily changed by changing the address. The circuit configuration of the address selection circuit will be described below. The structure of the memory cell array is as shown in FIG. 1 and is divided into four sub cell arrays. FIG. 16 shows column addresses and row addresses (page addresses) in the sub cell array A.

The column address for selecting the bit line is
C in the bus array A₀To C₂₅₅, Sub cell array B
Then C₂₅₆To C₅₁₁, In the sub cell array C₅₁₂Or
Et C ₇₆₇, C in the sub cell array D₇₆₈To C₁₀₂₃And
It Page address of the sub-cell arrays B, C, D (row
Address) is the same as the page address in FIG.
I just replaced suffix A with B, C, D
Of. Eight I / O lines (I / O lines) with the outside
O₀From I / O₇There is one column address.
Depending on the column, 8 columns (8
Book bit lines) are simultaneously selected.

As described above, since column addresses for different columns (bit lines) are assigned to each I / O, any column can be selected. Therefore, when the page size is 256 bytes, write data may be input after the write data is sequentially input to the data circuits of the column addresses C ₂₅₆ to C ₅₁₁ of the sub cell array B. When the page size is 1024 bytes, writing may be performed after the write data is sequentially input to the data circuits of the column addresses C ₀ to C _{10 24} .

The write data may be input in the reverse order of the serial read. That is, column addresses are sequentially selected by a counter or the like, and write data is input to the data circuit from outside the chip. The operation of inputting write data in serial is Y.Iwata et al .: IEE
E J. Solid-state Circuits, vol.30, no.11, p.1157 Nov
ember 1995 has a detailed explanation.

Each sub cell array is composed of 512 blocks, and one block has 16 pages (16 control gates).
Composed of. The row address (page address in FIG. 16) designates the control gate in each sub cell array, and in sub cell array A, P _0A to P _{81 91A} , sub cell array B
, P _0B to P _8191B , P _0C to P _{8191C in} the sub cell array C, and P _0D to P _{8191D in the} sub cell array D.

When the page size is 256 bytes,
For example, P of the sub cell array C_4000CSelect. page
If the size is 512 bytes, the sub cell array A,
For example, in P_5000A, P_5000BSelect. Page service
If the size is 1024 bytes, the sub cell array A,
For example, P of B, C, D_2000A, P_2000B, P_2000C, P
_2000DSelect.

17 and 18 show an example of a row (page) selection circuit for selecting the selection gate and the control gate. Figure 1
Although 8 is an example in which memory cells of 2 columns are connected per bit (see Japanese Patent Application No. 6-218031), the row selection circuit is almost the same regardless of the configuration of the memory cell array and the type of memory cell. Here, of the row selection circuit, only the circuit components different from the above example will be described in detail.

As shown in FIG. 17, the row address in each sub cell array is selected by the external addresses A _d0 to A _d12 . That is, using A _d0 to A _d12 , P _nx (n is 0,
1, 2, ..., 8189, 8190, 8191, where x
Selects A, B, C, D). A _d0 , A _d1 , A _d2 , A
_d3 is a common control gate C of the NAND cells in each block
Select _{one of} G ₁ to CG ₁₆ . A _{d4 to} A _d12 select blocks 0 to 511 in each sub cell array.

In the row predecoder of FIG. 17, T _o , S _p and U _q are selected according to the input external address.

FIG. 18 shows a block address decoder 1
A transfer gate bias circuit 2 which receives an output from the address decoder and applies a desired voltage to the gates of transfer gates (eg, Qh21, Qh22, Qh25) of the row decoder, a block 3 composed of NAND cells, and a control gate voltage (VCG). _{1 to} VCG ₆ ), select gate voltage (VSGD _1,2 , VSGS _1,2 ) control gate (CG ₁
To CG ₁₆ ) and a transfer gate circuit 4 for transferring to selection gates (SGD _1,2 , SGS _1,2 ).

In FIG. 18, the block address decoder 1 includes p-channel transistors Qp1 to Qp4, Qp30, n.
Channel transistors Qn1 to Qn3, Qn30 Fuse F,
It is composed of inverters I ₁ and I ₂ and NOR gates G ₁ and G ₂ . Each sub cell array has SB _x (x is A, B,
C or D) and Qp30 and Qn30. That is, the sub-cell array selection signals SB _A , SB _B , SB _C and SB _D are input to the block address decoders in the sub-cell arrays A, B, C and D, respectively. S
The sub-cell array in which B _x is “L” is in the non-selected state, the output N ₁ of the block address decoder is “L” when the block selection signal RDENBB is “L” regardless of T _o , S _p and U _q .

At this time, the sub-decoder activation inversion signal RDE
When NBBD is "L", the signal Φ is "H". As a result, SGD ₁ , SGD ₂ , SGS ₁ , and SGS ₂ are set to 0 V, and writing and reading are not selected.

[0093] sub-cell arrays of SB _x is "H" will be in the selected state, block selected in the sub-cell array signal T _o,
A block is selected by S _p and U _q . Fuse f
If There has been disconnected, or the block address signal T _o, in the case of S _p, 1 any time of the U _q "L" is
When RDENBB is "L", the output N1 of the block address decoder is "L" and the block is in the non-selected state.

[0094] On the other hand, the fuse F is not cut, when the block address signal T _o, S _p, U _q are all "H", the output of the block address decoder N1 becomes "H", the block is selected .

In FIG. 18, since one bit line is shared by memory cells of two columns, four select gates (SGD ₁ , S
GD ₂ , SGS ₁ , SGS ₂ ). 1 as shown in FIG.
Even if there is one bit line per memory cell in the column, the block selection method by the block address decoder is the same.

When the page size is 256 bytes,
SB_A"H", SB_B, SB_C, SB_DTo
When set to "L", only the sub cell array A is selected.
If the page size is 1024 bytes,
If SB_A, SB_B, SB_C, SB _DBoth to "H"
The same block in all subarrays by
Within the same page (eg P_1000A, P_1000B,
P_1000C, P_1000D) Is selected.

In the fourth embodiment, a plurality of sub sessions are used.
If you want to select all
Same page, eg P_1000A, P_1000B, P_1000C, P
_{1000 D}Is selected, but memory cells on different pages are selected.
May be selected. Ie P _1000A, P_1500B, P
_1800C, P_2000DMay be selected at the same time. See also FIG.
P like 5_1001B, P_1001C, P_1001D, P_1000ABut
It may be selected.

As described above, the method of combining the blocks selected at the same time is highly arbitrary.

For example, in erasing, block 0 and block 1 in sub cell array A, block 100 in sub cell array B, block 250, block 280, and block 490 in sub cell array D may be simultaneously erased.

When the page size is 512 bytes,
The sub cell array A and the sub cell array B may be simultaneously selected, and the sub cell array C and the sub cell array D may be simultaneously selected.

As described above, SB _x (x is A,
The page size can be easily changed by selecting B, C, or D). If the user of the flash memory can control the SB _x by a command from the outside of the chip, the user can freely change the page size according to the purpose.

The page size may be fixed when the chip is shipped. That is, the number of sub-cell arrays simultaneously selected (that is, the number of SB _X that becomes “H” at the same time) can be determined by cutting the fuse in the chip or changing the pattern of metal wiring such as Al.
In this way, chips with various page sizes can be easily provided.

The present invention is not limited to the above embodiment. In the above description, the case where all NAND type memory cells are used has been described.
The same can be applied to various memory cells such as DINOR type, AND type and Virtual Ground type.
In addition, the mask ROM, DRAM, and SRAM can be implemented.

[0104]

As described above, according to the semiconductor memory device of the present invention, writing, reading and the like are simultaneously performed by the user inputting a command from the outside or by adding a few steps at the shipping stage. Since the page size can be freely selected, by preparing a standardized element having a plurality of sub cell arrays, the unit of writing, reading, and erasing can be optimally determined according to the application in individual system design. Yes, you can achieve the best system performance. Also, advantageous results can be obtained in terms of device compatibility between generations.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a memory according to the present invention.

FIG. 2 is a diagram showing an example of a data circuit.

FIG. 3 is a timing chart of data reading.

FIG. 4 is a timing chart of data writing.

FIG. 5 is a timing diagram of a write verify operation.

FIG. 6 is a diagram showing a configuration of a sub cell array A.

FIG. 7 is a diagram showing a write operation when the page size is 256 bytes.

FIG. 8 is a diagram showing a read operation when the page size is 256 bytes.

FIG. 9 is a diagram showing an erase operation when the page size is 256 bytes.

FIG. 10 is a diagram showing a write operation when the page size is 1024 bytes.

FIG. 11 is a diagram showing a read operation when the page size is 1024 bytes.

FIG. 12 is a diagram showing an erase operation when the page size is 1024 bytes.

[FIG. 13] When the page size is 256 bytes and 10
The figure explaining the read-out operation in case of 24 bytes.

FIG. 14 is a diagram showing an example of a data structure of the present invention.

FIG. 15 is a diagram showing an example of another data configuration of the present invention.

FIG. 16 is a diagram showing an example of addresses of the sub cell array A of the present invention.

FIG. 17 is a diagram showing an example of a row predecoder of the present invention.

FIG. 18 is a diagram showing an example of a row decoder of the present invention.

FIG. 19 is a plan view and an equivalent circuit diagram showing a cell configuration of a NAND type EEPROM.

FIG. 20 is a cross-sectional view of a NAND-type EEPROM cell.

FIG. 21 is an equivalent circuit diagram of a memory cell array of a NAND type EEPROM.

FIG. 22 is a block diagram of a memory.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Block address decoder 2 ... Transfer gate bias circuit 3 ... NAND cell 4 connected in parallel with two columns 4 ... Transfer gate circuit 5 ... Silicon substrate 6 ... Element isolation oxide film 7 ... Gate insulating film 8 ... N ⁺ diffusion layer 9 ... Oxide film 10 that insulates the floating gate from the control gate ... CVD oxide film 11 ... Bit line 14 ... Floating gate 16 ... Select gates M _{1 to} M ₁₆ , MC ₁ ... Memory cells PR _A1 , PR _A2 ... Precharge signal S ₁ , S ₂ ... Drain-side selection transistors S ₃ , S ₄ ... Source-side selection transistors 14 _{1 to} 14 ₈ ... Floating gates 14 ₉ , 14 ₁₀ , 16 ₉ , 16 ₁₀ ... Drain-side and source-side selection gates 16 _{1 to} 16 ₈ Control gates 0 _{A to} 511 _A Block numbers 0 _{B to} 511 _{B of} sub cell array A Block numbers 0 _{C to} 511 _{C of} sub cell array B Buseruarei C block number 0 _D ~511 _D ... sub cell arrays D block numbers RD _{A of, RD B, RD C, RD} D ... sub-cell array A,
B, C, D row decoders SA _A , SA _B , SA _C , SA _D ... Sub cell array A,
B, C, D data circuits SA ₂ ... Sense amplifier circuits 1A, 1B ... Memory cells and dummy cells Φ _P , Φ _N ... CMOS flip-flop activation signal Φ _E ... CMOS flip-flop equalization signal CSL ₂ ... Column selection signal PR _A1 , PR _B1 ... Precharge signals V _A1 , V _B1 ... Precharge voltages SS ₂ , S _A , S _B ... Sense amplifier and bit line connection signals VRFY _A , VRFY _B ... Verify signals V _rA , V _rB ... Verify Voltages CG _{1A to} CG _8A ... Control gates SG _1A and SG _{2A of} sub cell array A ... Select gates CG _{1 to} CG _{16 of} sub cell array A ... Control gates SGD ₁ , SGD ₂ and SG ₁ ... Drain side select gates SGS ₁ and SGS _2, SG ₂ ... source-side selection gate VSGD _1, VSGD ₂ ... voltage VSGS ₁ of the drain side select gate, VSGS ₂ ... saw The control gate lines constituting a page of the voltage CG _1A ~CG _8A ... block 1A voltage VCG ₁ ~VCG ₁₆ ... control gate side selection gate BL, BL ₀ ~BL ₆₃ ... bit lines BL _0Z ... dummy bit lines BL _0A ~ BL _63A ... Bit lines A _{0 to} A _{1023 in the} sub cell array A ... Data P _{0A to} P _8191A from the start address to 1024 bytes ... _Rows (pages) in the sub cell array A
Address C ₀ -C ₂₅₅ ... column address A _d0 ~A _d3 ... NAND address A _d4 to A _d12 ... block addresses T ₀ in the sub-cell array A, S _p, the output of U _q ... row predecoder Q31～Q44 ... transistor Qp1 ~Qp4, Qp30 ... p-channel transistor Qn1~Qn3, Qn30 ... n-channel transistor Qh21, Qh22, Qh25 etc ... high voltage transistor F ... fuse I _1, I ₂ ... inverter G _1, G ₂ ... NOR gate SB _x (x = A, B, C, D) ... Sub-cell array selection signal RDENBB ... Block selection signal RDENBBD ... Sub-decoder activation inversion signal

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5B025 AA03 AB01 AC01 AD01 AD02                       AD03 AD04 AD05 AD06 AD09                       AE00

Claims (6)

[Claims] 1. A sub-cell array comprising electrically rewritable memory cells arranged in a matrix and including a plurality of memory cell pages, which is a unit composed of a plurality of memory cells, and the plurality of sub-cell arrays. In a semiconductor memory device including a memory cell array including the semiconductor memory device, a plurality of the memory cell pages in the same sub cell array are simultaneously selected at the time of reading or writing. 2. A corresponding address is allocated to each of the memory cell pages, and when reading or writing, the plurality of memory cell pages are simultaneously selected by the plurality of arbitrary address signals. The semiconductor memory device according to claim 1. 3. The semiconductor memory device according to claim 1, wherein when reading or writing, a plurality of the memory cell pages are simultaneously selected in any one of the plurality of sub cell arrays. . 4. The sub cell array comprises a plurality of blocks including a predetermined number of the memory cell pages, and at the time of erasing, a plurality of the blocks in the same sub cell array are simultaneously selected. The semiconductor memory device according to any one of claims 1 to 3. 5. The sub cell array includes a plurality of blocks including a predetermined number of the memory cell pages, and when erasing, a plurality of the blocks are included in any one of the plurality of sub cell arrays. The semiconductor memory device according to claim 4, wherein the semiconductor memory devices are selected at the same time. 6. The sub cell array comprises a plurality of NANDs.
6. A mold cell comprising a mold cell.
The semiconductor memory device described.