JP2003140598A - Plasma display device, its drive circuit and drive method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a plasma display device in which highly efficient light emitting display is realized using a simple method and to provide its drive circuit and its drive method. SOLUTION: A data pulse power supply and an RF (radio frequency) power supply are connected to a data driver in a changeover manner. The data driver generates data pulses corresponding to video data in an address interval based on a data pulse power supply voltage, outputs the data pulses to an address electrode 13 and outputs high frequency pulses from the RF power supply in a sustain interval. In the sustain interval, discharging is maintained in a high frequency electric field, energy loss due to the heating by electrons or the like is reduced, highly efficient Xe excitation is conducted and light emitting efficiency is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device for displaying by using AC plasma discharge, a driving circuit for the same, and a driving method.

[0002]

2. Description of the Related Art Plasma display (PDP: Plasma)
The Display Panel) has attracted attention as a display that can be made thinner and has a larger screen in recent years.
Commercialization has begun as a wall-mounted TV with a large screen of over an inch. The display panel of the PDP has a structure in which two glass substrates are attached to each other, and a pair of sustain electrodes is formed on the front glass substrate and an address electrode is formed on the rear glass substrate in a direction intersecting with the sustain electrodes. Are arranged respectively. A discharge gas composed of Xe, Ne, etc. is sealed between the two substrates, and in the case of color display,
The Xe gas excited by the electric field formed between the pair of sustain electrodes emits ultraviolet rays, which are irradiated to the phosphors of the respective colors to emit light.

A general PDP is digitally controlled and is driven by the subfield method. In the subfield method, as shown in FIG.
The display screen of the field is time-divided into several subfields, and gradation control is performed by controlling light emission for each subfield. That is, the brightness modulation is represented by the modulation of the display time width. At this time, the display period of one field is divided into N subfields that emit light the number of times weighted according to the bit digit of N-bit pixel data. For example, when the pixel data per pixel is 8 bits, the display period of one field is divided into eight subfields SF1 to SF8. At this time, the number of times of light emission in each of the subfields SF1 to SF8 is 2 depending on the bit digit.
⁰ (1), 2 ¹ (2), 2 ² (4), ..., 2 ⁷ (128) times are set, and 256 gradations are displayed by combining ON / OFF of these 8 subfields. Is realized.

Further, each subfield is composed of three types of operation periods, that is, a reset period, an address period, and a discharge sustaining period. Taking the selective erasing method as an example, in the reset period, discharge is performed for all pixels to uniformly form wall charges on the entire screen, and in the address period, it is selectively performed according to light emission / non-light emission of each pixel. The discharge is performed, the wall charges are erased from the predetermined pixel, and the display pixel is selected. In the next sustain period, an AC pulse voltage (sustain pulse) is applied to the sustain electrode pairs of all pixels, and discharge is generated and maintained only in the pixels in which wall charges are formed, so that light emission is continued during this period. It has become.

[0005]

Recently, such flat-panel PDPs have almost reached the stage of practical application, but further spread of broadband and advancement of IT technology pose a problem of further improvement in image quality in the future. . However, in the above-mentioned display method, increasing the number of gradations means increasing the number of subfields, and increasing the resolution means increasing the number of scan electrodes, which means that the address period becomes longer. To do. In either case, the total sustain period for the actual field is reduced (in order to maintain the brightness, the entire subfield is contained in the period of one field), which causes a problem of deterioration in luminance.

When the number of sub-fields is increased as the number of gray scales is increased, it becomes difficult to take a sufficient sustain period for lower bits. In particular, the smallest bit (LS
B) subfield S corresponding to the least significant bit
In F1, it was difficult to perform stable discharge because the sustain period was too short.

Further, even when the number of pixels is increased to achieve high resolution, the address period becomes long in each subfield, so that the sustain period is relatively shortened and the luminance is lowered. In order to compensate for such a decrease in brightness, it is common practice to increase the frequency of the sustain pulse, but increasing the frequency may cause the discharge state to become unstable. These operational instabilities have been factors such as flicker and defective gradation.

On the other hand, attempts have been made to improve the luminous efficiency by introducing a high frequency (RF) component into the sustain pulse (J. Kang et al; IDW '.
99 Proceedings, PDPp1-19, pp691-694, 1999). In a normal PDP, of the power supplied by the sustain pulse,
Since only 15 to 20% is consumed for the excitation of Xe that contributes to light emission, and the rest is consumed for heating electrons and ions, the emission efficiency is low at about 1.5 (lm / W). However, it is known that when the sustain frequency is increased to the RF band, plasma is maintained even in a weak electric field. Therefore, once the discharge is started, the plasma can be maintained by the low-voltage RF pulse, and the electron energy at that time is lower than that at the time of the normal sustain pulse application because the electric field strength is weak. In this way, when the RF pulse is applied, the loss due to heating of electrons and ions is conversely suppressed to about 20%, and Xe is reduced by about 60% of the supplied power.
It is known that it can be excited. In the above-mentioned document, as a result of producing a PDP provided with an RF electrode on the front substrate and introducing an RF pulse, it is reported that the luminous efficiency is about 10 (lm / W), which is about 10 times that of the AC pulse drive. Has been done. However, in that case, an electrode dedicated to RF must be provided in the PDP, but if a new electrode is added to the display panel on which three types of electrodes are already arranged or the electrode structure is changed, the panel structure is changed. There is a possibility that the manufacturing process becomes complicated and the manufacturing becomes difficult.

The present invention has been made in view of the above problems, and an object thereof is to provide a plasma display device and a driving circuit therefor capable of performing highly efficient light emitting display by a simple method.
And to provide a driving method.

[0010]

In the plasma display device of the present invention, a drive circuit unit for applying a high frequency voltage having a pulse width higher than or lower than a discharge sustaining voltage applied to a sustain electrode pair to an address electrode. It is equipped with.

The driving circuit of the plasma display device of the present invention is
A high frequency voltage applying means for generating a high frequency voltage having a pulse width higher than or lower than the discharge sustaining voltage applied to the sustain electrode pair and applying it to the address electrode is provided.

A method of driving a plasma display device according to the present invention comprises:
The drive circuit section applies a high frequency voltage to the address electrodes during the discharge sustaining period.

In the plasma display device, the driving circuit and the driving method thereof according to the present invention, the high frequency voltage is applied to the address electrode during the discharge sustaining period, and Xe is excited in the high frequency electric field.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a plasma display device according to an embodiment of the present invention. This plasma display device has the same structure as the conventional one except that the data pulse generating circuit 36 includes an RF power source 43 and a switch 44. That is, the display panel 10 and the video data DV obtained by A / D converting the input video signal SV.
An A / D converter 31 for generating the image data, an image memory 32 for storing the video data DV by the A / D converter 31, and an A / D converter
The D converter 31, the image memory 32, and the timing control unit 33 that controls the operation timing of the pulse generation circuits 34 to 36, and X that outputs a drive pulse to the display panel 10.
The pulse generation circuit 34, the Y pulse generation circuit 35, and the data pulse generation circuit 36 are mainly configured. The X pulse generation circuit 34 and the Y pulse generation circuit 35 apply the drive pulse to each of the sustain electrodes 17X and 17Y, and the data pulse generation circuit 36 applies the data pulse corresponding to the image data DV to the address electrode 13. It has become.

First, a concrete structure of the display panel 10 is shown in FIG. As described above, the display panel 10 includes the front glass substrate 11 and the rear glass substrate 12 which are made of transparent high strain point glass or soda lime glass and which are opposed to each other through the discharge space. On the front glass substrate 11, a plurality of paired sustain electrodes 17 (17X, 17Y) are provided in parallel. These sustain electrodes 17 are, for example, I
It is a transparent electrode made of TO (Indium-Tin Oxide), and a bus electrode 18 made of a metal such as Al (aluminum) is integrally provided on each side edge in order to reduce electric resistance. The sustain gap between the sustain electrodes 17X and 17Y is a discharge gap at the time of sustain discharge.
It is about 00 μm. A dielectric layer 1 made of, for example, SiO ₂ (silicon dioxide) is formed on the sustain electrode pair 17.
9, a protective layer 20 made of MgO (magnesium oxide) is sequentially provided.

On the other hand, on the rear glass substrate 12, address electrodes 13 made of metal such as Al are arranged in parallel. Since a high frequency voltage is applied to the address electrode 13 as described later, it is necessary to lower the impedance so as to propagate the high frequency and achieve matching. A dielectric layer 14 made of, for example, SiO ₂ is provided thereon, and a partition wall 15 for partitioning the discharge space into each address electrode 13 is further provided thereon. The partition wall 15 has, for example, a trapezoidal cross section and is mainly formed of low-melting glass.
A phosphor 16 is provided between them.

Rear glass substrate 1 having such a structure
1 and the front glass substrate 12 are the sustain electrodes 17 (17X, 1
7Y) and the address electrode 13 are aligned so that their extending directions are orthogonal to each other to form a matrix having each intersection as a pixel. FIG. 1 shows a state where such an electrode structure is viewed from the display surface side.
Y is an X pulse generation circuit 34 and a Y pulse generation circuit 35, and the address electrode 13 is a data pulse generation circuit 36.
Electrically connected to. Also, the substrates 11 and 12 are
The discharge space is hermetically sealed at the peripheral edge so as to fill the discharge gas with a predetermined pressure. As the discharge gas, for example, one or more kinds of rare gases can be used, and here, a mixed gas of Xe and Ne is used.

More specifically, the data pulse generating circuit 36 is composed of a data driver 41, a data pulse power source 42 and an RF power source 43 in more detail.
3 is electrically connected to the data driver 41 so as to be switchable, and the data pulse generated by the data driver 41 based on the voltage applied to the data pulse power supply 42 according to the video data from the memory 32; A high frequency pulse from the power source 43 is output to the address electrode 13.

FIG. 3 shows such a data pulse generation circuit 3
6 shows an example of the circuit configuration of No. 6. Data driver 41
Is, for example, a p-channel or n-channel MOS (Metal O
xide Semiconductor) transistors 41p and 41n, each of which is configured as an inverter circuit individually provided for each address electrode 13. The power source is the data pulse power source 42 or the RF power source 43, and one of them is selected by switching the switch 44. The switch 44 includes, for example, an FET (Field Effe
A semiconductor element such as ct Transistor) can be used.

Here, the RF power supply 43 is a power supply for supplying a high-frequency voltage having a frequency higher than that of a sustain pulse, which will be described later, or a short pulse voltage having a pulse width smaller than that of the sustain pulse. It is appropriately adjusted depending on the discharge gas conditions and the like. For example, the frequency is
It is enough to select from the band that is usually high frequency.
It can be set to about 50 MHz, and the voltage value is selected to be equal to or lower than the discharge start voltage of the discharge gas and capable of maintaining discharge. In the following description, such high frequency and short pulse voltages will be collectively referred to as high frequency pulses.
Further, the RF power source 43 is provided with a matching circuit 43a on the output side, which performs impedance matching so as to increase the supplied power.

Further, in this inverter, the video data DV from the image memory 32 or the switching signal SS from the timing control unit 33 is input from the input terminal, and the transistors 41p and 41n perform switching operation in response to this, A pulse voltage corresponding to the connected power source is output from the output end to the address electrode 13 side.

Next, the operation of this plasma display device will be described. Here, it is assumed that the display panel 10 is gradation-controlled by the subfield driving method and is driven by the selective erasing method. 4A to 4C show sustain electrodes 17X and sustain electrodes 1 from the pulse generating circuits 34 to 36, respectively.
7Y is a drive sequence (for one subfield) showing a voltage waveform input to the address electrode 13.

In the reset period, the X pulse generation circuit 34, Y controlled by the timing control unit 33 is operated as usual.
The pulse generation circuit 35 applies a pulse of a predetermined value to all the sustain electrodes 17X and 17Y to perform preliminary discharge between the paired electrodes. As a result, the protective layer 19 for all pixel regions
So-called wall charges are formed on top.

In the next address period as well, under the control of the timing control unit 33, the Y pulse generation circuit 35 outputs pulses in sequence to the sustain electrodes 17Y arranged in parallel, and at the same time, the scanning is performed at the same time. The data pulse generation circuit 36 applies a data pulse to the address electrode 13 in synchronization with the timing. The data pulse is based on a signal generated from the video data DV as described later, and is applied to the address electrode 13 belonging to the pixel which does not emit light among the horizontal pixels sharing the sustain electrode 17Y. It has become. The input voltage value to the sustain electrode 17Y and the address electrode 13 is set so that the address discharge is generated by exceeding the discharge start voltage only when a voltage is applied to both electrodes. As a result, the address discharge is selectively generated in the pixels that do not emit light, and the wall charges are erased.

The control operation of such address discharge is performed as follows. First, the input video signal SV is
The / D converter 31 converts each pixel into an 8-bit digital signal indicating the brightness of each of the three primary colors, that is, video data DV based on the sampling control by the timing control unit 33, and sequentially supplies it to the image memory 32. In this video data DV, the luminance component ratio of each bit is 1: 2: 4: 8: 16: 32: 64: 128 in order from the least significant bit, and the maximum luminance is (111111
11), that is, quantized as 255.

The image memory 32 separates the video data DV into, for example, eight bit data under the control of the timing control unit 33 and stores the data in line units or field units. Further, the image memory 32 reads out bit data for each pixel in the subfield to be displayed next among the stored video data DV under the control of the timing control unit 33, and outputs it to the data pulse generation circuit 36.

The data pulse generation circuit 36 outputs 2 based on the inputted video data DV (bit data for each pixel).
Value data pulses are generated, and these are output to the address electrode 13 corresponding to each pixel based on the timing control by the timing control unit 33. In this embodiment, at this time, the switch 44 is switched so that the data pulse power supply 42 becomes conductive, and the data driver 41
Is supplied with the power supply voltage V _dd . The data driver 41 is
Invert output for bit data. That is, when bit data “1” is input (transistor 41p, transistor 41n) becomes (off, on) and output 0
(V), when the bit data is “0” (41p, 41
n) becomes (ON, OFF), which is the output V _dd (V). As a result, the address electrodes 13 are
The voltage is applied from.

Next, during the sustain period, the X pulse generating circuit 34 and the Y pulse generating circuit 35 controlled by the timing control unit 33 apply the sustain pulse to all the sustain electrodes 17X and 17Y. Further, here, after the addressing, the switch 4 of the data pulse generating circuit 36 is
4 is switched so that the side of the RF power source 43 is made conductive, and the switching signal SS from the timing control unit 33 is sent to the data driver 41 at the same time when the sustain pulse is input.
Input to all columns. As a result, a high frequency pulse is applied from the RF power source 43 to the address electrode 13 via the transistor 41p at the same timing as the start of sustain discharge (FIG. 4).
(C)).

At this time, in the display pixel, discharge is started between the sustain electrodes 17X and 17Y where the potential of the wall charge is superimposed on the applied sustain pulse and the discharge start voltage is reached, and the discharge is maintained by the high frequency pulse. It The sustain pulse is applied as a trigger for maintaining and stabilizing the plasma while the high frequency pulse is applied.

During the discharge, the excitation energy of Xe is used for the emission of ultraviolet rays, and the emitted ultraviolet rays strike the fluorescent material 16.
Emits light. Here, as described above, since the discharge is performed by the high frequency pulse, the energy loss due to the heating of the electrons and the like is reduced and the Xe is efficiently excited, so that the luminous efficiency is improved and the brightness is higher than the conventional one. Maintained and improved.

Thus, during the sustain period, the pixels to be displayed selectively emit light, and the subfields are overlapped in time series, so that the brightness corresponding to one field is weighted and the gradation is controlled. Is displayed. The brightness of this displayed image is also maintained / improved.

As described above, in the present embodiment, the RF power source 43 is provided in the data pulse generating circuit 36, and the RF power source 43 applies the high frequency pulse to the address electrode 13 via the switch 44 during the sustain period. Because I did
Energy loss due to heating of electrons or the like is reduced in a high frequency electric field, and Xe excitation is performed with high efficiency. Therefore, the luminous efficiency due to the sustain discharge can be improved, and high-luminance display can be performed. Further, according to the present embodiment,
Even if the sustain period is shortened, it is possible to secure the same brightness as the conventional one, and it is possible to improve gradation and resolution while maintaining sufficient brightness.

Further, in the present embodiment, the RF power source 43 is incorporated in the drive circuit, and the display panel 10 having the same structure as the conventional one is driven at a high frequency by using the address electrode 13 which is not used during the sustain period. Therefore, it is possible to easily carry out the method without making a large modification to the apparatus.

The present invention is not limited to the above embodiment, and various modifications can be made. For example, in the above embodiment, the RF power source 43 is described as being connected to the address electrode 13 via the data driver 41, but in the plasma display device of the present invention, the high frequency pulse is timing-controlled separately from the data pulse. The RF power source and the address electrode can be connected in various ways without being limited to those described in the above embodiment.

FIG. 5 shows a concrete modification thereof. In this case, an inverter composed of transistors 41p and 41n is provided at an input terminal V _in to which the video data DV is input, a data pulse power supply 42 is provided on the source side of the transistor 41p, and a pMOS type transistor 51p is provided on the inverter output side. The address electrodes 13 are connected to each other through. The matching circuit 43 is provided on the address electrode 13.
a, the RF power source 43 is connected via the nMOS type transistor 52n, and the gates of the transistors 51p and 52n are gate input terminals V _G to which the gate signal SG is input.
It is connected to the.

In this pulse generation circuit, the video data DV
The gate signal SG switches the two transistors 51p and 52n in the preceding inverter, so that the data pulse and the high frequency pulse are output to the address electrode 13 at different timings. The gate signal SG is continuously input during the application period of the high frequency pulse, but is not input during other periods. Therefore, in the address period, the transistor 51p is turned on and the transistor 52n is turned off, the conduction between the RF power source 43 and the address electrode 13 is cut off, and the video data DV input to the input terminal V _in is exclusively supplied to the address electrode 13. The data pulse generated by the operation control of the inverter to be performed and the supply voltage from the data pulse power supply 42 is input. In the sustain period, since the gate signal SG is input to the input terminal V _G this time, the transistor 51p is turned off, the transistor 52n is turned on, the conduction on the input terminal V _in side is cut off, and only the RF power supply 43 is addressed to the address electrode 13. To become conductive. As a result, a high frequency pulse having the same application time as the gate signal SG can be supplied to the address electrode 13.

In this modification, since the output control of the high frequency pulse is performed without passing through the transistor 41 for controlling the data pulse, there is a fear of malfunction if the accumulated charge is present in the transistor due to the effect of the previously input video data DV. However, the influence of such other signals can be eliminated.

Further, in the present invention, the high frequency voltage applied to the address electrodes may be any voltage that is applied to the address electrodes during at least one of the sustain periods and effectively contributes to the sustain discharge. On the other hand, the sustain pulse is not limited to the pattern normally used as in the above embodiment. For example, the high-frequency pulse and the sustain pulse can be set in terms of voltage value, frequency or pulse width so as to balance generation and disappearance of charged particles in the electric field during sustain discharge.

As such an example, FIG. 6 shows a modification of the above embodiment. In this case, in order to start the first discharge, a single pulse or a pulse that lasts for a short period is applied to the sustain electrode 17 at the initial stage of sustain, and this is replaced with a high-frequency pulse during the remaining sustain period. It is designed to apply only. The power of the high frequency pulse at this time is set so that the discharge is maintained even if the voltage is not applied to the sustain electrode 17.

Further, as shown in FIG. 7, the sustain pulse voltage is 0 V even when the high frequency pulse is applied in the drive waveform of FIG.
Sustaining voltage of about half that of conventional electrodes
Alternatively, the power of the high frequency pulse may be suppressed to a low level.

[0042]

As described above, in the plasma display device according to the present invention, the driving for applying the high frequency voltage having the pulse width higher or lower than the discharge sustaining voltage applied to the sustain electrode pair to the address electrodes. A driving circuit for a plasma display device according to the present invention is provided with a circuit section,
Since the high-frequency voltage applying means for generating the high-frequency voltage and applying it to the address electrode is provided, according to these, the high-frequency voltage is applied to the address electrode to perform the sustain discharge, and Xe is applied in the high-frequency electric field. Energy loss given to electrons, etc.
The energy efficiency for e-excitation can be improved. Therefore, it is possible to improve the luminous efficiency due to the sustain discharge, and it is possible to increase the luminance or to improve the image quality by increasing the resolution and the number of gradations while maintaining the luminance. Further, the plasma display device and the driving circuit thereof according to the present invention do not need to be largely modified from the conventional configuration, and can easily perform high frequency driving.

According to the driving method of the plasma display device of the present invention, since the driving circuit section applies the high frequency voltage to the address electrodes during the discharge sustaining period, the Xe excitation is performed in the high frequency electric field and the electric field is generated. The energy loss provided to the electrons and the like through is reduced, and the power efficiency for Xe excitation is improved. Therefore, it is possible to drive with a high luminous efficiency though it is a simple method, and it is possible to perform high-luminance display or display with high resolution and a high number of gradations while maintaining the luminance.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a plasma display device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a configuration of a display panel of the plasma display device shown in FIG.

3 is a circuit diagram showing a specific configuration example of a data driver in the plasma display device shown in FIG.

FIG. 4 is a voltage waveform diagram showing a driving sequence of the plasma display device shown in FIG.

5 is a circuit diagram showing a modified example of the plasma display device shown in FIG.

FIG. 6 is a voltage waveform diagram according to a modification of the embodiment of the present invention.

FIG. 7 is a voltage waveform diagram according to a modification of the embodiment of the present invention.

FIG. 8 is a diagram for explaining a general driving method of a conventional plasma display device.

[Explanation of symbols]

10 ... Display panel, 11 ... Front glass substrate, 12 ... Rear glass substrate, 13 ... Address electrode, 14 ... Dielectric layer, 1
5 ... Partition wall, 16 ... Phosphor, 17, 17X, 17Y ... Sustaining electrode, 18 ... Bus electrode, 19 ... Dielectric layer, 20 ... Protective layer, 31 ... A / D converter, 32 ... Image memory, 33 ... Timing Control unit, 34 ... X pulse generation circuit, 35 ... Y pulse generation circuit, 36 ... Data pulse generation circuit, 41 ... Data driver, 41p, 51p ... pMOS transistor, 41n, 52n ... nMOS transistor, 42 ... Data pulse power supply, 43 ... RF power source, 43a ... Matching circuit, 44 ... Switch.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 H04N 5/66 101B H04N 5/66 101 G09G 3/28 H

Claims (4)

[Claims] 1. A first substrate and a second substrate which are arranged to face each other, a pair of sustain electrodes which are provided in parallel on the first substrate, and the sustain which is provided on the second substrate. Address electrodes provided in parallel in a direction intersecting with the electrode pair, and for applying a high frequency voltage having a pulse frequency higher than or lower than the discharge sustaining voltage applied to the sustain electrode pair to the address electrodes A plasma display device comprising a drive circuit section. 2. A first substrate and a second substrate that are arranged to face each other, a pair of sustain electrodes provided in parallel on the first substrate, and the sustain electrode on the second substrate. A driving circuit for a plasma display device, comprising an address electrode provided in parallel with a pair of electrodes in a direction intersecting with the electrode pair, the pulse width being higher or smaller than a discharge sustaining voltage applied to the sustaining electrode pair. Generates high frequency voltage of
A driving circuit for a plasma display device, comprising a high-frequency voltage applying means for applying to the address electrodes. 3. The drive circuit of the plasma display device according to claim 2, further comprising a timing control means for controlling the timing of applying the high frequency voltage to the address electrodes so as to be within a discharge sustaining period. 4. A first substrate and a second substrate, which are arranged to face each other, a pair of sustain electrodes provided in parallel on the first substrate, and the sustain electrode on the second substrate. An address electrode provided in parallel in a direction intersecting with the electrode pair, and for applying a high frequency voltage having a pulse width higher than or lower than the discharge sustaining voltage applied to the sustain electrode pair to the address electrode. A driving method of a plasma display device, comprising: a driving circuit unit, wherein the driving circuit unit applies the high frequency voltage to the address electrodes during a discharge sustaining period.