JP2003133920A - Noise filter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize hysteresis characteristic of an input buffer of a semiconductor device and filer out noise corresponding to the occurrence frequency and magnitude of the noise. SOLUTION: The device is provided with a 1st signal generation circuit 140 which generates a pseudo signal S140, a 2nd signal generation circuit which generates a signal 11 equivalent to the pseudo signal S140, a plurality of noise filter means 110 which filter out noise from the output signal 11 of the 2nd signal generation circuit 10 with different abilities of each noise filter measure, and a selector 120 which selects one of outputs of a plurality noise filter means 110. The device also provides a counter 150 which counts noise detection signals S130 and outputs a selection signal of the selector 120 corresponding to the counting value, reset signals 160 that initialize counting values of the counter 150, and a signal comparator 130 which compares an output of the noise filter means 110 and the pseudo signal S140 and outputs a noise detection signal S130 that shows disagree information of the signal waveforms.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a noise eliminator applied to an information processing device such as an LSI.

[0002]

2. Description of the Related Art In recent years, information processing apparatuses have been reduced in voltage of a power supply for the purpose of lowering power consumption. With the reduction in voltage, electrical noise causing malfunction of the information processing apparatus has been reduced. As it becomes minute, highly accurate noise evaluation technology is required.

Conventionally, there is an information processing apparatus mounting system incorporating a noise detection circuit as such a noise evaluation technique.

FIG. 5 shows an example of an information processing device mounting system incorporating a noise detection circuit. This information processing apparatus mounting system includes a first signal generation circuit 11 that generates a pseudo signal 19 and a second signal generation circuit that generates a first system signal (hereinafter, first signal) 410 equivalent to the pseudo signal 19. The circuit 45 and the output signal 41 of the second signal generation circuit 45
A logic circuit 44 for inputting 0 and a second signal generation circuit 45
Signal comparator 12 which inputs the output signal 410 of the above and compares it with the pseudo signal 19 and outputs the information of the match / mismatch of the signal waveforms.
And a selector 14 for switching and inputting the output signal 410 of the second signal generating circuit 45 to one of the logic circuit 44 and the signal comparator 12.

In the figure, 41 is an information processing apparatus mounting system, 13 is a signal line for outputting the pseudo signal 19 from the first signal generating circuit 11 and inputting it to the signal comparator 12, and 15 is a selector 14. Reference numeral 16 is a signal line for inputting the output signal to the signal comparator 12, and 16 is a signal line connecting the selector 14 and the logic circuit 44. 43 is an input terminal, 17 is an output terminal, 18 is a noise detection signal output from the signal comparator 12, 110 is a signal line for sending the noise detection signal 18 from the signal comparator 12 to the output terminal 17, and 46 is an input terminal 43 is a signal line that connects the selector 14; 47 is a noise generation source; 48 is a connection wiring that connects the noise generation source 47 and the input terminal 43; 412 is a noise signal output from the noise generation source 47; and 413 is a first signal. It is a noise first signal in which the noise signal 412 is superimposed on 410.

With this conventional technique, it is possible to identify the presence or absence of electrical noise in the information processing device 42 and the location of the electrical noise.

[0007]

However, in order to prevent the information processing device 42 from malfunctioning due to electrical noise, some noise countermeasures are taken on the information processing device mounting system, noise detection is performed again, and noise is detected again. If this is the case, it will be necessary to repeat the above steps. Further, when the information processing device mounting system is changed, it is necessary to perform the noise detection again.

The present invention solves the above conventional problems.
An object of the present invention is to provide a noise removing device that does not require noise countermeasures on an information processing device mounting system and that can perform appropriate noise removing according to the noise level.

[0009]

A noise eliminator according to claim 1 comprises: first signal generating means for generating a pseudo signal;
Second signal generating means for generating a signal equivalent to the pseudo signal, a plurality of noise removing means for removing noise from the output signal of the second signal generating means with different noise removing capabilities, and outputs of the plurality of noise removing means Selecting means for selecting any one of the signals, counting means for counting the noise detection signal and outputting the selection signal of the selecting means according to this count value, and comparing the output signal of the noise removing means with the pseudo signal It is provided with a comparison means for outputting the information of the waveform mismatch as a noise detection signal.

According to this configuration, for example, by incorporating it in an information processing apparatus mounting system, noise detection is performed at the time of system startup, and it is possible to perform appropriate noise removal according to the information processing apparatus mounting system. is there.

According to a second aspect of the present invention, there is provided the noise elimination device according to the first aspect, wherein the noise elimination device is provided after the counting means.
It further comprises storage means for storing the count value and giving the count value stored at the time of restart to the comparing means.

According to this configuration, in addition to the same effects as those of the first aspect, when the noise environment of the information processing apparatus mounting system does not change, appropriate noise removal can be performed without performing noise detection, and the system can be started. It is possible to shorten the time.

According to a third aspect of the present invention, there is provided the noise elimination device according to the first or second aspect, wherein the plurality of noise elimination means are composed of a plurality of Schmitt trigger buffers having different hysteresis widths.

According to this structure, the same operation as in claim 1 or 2 is achieved.

A noise removing device according to a fourth aspect is the noise removing device according to the first or second aspect, in which the plurality of noise removing means are composed of a plurality of noise filters using delays and having different delay amounts. According to this configuration, the same operation as in claim 1 or 2 is achieved.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus including the noise removing apparatus of the present invention and its peripheral circuits (information processing apparatus mounting system). In FIG. 1, reference numeral 40 is an information processing apparatus, and 41 is an internal logic circuit of the information processing apparatus 40.

Reference numeral 140 denotes a first signal generating circuit provided in the information processing device 40 as a first signal generating means, and S1.
Reference numeral 40 is a pseudo system signal (hereinafter, referred to as pseudo signal) generated by the first signal generating circuit, 10 is a second signal generating circuit as second signal generating means, 20 is a noise generating source, and 11 is A second system signal that does not include noise (hereinafter referred to as the second signal), 21 is a noise signal generated by the noise generation source 20, and 22 is a second system signal that includes noise (hereinafter referred to as the noise second signal). Note).

Reference numeral 100 denotes an input terminal of the information processing device 40, 1
Reference numeral 10 denotes a Schmitt trigger buffer group in which a plurality of Schmitt trigger buffers are arranged in parallel. 111-118
Is a Schmitt trigger buffer as a noise removing means having different hysteresis widths.

Here, the Schmitt trigger buffer group 11
The configuration of 0 will be described with reference to FIG. 2 is shown in FIG.
3 is an output waveform diagram of the Schmitt trigger buffer group 110 in FIG.

FIG. 2A is a waveform diagram of the noise second signal 22 input to the Schmitt trigger buffer group 110. V _{T1H to} V _T8H are logic levels of outputs of the Schmitt trigger buffers 111 to 118, respectively, being low level. Is the threshold voltage that rises from the
_{T1L to} V _T8L are the Schmitt trigger buffer 111, respectively.
It is a threshold voltage at which the logical polarity of the output of ~ 118 falls from the low level to the high level.

FIG. 2 (b) is an output waveform diagram of the first Schmitt trigger buffer 111, FIG. 2 (c) is an output waveform diagram of the second Schmitt trigger buffer 112, and FIG. 2 (d) is a third Schmitt trigger. An output waveform diagram of the buffer 113, and FIG. 2E is an output waveform diagram of the eighth Schmitt trigger buffer 118.

At time T ₀ , the voltage of the noise second signal 22 exceeds the threshold voltage V _T1H , and the logical polarity of the output of the Schmitt trigger buffer 111 rises from low level to high level. At time T ₁ , the voltage of the noise second signal 22 _falls below the threshold voltage V _T1L, and the logical polarity of the output of the Schmitt trigger buffer 111 falls from the high level to the low level.

Similarly, at time T ₂ , the logic polarity of the output of the Schmitt trigger buffer 111 rises from low level to high level, and at time T ₃ , the logic polarity of the output of the Schmitt trigger buffer 112 changes from low level to high level. At time T ₄ , the logical polarity of the output of the Schmitt trigger buffer 111 falls from the high level to the low level, and at time T ₅ , the logical polarity of the output of the Schmitt trigger buffer 111 rises from the low level to the high level. At time T ₆ , the logical polarity of the output of the Schmitt trigger buffer 113 rises from low level to high level,
_{At 7} , the logical polarity of the output of the Schmitt trigger buffer 118 rises from the low level to the high level, at time T ₈ , the logical polarity of the output of the Schmitt trigger buffer 111 falls from the high level to the low level, and at the time T ₉ , the Schmitt Trigger buffer 112
The logic polarity of the output of the output falls from the high level to the low level, and at time T ₁₀ , the Schmitt trigger buffer 1
The logic polarity of the output of 13 falls from the high level to the low level, the logic polarity of the output of the Schmitt trigger buffer 111 rises from the low level to the high level at time T ₁₁ , and the output of the Schmitt trigger buffer 111 at the time T ₁₂ . The logic polarity of falls from high level to low level.

Schmidt trigger buffer 1 as described above
11 to 118, the Schmitt trigger buffer group 11
0 is configured.

Referring again to FIG. 1, reference numeral 120 denotes a multi-input / single-output selector as selecting means, and the Schmitt trigger buffers 111 to 118 are selected from the Schmitt trigger buffer group 110 by the count value of the counter 150 as counting means which will be described later. Select one of these.
S120 is one of the output signals of the Schmitt trigger buffer groups 111 to 118 selected by the selector 120 (hereinafter, referred to as noise removal second signal). 42 is a 1-input / 2-output selector, which is a noise removal second signal S120
Is switched to the input signal to the logic circuit 41 and the signal comparator 130 as a comparison means described later.

Reference numeral 130 is a signal comparator, and S130 is a signal for transmitting noise detection (hereinafter referred to as noise detection signal).
, 150 is a counter, and the noise detection signal 13
Count the number of times 0 was asserted. S150 is the count value of the counter 150, and 160 is the counter 1
This is a reset signal for resetting the count value of 50.

Now, a procedure for the selector 120 to select any one of the Schmitt trigger buffers 111 to 118 from the Schmitt trigger buffer group 110 will be described with reference to FIG.

FIG. 3 shows the count value S150 and the selector 12
0 shows the relationship with the Schmitt trigger buffer selected. When the count value S150 is the initial value '000',
The selector 120 is the first Schmitt trigger buffer 11
Select 1. When the count value S150 is '001',
The selector 120 is the second Schmitt trigger buffer 11
Select 2. When the count value S150 is '010',
The selector 120 is the third Schmitt trigger buffer 11
Select 3. Similarly, the count value S150 is 1
When 11 ′, the selector 120 selects the eighth Schmitt trigger buffer 118.

A noise removing operation of the information processing apparatus 40 according to the first embodiment of the present invention configured as above will be described.

First, by inputting the reset signal 160, the count value of the counter 150 is set to the initial state '000', and the first Schmitt trigger buffer 1 having the smallest hysteresis width than the Schmitt trigger buffer group 110.
Select 11.

Next, the input terminal 1 is selected by the selector 42.
00, Schmitt trigger buffer group 110, and selector 1
Noise removal second signal S120 input via 20
Is switched from the input to the logic circuit 41 to the input to the signal comparator 130.

Next, in the first signal generating circuit 140, the second signal is generated.
The pseudo signal S140 equivalent to the second signal 21 generated from the signal generation circuit 10 is generated.

Next, the noise removal second signal S120 selected by the selector 120 is input to the signal comparator 130, and the pseudo signal S140 is input to the signal comparator 130. The signal comparator 130 compares the input noise removal second signal S120 with the pseudo signal S140, and when the comparison results do not match, the noise removal second signal S120.
Output a noise detection signal S130 indicating the presence of noise,
Input to the counter 150. The count value of the counter 150 is incremented to "001" by the input of the noise detection signal S130, and the selector 120 selects the second Schmitt trigger buffer 112 having the second smallest hysteresis width than the Schmitt trigger buffer group 110.

By repeating the same operation thereafter, the Schmitt trigger buffer 111 having a hysteresis width necessary to remove noise from the noise removal second signal S120.
The Schmitt trigger buffer group 110 having the smallest hysteresis width of
It is selected more and noise can be removed.

Here, the Schmitt trigger buffer having the minimum hysteresis width is selected for the following reason. That is, when the hysteresis width is large, the absolute amount of noise that can be removed increases, but the margin of the input level decreases. Therefore, it is considered best to use a Schmitt trigger buffer with a minimum hysteresis width that can remove noise.

According to the noise eliminator of this embodiment,
For example, by incorporating in an information processing apparatus mounting system, noise detection is performed at the time of system startup, and thus it is possible to perform appropriate noise removal according to the information processing apparatus mounting system. That is, a Schmitt trigger buffer (input buffer) having an optimum hysteresis width can be selected in the signal input section according to the frequency and magnitude of noise, and noise can be removed in an optimum state.

Next, a second embodiment of the present invention will be described with reference to FIG.

FIG. 4 is a block diagram of an information processing apparatus and its peripheral circuits (information processing apparatus mounting system) according to the present invention. In FIG. 4, 170 is a storage device and 180 is a set signal, and the storage value of the storage device 170 is set in the counter 150 as the count value S150. Since the other configurations are similar to those of the first embodiment, description thereof will be omitted.

A noise removing operation of the information processing apparatus 40 according to the second embodiment of the present invention configured as above will be described.

First, by inputting the reset signal 160, the count value of the counter 150 is set to the initial state of “000”, and the first Schmitt trigger buffer 1 having the smallest hysteresis width than the Schmitt trigger buffer group 110.
Select 11.

Next, the input terminal 1 is selected by the selector 42.
00, Schmitt trigger buffer group 110, and selector 1
Noise removal second signal S120 input via 20
Is switched from the input to the logic circuit 41 to the input to the signal comparator 130.

Next, the first signal generating circuit 140
The pseudo signal S140 equivalent to the second signal 21 generated from the signal generation circuit 10 is generated.

Next, the noise removal second signal S120 selected by the selector 120 is input to the signal comparator 130, and the pseudo signal S140 is input to the signal comparator 130. The signal comparator 130 compares the input noise removal second signal S120 with the pseudo signal S140, and outputs a noise detection signal S130 indicating the presence of noise in the noise removal second signal S120 when the comparison results do not match, Input to the counter 150. The count value of the counter 150 is incremented to "001" by the input of the noise detection signal S130, and the selector 120 selects the second Schmitt trigger buffer 112 having the second smallest hysteresis width than the Schmitt trigger buffer group 110 and the count value S150. Are stored in the storage device 170.

By repeating the same operation thereafter, the Schmitt trigger buffer 111 having a hysteresis width necessary for removing noise from the noise removal second signal S120.
The Schmitt trigger buffer group 110 having the smallest hysteresis width of
It is selected more and noise can be removed.

By inputting the set signal 180 to set the value stored in the storage device 170 in the counter 150, the Schmitt trigger buffer selected last time can be selected.

According to the noise eliminator of this embodiment, when the noise environment of the information processing apparatus mounting system does not change, the noise can be appropriately removed without performing noise detection, and the system startup time can be shortened. Is possible. Other effects are similar to those of the first embodiment.

In the first and second embodiments of the present invention described above, the case where the Schmitt trigger buffer group 110 is composed of eight Schmitt trigger buffers having different hysteresis widths has been described as an example. The present invention can also be implemented by configuring the Schmitt trigger buffer group 110 with n different Schmitt trigger buffers (n is an integer of 2 or more).

In the first and second embodiments described above, the Schmitt trigger buffer is used as the noise removing means. However, instead of the Schmitt trigger buffer, a plurality of noises using delays and having different delay amounts are used. A filter can also be used.

[0050]

According to the noise eliminator according to the first aspect of the present invention, by incorporating the noise eliminator in, for example, an information processing apparatus mounting system, noise detection is performed at the time of system startup
It is possible to perform appropriate noise removal according to the information processing device mounting system.

According to the noise removing device of the second aspect,
In addition to the same effect as the first aspect, when the noise environment of the information processing apparatus mounting system does not change, appropriate noise removal can be performed without performing noise detection, and the system startup time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing apparatus and its peripheral portion according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram showing signal waveforms of a Schmitt trigger buffer group according to the first embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a relationship between a count value and a selector according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of an information processing device and its peripheral circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional information processing apparatus mounting system.

[Explanation of symbols]

10 Second signal generation circuit 11 Second signal 20 noise sources 21 noise signal 22 Noise second signal 40 Information processing device 41 Logic circuit 42,120 selector 100 input terminals 110 Schmitt trigger buffer group 111-118 Schmitt trigger buffer S120 Noise removal second signal 130 signal comparator S130 Noise detection signal 140 First Signal Generation Circuit S140 Pseudo signal 150 counter S150 count value 160 reset signal 170 storage device 180 set signal

Claims (4)

[Claims] 1. A first signal generating means for generating a pseudo signal, a second signal generating means for generating a signal equivalent to the pseudo signal, and different noise removal from an output signal of the second signal generating means. A plurality of noise removing means for removing noise by the capacity, a selecting means for selecting any one of the output signals of the plurality of noise removing means, and a noise detecting signal for counting the noise detection signals A noise removing apparatus comprising: a counting unit that outputs a selection signal; and a comparing unit that compares the output signal of the noise removing unit with the pseudo signal and outputs information on signal waveform mismatch as the noise detection signal. 2. The noise eliminator according to claim 1, further comprising a storage unit that stores the count value after the counting unit and supplies the stored count value to the comparison unit at the time of restarting. 3. The noise eliminator according to claim 1, wherein the plurality of noise eliminators comprises a plurality of Schmitt trigger buffers having different hysteresis widths. 4. The noise eliminator according to claim 1, wherein the noise eliminator comprises a plurality of noise filters using delays and having different delay amounts.