JP2003133504A - Lead frame structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a small-sized lead frame structure by substantially reducing package dimensions to the dimensions of a semiconductor chip. SOLUTION: The lead frame structure is provided with; a stage frame having a first frame portion, a stage for mounting a semiconductor chip and a stage support portion for connecting the stage to the first frame portion; and a lead frame having a second frame portion and a lead for establishing connection to the second frame portion via an outer lead and laid on the stage frame. The stage support portion extends to the first frame portion from the stage through the center between the opposed two sides thereof, and has a bent portion so that the level of the stage is rendered lower than the level of the first frame portion by the distance equivalent to the thickness of the semiconductor chip. The bent portion has a portion whose width or thickness is smaller than the other portions in order to facilitate bending of the stage support portion.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having leads packaged in a three-dimensional structure and a lead frame structure used in the method of manufacturing the same.

In recent years, resin-encapsulated semiconductors are required to be compact in size, despite the fact that semiconductor chips are becoming larger. In semiconductor devices using a lead frame having a two-dimensional structure, miniaturization is required. However, there is a problem in its mechanical strength and reliability.

Therefore, a COL (Chip on Lea) in which the leads are arranged on the lower surface of the semiconductor chip which has not been used until now.
ad) structure or LOC (Lead on Ch
Various semiconductor devices having a three-dimensional structure such as an (ip) structure have been proposed.

[0004]

2. Description of the Related Art FIGS. 27A and 27B are views showing an example of a conventional semiconductor device having a LOC structure. FIG. 27A is a plan view showing the inside of a package as seen through, and FIG. A) Medium A
It is a longitudinal cross-sectional view along the line A.

In the LOC structure shown in FIG. 27, the inner lead 4 formed in a predetermined shape is connected to the bonding pad 7 arranged on the circuit forming surface 1a of the semiconductor chip 1 by the bonding wire 3. An insulating material 6 is adhered and interposed between the semiconductor chip 1 and the inner lead 4 to maintain insulation between the inner lead 4 and the circuit forming surface 1a of the semiconductor chip 1.

However, in the above structure, since the insulating material 6 is arranged between the semiconductor chip 1 and the inner lead 4, when the compatibility between the insulating material 6 and the sealing resin 2 is poor, or the adhesive force is low. If it is insufficient, there is a problem that the sealing resin 2 is cracked after packaging.

Further, since the inner lead 4 made of a metal having a different linear expansion coefficient from that of the semiconductor chip 1 is disposed on the thin insulating material 6 interposed on the circuit forming surface 1a of the semiconductor chip 1, heat generation of the semiconductor chip 1 causes There is a problem that the reliability of the semiconductor device is impaired, for example, stress is generated on the surface of the semiconductor chip 1 and the semiconductor circuit is deformed.

In addition, the conventional manufacturing process using an insulating material,
There is also a problem that the device cannot be used and the manufacturing cost of the semiconductor device increases due to the introduction of a new device.

Therefore, the applicant of the present invention has disclosed a semiconductor device having a LOC structure shown in FIG. 28 as a semiconductor device having a three-dimensional structure capable of solving the above-mentioned drawbacks and reducing the size of the package.
It is proposed by Japanese Patent Publication No. 9-66157 (Japanese Patent Publication No. 4-1503). 28A is a front view showing the inside of the package as seen through, FIG. 28B is a plan view of the lead frame, and FIG. 28C is a plan view of the stage frame.

In the semiconductor device having the LOC structure shown in FIG. 28, a lead frame 8 having outer leads 5 and inner leads 4 connected to the frame portion 15 and formed in a predetermined shape, and a step portion are formed with the frame portion 15. Bending part 10
And a stage frame 9 having a rectangular stage 13 connected to the center of the frame portion 15 via.

Then, as shown in the figure, the semiconductor chip 1 is placed on the stage 13, the lead frame 8 and the stage frame 9 are overlapped and packaged with the sealing resin 2, and the device is constructed. At this time, the semiconductor chip 1 and the inner leads 4 are arranged apart from each other by forming the bent portion 10 on the stage frame 9.

Therefore, the semiconductor chip 1 and the inner leads 4 are insulated by the sealing resin 2 interposed therebetween. As described above, since the insulating material is not used unlike the above-mentioned device, the above problems caused by the insulating material are solved.

However, in the above-described semiconductor device, the bending portion 10 for mounting the semiconductor chip 1 on the stage 13 and forming a space between the semiconductor chip 1 and the inner lead 4 is provided inside the package. Therefore, the package dimensions are the same as those of the semiconductor chip 1 and the bending portion 10.
It was impossible to make it less than or equal to the sum of the dimensions.

In view of the above points, it is an object of the present invention to provide a lead frame structure suitable for use in a semiconductor device and a method of manufacturing the same, which can reduce the size of the package to the size of a semiconductor chip. And

[0014]

SUMMARY OF THE INVENTION The above-mentioned problem is a stage having a first frame part, a stage on which a semiconductor chip is mounted, and a stage support part for connecting the stage to the first frame part. A lead frame that has a frame, a second frame portion, and a lead connected to the second frame portion via an outer lead, and is overlaid on the stage frame; 2 opposite stages
The first frame part extends from each side of the side to the first frame part while sandwiching the center part of each side, and the height position of the stage is the distance corresponding to the thickness of the semiconductor chip. The bent portion has a portion having a width or a thickness smaller than other portions to facilitate bending of the stage support portion. This can be achieved by the lead frame structure.

[0015] The above-mentioned problem is that a stage frame having a first frame part, a stage on which a semiconductor chip is mounted, a stage support part connecting the stage to the first frame part, and a second frame. The second portion through the frame and the outer lead.
A lead frame connected to the frame part of the stage, and a lead frame stacked on the stage frame, and the stage support part sandwiches a center part of each side from two opposite sides of the stage. And extending to the first frame portion,
The stage has a bent portion such that the height position of the stage is lower than the height position of the first frame portion by a distance corresponding to the thickness of the semiconductor chip, and the first frame portion, the stage, and The lead is characterized by comprising a flat plate integral with the stage support part, and the bending part having means for absorbing strain generated by use of upper and lower molds sandwiching the lead frame and the stage frame. It can also be achieved by a frame structure.

According to the lead frame structure of the present invention, the semiconductor chip is mounted over the entire surface of the stage inside the encapsulating resin without disposing an insulating material between the inner lead and the semiconductor chip, and the package size is reduced. It is possible to reduce the size to about the size of a semiconductor chip.

[0017]

1A and 1B are views showing a first embodiment of a semiconductor device using a lead frame structure according to the present invention. FIG. 1A is a front view and FIG. 1B is a side view. The left halves of both figures are perspective views of the inside of the package for convenience of explanation.

The semiconductor device 14 shown in FIG.
3, the semiconductor chip 1 mounted on the stage 13, and the inner leads 4 which are spaced apart from the semiconductor chip 1 and arranged above the semiconductor chip 1 are sealed with a sealing resin 2 to form an MF-LOC ( Multi Flame-Lead on Chip) structure.

The stage 13 is substantially rectangular and flat,
It has two stage support parts 130a projecting to the left end and two stage support parts 130b projecting to the right end in FIG. Stage support unit 130a
The tip portions of and 130b are exposed from the sealing resin 2. A semiconductor chip 1 having a substantially rectangular shape and slightly smaller than the stage 13 is bonded and fixed onto the stage 13.
A circuit is formed on the upper surface (circuit forming surface) 1a of the semiconductor chip 1.

Above the circuit forming surface 1a of the semiconductor chip 1, a plurality of inner leads 4 are arranged at equal intervals, apart from the circuit forming surface 1a. Each inner lead 4 is electrically connected to the semiconductor chip 1 by a bonding wire 3.

As shown in FIG. 1A, the distance between each inner lead 4 and the stage 13 is substantially constant, and the distance between each inner lead 4 and the circuit forming surface 1a is also substantially constant.
Further, as shown in both figures, each inner lead 4 extends in parallel from the upper center of the semiconductor chip 1 to the outside of the sealing resin 2 in a state substantially parallel to the stage 13 and the circuit forming surface 1a, and the outer lead 4 It becomes 5.

When the semiconductor device 14 is viewed from the outside of the sealing resin 2, the stage support portion 13 exposed from the sealing resin 2 is exposed.
Surfaces 130c and 130d of a and 13b on which the semiconductor chip 1 is mounted respectively, and surfaces 5a of the portions of the outer leads 5 exposed from the sealing resin 2 that face the circuit forming surface 1a are semiconductors. The chips 1 are arranged substantially parallel to each other with a distance that is approximately the sum of the thickness dimension of the chip 1 and the distance between the inner lead 4 and the circuit forming surface 1a. Therefore, the inner lead 4 and the stage 13 are substantially parallel to each other at least in the sealing resin 2.

The outer lead 5 is bent outside the sealing resin 2 at a substantially right angle in the lower part of FIG.
It is formed to have a letter shape. By connecting the outer leads 5 to an external circuit (not shown), the semiconductor chip 1 is electrically connected to the external circuit.

Next, a method of manufacturing the semiconductor device 14, which is the first embodiment of the method of manufacturing a semiconductor device using the lead frame structure according to the present invention, will be described with reference to FIGS.

2 to 4 are diagrams showing the constituent elements of the semiconductor device 14, respectively. 2 is a plan view showing a semiconductor chip, FIG. 3 is a three-view drawing showing a stage frame, and FIG. 4 is a three-view drawing showing a lead frame. 3 and 4, (A) is a plan view, (B) is a front view, and (C) is a side view.

As shown in FIG. 2, a predetermined number of bonding pads 7 corresponding to the number of terminals (that is, the number of outer leads 5) of the semiconductor device are provided at predetermined positions in the central portion of the circuit forming surface 1a of the semiconductor chip 1. Is provided.

Further, as shown in FIG. 3, the stage frame 9
Is a rectangular stage 13 on which the semiconductor chip 1 is mounted.
There is constructed are connected to the frame portion 15 ₁ extending in the vertical direction in the figure by the stage support part 130a, 130b. The size of the stage 13 is slightly larger than the semiconductor chip 1 in both the vertical and horizontal directions. The stage support parts 130 a and 130 b have a bending part 10 that is flatly projected from the stage 13 with respect to the stage 13 and then bent upward in the figure, and is further bent flatly with respect to the frame part 15. It is connected to the part 15. Thus, the upper surface of the stage 13 spaced apart by d in vertical direction in the drawing with respect to the upper surface of the frame portion 15 _1. This distance d is larger than the thickness dimension of the semiconductor chip 1 which does not appear in FIG.

A plurality of positioning holes 16 are formed in the frame 151. Positioning holes 16 are used to carry out the positioning of the frame portion 15 ₁ in the manufacturing process. The positioning hole 16 includes an elliptical shape and a circular shape. The elliptical positioning hole 16 serves as the frame portion 15 in the manufacturing process.
It is provided for the purpose of absorbing the expansion and contraction of ₁ . Therefore, FIG.
Only four positioning holes 16 are shown in (A),
One of the positioning holes 16 has an elliptical shape,
Actually, a plurality of positioning holes 16 are arranged at predetermined intervals. Further, positioning holes 16 of the elliptical shape, the frame portion 15 ₁
May be provided along one end or both ends.

Further, as shown in FIG. 4, the lead frame 8
Is formed in a flat plate shape, and the inner lead 4 and the outer lead 5 extending from the inner lead 4 are
5 ₂ is constructed by being connected by a connecting portion 18 and.
The lead frame 8 is punched into a shape such that the tip of the inner lead 4 is located at a position where wire bonding is easy with respect to the position of the bonding pad of the semiconductor chip 1.

[0030] the frame portion 152, positioning holes 16 for the same reasons as the positioning hole 16 is formed in a frame portion 15 ₁ is formed. Positioning hole 16 of frame portion 15 ₂ and frame portion 15 ₁
The positioning holes 16 are formed at positions corresponding to each other so that they can be accurately positioned.

The stage 13 of the above stage frame 9
After the semiconductor chip 1 is adhesively fixed to the upper surface, the lead frame 8 is aligned by the positioning holes 16 and overlapped on the upper surface of the stage frame 9, the inner leads 4 and the semiconductor chip 1 are wire-bonded in the wire bonding step. It

Next, FIG. 5 is a conceptual diagram for explaining an outline of a mold (lower mold) used in the embodiment of the present manufacturing method.
In FIG. 5, the positioning pin 17 is inserted into the positioning holes 16 of the lead frame 8 and the stage frame 9 which are overlapped with each other, and the respective frames are aligned with the mold. In the figure, the frame portions 15 ₁ and 15 ₂ are shown as one frame portion 15.

The lower die 23 is composed of three kinds of digging depths shown by different hatching in FIG. 5, and the upper die (not shown) has the digging depths of the lower die 23. It has a shape corresponding to.

The lower die 23 has a rectangular package portion 25a having the deepest digging, and four support portions 19 having the deepest digging next to the package portion 25a and projecting vertically from the package portion 25a in FIG. It is configured by a gate portion 21 which has the same depth as the support portion 19 and which protrudes downward from the center of the package portion 25a, and a rectangular lead portion 20 around the shallowest dug package portion 25a.

The vertical and horizontal dimensions of the package portion 25a are slightly larger than the vertical and horizontal dimensions of the stage. Support section 19
2 protrudes from the package portion 25a at two points in the upper and lower parts of FIG. 5, and extends to the end of the frame portion 15. After the gate portion 19 extends downward in the figure, the longitudinal direction of the frame portion 15 (left-right direction)
Runner part 22 extending to the same depth as the gate part 19
Communicate with.

Lead frame 8 superposed integrally
(FIG. 4) and the stage frame 9 (FIG. 3) are placed on the lower mold 23 so that the positioning pins 17 of the lower mold 23 are inserted into the positioning holes 16 of the frame portions 15 ₁ and 15 ₂ , respectively. It is resin-sealed.

FIGS. 6A to 6D are views for explaining a second embodiment of the method of manufacturing a semiconductor device using the lead frame structure according to the present invention, in which the lead frame 8 and the stage which are superposed are stacked. The frame 9 and the lower die 23 are placed on the lower die 23, and the upper die 24 is placed on the lower die 23. 6C is a plan view, FIG. 6A is a cross-sectional view taken along line I-I in FIG. 6C, and FIG. 6B is taken along line II-II in FIG. 6C. A sectional view and FIG. 6D are sectional views taken along line III-III in FIG. 6C.

In FIG. 6, the upper mold 24 is the lower mold 2 described above.
3 and 3, the outer leads 5 of the flat lead frame 8 extending from the package portion 25a and the stage frame 9 having the stage support portions 130a and 130b are held and clamped at predetermined positions. . That is, the upper mold 24 is the package part 25 of the lower mold 23.
The package portion 25b dug in the same shape as the package portion 25a at a position corresponding to a, and the flat portion 26 that supports the frame portion 15 of each of the lead frame 8 and the stage frame 9.
And the support section 19 together with the stage support section 13
It is comprised by the protrusion part 27 which supports a, 13b.

Then, by injecting the sealing resin from the runner portion 22 through the gate portion 21, the semifinished product 14a of the semiconductor device 14 shown in FIG. 7 is obtained. Figure 7
(A) is a front view showing the inside of the package as seen through, and (B) is a side view showing the inside of the package as seen through.

Further, the stage support portions 130a and 130b of the semi-finished product 14a are cut at the position indicated by the alternate long and short dash line, the outer lead 5 is cut to a predetermined length, and the connecting portion 18 shown in FIG. 4 is cut. After separating the leads, the leads are formed into a predetermined lead shape, whereby the semiconductor device 14 shown in FIG. 1 is obtained.

In the semiconductor device 14 having the three-dimensional structure manufactured by the above method, since the semiconductor chip 1 is mounted over the entire flat stage 13 inside the sealing resin 2, the semiconductor chip 14 is slightly smaller than the sealing resin 2. The semiconductor chip 1 which is extremely small and larger than the conventional one can be sealed, and the package can be downsized.

A space between the inner lead 4 and the circuit forming surface 1a of the semiconductor chip 1 is sealed with a sealing resin 2.
There is no intervening insulating material. Therefore, the reliability is high without causing mechanical problems due to the insulating material.

It is conceivable that the semiconductor device 14 having the above-mentioned three-dimensional structure is manufactured by another method instead of the above-mentioned manufacturing method. Next, FIG. 8 is a diagram for explaining a third embodiment of the manufacturing method according to the present invention. In FIG. 8, (A) is a conceptual plan view and (B) is FIG. 8 (A).
A sectional view taken along the line IV-IV in FIG.
It is sectional drawing in the V line.

In FIG. 8, the frame portion 15 of the stage frame 9a, in which the semiconductor chip 1 is bonded and fixed to the stage 13, is shown.
Over _1, spacer 30 shown by hatching have the same width as the frame portion 15 ₁ is mounted. Furthermore, the frame portion 15 ₂ of the lead frame 8 on the spacer 30 are superimposed are respectively aligned and held by the upper mold 24a thereof and a lower mold 23a.

The spacer 30 has a rectangular cross section,
The thickness dimension is larger than that of the semiconductor chip 1. Therefore,
The inner lead 4 is separated from the circuit forming surface 1a of the semiconductor chip 1. The linear expansion coefficient of the spacer 30 is substantially equal to the linear expansion coefficient of the lead frame 8 and the stage frame 9a.

The above-mentioned stage frame 9a has a flat shape similar to that of the stage frame 9 shown in FIG. 3, and has a flat plate shape having no bending portions in the support supporting portions 130e and 130f. The stage frame 9a has a positioning hole 16a at a position corresponding to the positioning hole 16 of the lead frame 8.
Are formed. The spacer 30 also has a positioning hole 16b formed at a position corresponding to the positioning holes 16 and 16a.

The lower mold 23a has a flat portion 31 for supporting in contact with the frame portion 15 ₁ of the stage frame 9a, a deeply dug package portion 25a for sealing by the sealing resin 2 to the semiconductor chip 1, As shown in FIG. 4, the lead frame 8
Protrusion 15a that protrudes from the frame portion 15 _2, and the protrusion 32 which abuts supported 15b, the protrusion 33 constituting the gate portion 21a, the runner 22 communicating with the gate section 21a
and a.

The upper die 24a is a frame portion 1 of the lead frame 8.
5 a flat portion 34 which abuts _2, the stage support part 130e of the stage frame 9a, a projecting portion 35 which abuts from above 130f, deeply dug package portion for sealing the semiconductor chip 1 by the sealing resin 2 25b, and a shallowly dug communicating portion 36 for communicating the gate portion 21a with the runner portion 22a.

Then, the runner portion 22a to the gate portion 21
By injecting the sealing resin 2 through a, the semi-finished product 14a of the semiconductor device 14 shown in FIG. 7 is obtained as in the case of the above-described manufacturing method.

According to this manufacturing method, since the stage frame bending process is not necessary, the manufacturing process can be simplified, and in comparison with the molds 23 and 24 used in the above-described manufacturing method, the mold (upper mold 24a Also, there is an advantage that the lower die 23b) can be formed into a simple shape and the die cost can be reduced.

Next, FIG. 9 is a diagram for explaining a fourth embodiment of the method of manufacturing a semiconductor device using the lead frame structure according to the present invention. 9, (A) is a conceptual plan view, (B) is a sectional view taken along line VI-VI in FIG. 9 (A), and (C) is a sectional view taken along line VII-VII in FIG. 9 (A). is there. 9, those parts which are the same as those corresponding parts in FIG. 8 are designated by the same reference numerals, and a description thereof will be omitted.

In FIG. 9, the spacer 30a shown by hatching has a positioning hole 16c.
6c is formed at a position corresponding to the positioning holes 16 and 16a of the lead frame 8 and the stage frame 9a, respectively.

As shown in the figure, the stage frame 9a
The spacer 30a and the lead frame 8 are aligned and overlapped with each other, and these are held by the lower mold 23b and the upper mold 24b. The spacer 30a has a rectangular cross-sectional shape, the thickness dimension thereof is larger than the thickness dimension of the semiconductor chip 1, and the inner lead 4 of the lead frame 8 is separated from the circuit forming surface 1a of the semiconductor chip 1.

The linear expansion coefficient of the spacer 30a is determined by the spacer 3
Similar to the coefficient of linear expansion of 0, the coefficient of linear expansion of the lead frame 8 and the stage frame 9a is substantially equal.

[0055] lower mold 23b includes a flat portion 41 for supporting in contact with the frame portion 15 ₁ of the stage frame 9a, a deeply dug package portion 25a for sealing by the sealing resin 2 to the semiconductor chip 1, It is composed of a runner portion 22b communicating with the gate portion 21b.

[0056] On the other hand, the upper die 24b has a flat portion 42 which contacts the frame portion 15 ₂ of the lead frame 8, and a package portion 25b dug deeply for sealing by the sealing resin 2 to the semiconductor chip 1, the runner It is constituted by a shallowly dug gate portion 21b communicating with the portion 22b.

In the above structure, the side surface 25d of the package portion 25b of the upper die 24b, the side surface 30b of the spacer 30a on the semiconductor chip 1 side, and the side surface 25c of the package portion 25a of the lower die 23b form a continuous surface. Has been done.

Then, the runner portion 22b to the gate portion 21
By injecting the sealing resin 2 through b, the above-mentioned 2
Similar to the one manufacturing method, the semi-finished product 14a of the semiconductor device 14 shown in FIG. 7 is obtained.

According to this manufacturing method, the manufacturing process can be simplified without the need for bending the stage frame 9a, and the molds (the upper mold 24b and the lower mold 23b) are molded into the mold 23a shown in FIG. , 24a can be made into a simpler shape,
It has an excellent feature that the die cost can be further reduced.

Next, the bonding step in the above-mentioned method for manufacturing a semiconductor device will be described. When wire-bonding the semiconductor chip 1 and the inner leads 4 by each of the above-described manufacturing methods, the circuit forming surface 1a of the semiconductor chip 1 and the inner leads 4 in the state where the lead frame 8 and the stage frame 9 are overlapped with each other. Are separated.

Therefore, when the conventional wire bonding using ultrasonic waves is performed, the bonding portion of the inner lead 4 vibrates, so that it is difficult to reliably perform the wire bonding. Therefore, when manufacturing the semiconductor device having the LOC structure, it is desirable to perform highly reliable wire bonding by the following method.

FIG. 10 is a diagram for explaining a wire bonding step in the method of manufacturing a semiconductor device using the lead frame structure of the present invention. In FIG. 10, (A) is a diagram showing a schematic configuration of a wire bonder, and (B) and (C) are diagrams for explaining a bonding process.

In FIG. 10A, the semiconductor chip 1 to be wire-bonded is placed on the stage 13 of the stage frame, and the inner lead 4a of the lead frame is spaced apart from the circuit forming surface 1a on the semiconductor chip 1. Are arranged in a predetermined number. A cushioning material 100 is provided on the lower surface of the inner lead 4a opposite to the circuit forming surface.

A bonding pad 7 made of a plurality of aluminum electrodes is arranged in the center of the circuit forming surface 1a of the semiconductor chip 1. The lead frame and the stage frame are integrally stacked and placed on the heater 103.

A capillary 101, which is a part of the wire bonder, is located above the semiconductor chip 1. The capillary 101 is provided with a hole having a diameter slightly larger than the diameter of the bonding wire, and is inserted into this hole,
The bonding wire is guided and supplied. The capillary 101 is attached to a transducer not shown in the figure. This transducer vibrates by ultrasonic oscillation and ultrasonically bonds the bonding wire.

A frame retainer 102, which is a part of the wire bonder, is arranged above the inner leads 4a. As shown in the figure, the frame retainer 102 has a tip portion formed in an “L” shape, and is configured so that the tip portion rotates in the AB direction.

As shown in FIG. 10B, the frame holder 102 is rotated in the A direction and an appropriate load is applied to the inner lead 4a from above so that the cushioning material 100 is brought into contact with the circuit forming surface 1a of the semiconductor chip 1. Let At this time, the circuit forming surface 1a is not damaged by applying a large load, and the tips of the inner leads 4a to which the bonding wires 3 are connected are brought into contact with the circuit forming surface 1a to stabilize mechanically. An appropriate load is applied to the inner lead 4a so that ultrasonic welding can be stably performed.

As described above, the bonding wire 3 is guided by the capillary 101 in a state where the cushioning material 100 is brought into contact with the circuit forming surface 1a as shown in the figure by the frame press 102, and the predetermined inner lead 4a and the bonding pad 7 are formed. Is wire-bonded.

When the wire bonding to all the inner leads 4a is completed, the frame retainer 102 becomes B
And the load on the inner lead 4a is stopped. As a result, the inner lead 4a becomes parallel to the circuit forming surface 1a due to its own elastic force, and the inner lead 4a
A space appears between a and the circuit forming surface 1a as shown in FIG.

By bonding the semiconductor chip 1 and the inner lead 4a by the above method, a semiconductor device having a LOC structure having a space between them is provided.
Highly reliable wire bonding can be performed.
Subsequently, the cushioning material 1 is resin-sealed by one of the methods described in FIGS. 5 to 9 and has the same shape as that shown in FIG.
A semiconductor device in which 00 is arranged on the inner lead 4a with the circuit forming surface 1a separated is completed.

By the way, the stage frame 9 dissipates the heat generated by the semiconductor chip 1 to the outside of the package. However, due to the close contact between the metal stage frame 9 and the resin sealing resin 2, the package (resin sealing is performed). A crack may occur in the resin 2). Therefore, the stage frame 9
It is desirable to prevent the sealing resin 2 from cracking by minimizing the area where the sealing resin 2 and the sealing resin 2 are in close contact with each other.

Hereinafter, various embodiments of the stage frame configured to have a small contact area with the sealing resin will be shown and briefly described. FIG. 11 is a three-sided view showing another example of the stage frame, and FIGS. 12 to 14 are three-sided views showing still another example of the stage frame.
Is a plan view, (B) is a front view, and (C) is a side view.

A stage frame 50 shown in FIG. 11 is a stage 51 for supporting the left and right ends of the semiconductor chip 1 in the figure.
The a and 51b are connected to and supported by the frame portion 15 by the stage support portions 52a and 52b having the bent portions.

The stage frame 53 shown in FIG. 12 has bent portions at both left and right ends, and the semiconductor chip 1 is supported by two rod-shaped support portions 54a and 54b connected to the left and right frame portions 15 in the figure. It is supposed to be structured.

The stage frame 55 shown in FIG. 13 is a stage 5 that supports the central portion of the semiconductor chip 1 in the left-right direction.
Both ends of 6 are connected to T-shaped structures 57a and 57b, and
The character structures 57a and 57b are structured to be connected to the frame portion 15 via stage support portions 52a and 52b having bending portions.

The stage frame 58 shown in FIG. 14 is a stage 5 for vertically supporting the central portion of the semiconductor chip 1.
Both ends of 9 are connected to the frame portion 15 via the stage support portions 52c and 52d.

According to the structure of the stage 56 of the stage frame 55, when the bonding pads on the semiconductor chip 1 are arranged in the horizontal direction in FIG. I can support you.

According to the structure of the stage 59 of the stage frame 58, when the bonding pads on the semiconductor chip 1 are arranged in the vertical direction in FIG. I can support you.

Incidentally, each of the above stage frames 50, 5
3, 55, 58, the stages 51a, 51b, 56,
59, the support portions 54a and 54b, and the frame portion 15 have steps formed by bending portions as described above. The upper surface of the frame portion 15 and the stages 51a, 51b, 56, 59
The vertical distance from the upper surface of each of the support portions 54a and 54b is, of course, larger than the thickness of the semiconductor chip 1.

Therefore, the stages 51a, 51b, 56,
59, the semiconductor chip 1 is placed on the support portions 54a and 54b, and the lead frame 8 (not shown) is placed on them.
When the two are superposed on each other, the lead frame 8 and the circuit forming surface 1a of the semiconductor chip 1 are separated from each other, and the insulation between the lead frame 8 and the semiconductor chip 1 is maintained.

Even when the above-mentioned various stage frames are used, a gap is formed between the circuit forming surface 1a of the semiconductor chip 1 and the lead frame 8. Therefore, the semiconductor device obtained by subsequently resin-sealing by any of the above-described methods can seal a large semiconductor chip which is slightly smaller than the package, like the semiconductor device 14. Therefore, it is possible to obtain a semiconductor device having an MF-LOC structure in which the package is reduced in size to a size of a semiconductor chip.

Next, a process of bending the stage support portions 130a and 130b of the stage frame 9 shown in FIG. 14 will be described. As shown in FIG. 15, the lead frame 9 is mounted on the lower stand 101 of the press and fixed at the portion indicated by P. In this state, the upper portion 102 descends in the direction of arrow X and bends the stage frame 9 as indicated by the broken line in the figure.

For example, the stage support section 130a is
As shown in FIG. 16 (A), it has a length a before being pressed, but after bending it has a length a '(a'> a) extended as shown in FIG. 16 (B). . Here, when the thickness of the stage frame 9 is t, the bending limit is t ′ = 1.5t to 2.0t. If the bending process exceeds this limit and t'is larger than 2.0t,
The stage frame 9 may be cut at the stage support part 130a.

Therefore, in the first embodiment of the semiconductor device using the lead frame structure, the stage support section 130 is used.
The bent portions 10 are provided at a and 130b. Bent part 1
0 facilitates bending of the stage support parts 130a and 130b, and when the stage frame 9 is bent, the stage support parts 130a and 130b.
To prevent disconnection.

FIG. 17 shows an embodiment of the bending portion 10.
In the figure, (A) is a plan view and (B) is a side view. In this embodiment, in order to facilitate bending of the stage support part 130a, the width of the bent part 10 is formed smaller than the other parts of the stage support part 130a. For example, the bent portion 10 is formed by performing half etching on a part of the stage support portion 130a.

FIG. 18 shows another embodiment of the bending portion 10. In the figure, (A) is a plan view and (B) is a side view.
In this embodiment, in order to facilitate bending of the stage support portion 130a, the width and thickness of the bent portion 10 are formed smaller than other portions of the stage support portion 130a. For example, the bent portion 10 is formed by performing half etching on a part of the stage support portion 130a or reducing the thickness by pressing.

By the way, in the first embodiment of the semiconductor device using the lead frame structure, the space between the inner lead 4 and the circuit forming surface 1a of the semiconductor chip 1 has a stage frame 9 for accommodating the semiconductor chip 1. It is determined by the forming accuracy of the space formed in the. For this reason, when the stage frame 9 is bent, it is necessary to consider the tolerance of this void.

When the thickness of the package is relatively large, the bending can be performed in consideration of the tolerance as described above.
When the thickness of the package is small, it is very difficult to accurately bend the stage frame 9 in consideration of the tolerance. In the latter case, the space cannot be accurately formed between the stage frame 9 and the inner lead 4. As a result, the inner lead 4 and the circuit forming surface 1a
The space between the inner lead 4 and the circuit forming surface 1a cannot be properly filled with the sealing resin 2 if the space is too small. In this way, the sealing resin 2
If the space is not filled well, the reliability of the semiconductor device will be significantly reduced.

FIG. 19 shows the target value La of the space between the stage frame 9 and the inner lead 4. For example, the stage frame 9 is bent within an error range of the target value La ± 0.1 mm.

On the other hand, FIG. 20 shows a side view of the semiconductor device. The sealing resin 2 has a thickness L at the upper part of the inner lead 4.
c, and has a thickness Lb between the inner lead 4 and the circuit forming surface 1a. Therefore, the error of the target value La is ±
If the thickness is 0.1 mm, the thickness Lb varies within a range of ± 0.1 mm. If the thickness Lc can be reduced so that the thickness Lb can be increased without increasing the overall thickness of the semiconductor device, even if the thickness Lb varies by ± 0.1 mm, this variation can be ignored. However, if the thickness of the entire semiconductor device is relatively small, it is impossible to reduce the thickness Lc, and therefore the thickness Lb cannot be increased.

According to the present inventor, the thickness Lb <0.1 mm
Then, as shown in FIG. 21, it was found that the space between the inner lead 4 and the circuit forming surface 1a of the semiconductor chip could not be filled with the sealing resin 2 satisfactorily. As a result, the unfilled portion 200 is formed between the inner lead 4 and the circuit forming surface 1a. in this case,
The insulation between the inner leads 4 and the circuit forming surface 1a becomes insufficient, and the reliability of the semiconductor device is significantly lowered.

Next, a fourth embodiment of the method of manufacturing a semiconductor device using the lead frame structure according to the present invention will be described with reference to FIG.

The embodiment of this manufacturing method is such that the upper and lower molds 2 used when the semiconductor chip 1 is sealed with the sealing resin 2.
The above problems are solved by utilizing the accuracy of 4,23.
That is, when the upper and lower molds 24 and 23 are combined before being filled with the sealing resin 2, the upper and lower molds 24 and 23 are forcibly forced to reach the target value by the pressing action particularly at the portion indicated by the arrow. L
Correct a. In the part indicated by the arrow on the left side in FIG. 22,
The spacer 140 and the lower die 23 cooperate to set the target value La.
To fix. The spacer 140 has a thickness larger than that of the semiconductor chip 1 so that a space is formed between the circuit forming surface 1 a and the inner lead 4.

As a result, the error of the target value La is from La ± 0.02 mm to La ± 0.03 m regardless of the error generated when the stage frame 9 is bent as shown in FIG.
It is corrected to the range of m. Therefore, according to this embodiment,
A space between the inner lead 4 and the circuit forming surface of the semiconductor chip 1 can be guaranteed. That is, the thickness Lb shown in FIG. 20 can be formed to a design value. Therefore, the unfilled portion 2 shown in FIG.
It is possible to reliably prevent the occurrence of 00.

23 and 24 show the upper and lower molds 2 respectively.
An example of the bending portion 10 of the stage support portion 130a (and 130b) for facilitating the correction of the target value La using 4, 23 will be shown. 23 and 24, (A) is a plan view and (B) is a side view.

In FIG. 23, the bent portion 10 has a generally inverted U-shape. On the other hand, the bent portion 10 shown in FIG. 24 has a zigzag shape. Since the shape of these bent portions 10 can absorb some expansion and contraction, it is easy to correct the target value La.

Next, a second embodiment of the semiconductor device using the lead frame structure according to the present invention will be described with reference to FIG. 4, those parts which are the same as those corresponding parts in FIGS. 1 to 4 are designated by the same reference numerals, and a description thereof will be omitted. In FIG. 25, (A) is a partial plan view and (B) is a partial sectional view.

In FIG. 25A, the inner lead 4 and the stage support portion 130a intersect with each other in a plan view, as shown in a portion surrounded by a circle indicated by Y. The crossing on the plan view is performed by positioning the two frame portions 15 ₁ and 15 ₂ , that is, the stage frame 9 and the lead frame 8 by using the positioning hole 16 in a portion that does not finally remain in the package. It is possible because Since such crossing on the plan view is possible, in this embodiment, the inner lead 4
The effect that the degree of freedom in design can be improved is further obtained.
That is, the degree of freedom in designing the inner leads 4 is increased as compared with the case where the above plan views cannot be intersected.

Next, a third embodiment of the semiconductor device using the lead frame structure according to the present invention will be described with reference to FIG. In the figure, (A) is a front view, (B) is a side view,
The left halves of both figures are perspective views of the inside of the package for convenience of explanation. In the figure, those parts which are the same as those corresponding parts in FIG. 1 are designated by the same reference numerals, and a description thereof will be omitted.

In this embodiment, the bottom surface of the stage 13 is exposed from the sealing resin 2. That is, the sealing resin 2 is not formed on the bottom surface of the stage 13. As a result, the stage 13 itself acts as a heat radiating portion, and the heat generated during the operation of the semiconductor chip 1 can be efficiently radiated. In addition, since the sealing resin 2 is not formed on the bottom surface of the stage 13, the thickness of the semiconductor device (package) is increased even though the two frame portions 15 ₁ and 15 ₂ , that is, the stage frame 9 and the lead frame 8 are used. It is also possible to effectively reduce the size.

The present invention has been described above with reference to the embodiments.
Needless to say, the present invention is not limited to these embodiments and can be variously modified and improved.

[0102]

As described above, according to the present invention, the semiconductor chip is mounted over the entire surface of the stage inside the sealing resin without disposing an insulating material between the inner lead and the semiconductor chip. It is possible to mount a semiconductor chip having substantially the same size as the package without reducing the reliability of the device due to the material, and to reduce the size of the package, which is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a two-sided view showing a first embodiment of a semiconductor device using a lead frame structure according to the present invention.

FIG. 2 is a first semiconductor device using a lead frame structure.
It is a top view which shows the semiconductor chip of an Example.

FIG. 3 is a first semiconductor device using a lead frame structure.
It is a trihedral view which shows the stage frame of an Example.

FIG. 4 is a first semiconductor device using a lead frame structure.
It is a trihedral view which shows the lead frame of an Example.

FIG. 5 is a conceptual diagram for explaining a mold used in the first embodiment of the method for manufacturing a semiconductor device using the lead frame structure according to the present invention.

FIG. 6 is a drawing for explaining the first embodiment of the method of manufacturing the semiconductor device using the lead frame structure.

FIG. 7 is a diagram showing a semi-finished product obtained in a certain step of the first embodiment of the method for manufacturing a semiconductor device using a lead frame structure.

FIG. 8 is a drawing for explaining the second embodiment of the method of manufacturing a semiconductor device using the lead frame structure according to the present invention.

FIG. 9 is a drawing for explaining the third embodiment of the method for manufacturing a semiconductor device using the lead frame structure according to the present invention.

FIG. 10 is a diagram illustrating a wire bonding process used in an example of a method for manufacturing a semiconductor device using the lead frame structure of the present invention.

FIG. 11 is a three-view drawing showing an embodiment of a stage frame.

FIG. 12 is a trihedral view showing another embodiment of the stage frame.

FIG. 13 is a trihedral view showing still another embodiment of the stage frame.

FIG. 14 is a trihedral view showing still another embodiment of the stage frame.

FIG. 15 is a side view illustrating a step of bending a stage frame.

FIG. 16 is a side view illustrating the extension of the stage support portion of the stage frame.

FIG. 17 is a two-sided view showing an example of a stage support unit.

FIG. 18 is a two-sided view showing another embodiment of the stage support section.

FIG. 19 is a side view illustrating a target value when the stage frame is bent.

FIG. 20 is a side view illustrating the thickness of the sealing resin in each part of the semiconductor device.

FIG. 21 is a side view illustrating an unfilled portion formed between the inner lead and the circuit forming surface of the semiconductor chip.

FIG. 22 is a side view for explaining the fourth embodiment of the method of manufacturing the semiconductor device using the lead frame structure according to the present invention.

FIG. 23 is a two-sided view showing a main part of a stage support section used in a fourth example of a method of manufacturing a semiconductor device using a lead frame structure.

FIG. 24 is a two-sided view showing a main part of another stage support section used in the fourth embodiment of the method of manufacturing a semiconductor device using the lead frame structure.

FIG. 25 is a two-sided view showing a second embodiment of the semiconductor device using the lead frame structure according to the present invention.

FIG. 26 is a two-sided view showing a third embodiment of the semiconductor device using the lead frame structure according to the present invention.

FIG. 27 is a two-sided view showing an example of a conventional LOC structure semiconductor device.

FIG. 28 is a diagram showing another example of a conventional semiconductor device having a LOC structure.

[Explanation of symbols]

1 semiconductor chip 1a Circuit formation surface 2 Sealing resin 4 inner lead 8 lead frame 9, 9a, 50, 53, 55, 58 Stage frame 13, 51a, 51b, 56, 59 stages 15 Semiconductor device 23, 23a, 23b Lower mold 24, 24a, 24b Upper mold 30,30a spacer 100 cushioning material

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Junichi Kasai             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor ▲ Yoshi ▼ Masanori             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Koichi Takeshita             5950 Soeda, Iriki-cho, Satsuma-gun, Kagoshima             Company Kyushu Fujitsu Electronics inside F-term (reference) 5F044 AA01 BB21 GG07                 5F061 AA01 BA02 CA21 DA06                 5F067 AA01 BA10 BB14 BD05 BD10                       BE06 DA11

Claims (2)

[Claims] 1. A stage frame having a first frame part, a stage on which a semiconductor chip is mounted, a stage support part connecting the stage to the first frame part, and a second frame part. A lead frame connected to the second frame portion via an outer lead, and a lead frame overlaid on the stage frame, wherein the stage support portion has two opposite sides of the stage. To the first frame portion with the center portion of each side interposed therebetween, and the height position of the stage is the height position of the first frame portion by a distance corresponding to the thickness of the semiconductor chip. A lead frame structure having a bent portion so as to be lower, and the bent portion has a portion whose width or thickness is smaller than other portions in order to facilitate bending of the stage support portion. . 2. A stage frame having a first frame part, a stage on which a semiconductor chip is mounted, a stage support part connecting the stage to the first frame part, and a second frame part. A lead frame connected to the second frame portion via an outer lead, and a lead frame overlaid on the stage frame, wherein the stage support portion has two opposite sides of the stage. To the first frame portion with the center portion of each side interposed therebetween, and the height position of the stage is the height position of the first frame portion by a distance corresponding to the thickness of the semiconductor chip. The first frame portion, the stage, and the stage support portion are integrally formed as a flat plate having a bent portion so as to be lower, and the bent portion includes an upper side that sandwiches the lead frame and the stage frame. Caused by the use of the lower mold Leadframe structure, characterized in that it comprises means for absorbing the strain.