JP2003132009A - Information processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a bus system for an information processing apparatus for maximizing usage efficiency of each bus of three kinds of a system bus, a memory bus and a processor bus. SOLUTION: A processor bus (111) connected with a processor (101), a memory bus (112) connected with a main memory (104) and a system bus (113) connected with an input/output device (105), are connected to a trident path connection control means (103). The control means (103) has a bus memory connection controller (401), with which each address bus of the processor bus (111), memory bus (112), system bus (113) and a control bus are connected to transmit mutually addresses and control signals and generate data bus control signals (420). The control means (103) also has a data bus switch (402), with which each data bus of the processor bus (111), memory bus (112) and system bus (113), is connected to transfer mutually data on the data bus.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system used in information processing devices such as workstations, personal computers, word processors and the like.

[0002]

2. Description of the Related Art Conventionally, a bus system in an information processing device is
Bite, Volume 14, Issue 12 (1989), pages 417-4
24 pages, (BYTE, Volume 14, Number 12
(1989), pp. 417-424). Brett
A configuration in which the memory bus and the system bus are individually connected to the processor bus, or the processor bus and the memory bus are individually connected to the system bus, as in the bus system described in Glass, "INSIDE EISA". Was becoming.

[0003]

The former is a so-called direct memory access (hereinafter referred to as DMA) in which a system bus and a memory bus operate in conjunction with each other.
In this case, since the processor bus cannot operate independently, the use efficiency of the processor bus is deteriorated. On the other hand, the latter has a problem that the system bus cannot operate independently during so-called main memory access in which the processor bus and the memory bus operate in an interlocking manner, resulting in poor system bus usage efficiency.

The structure and problems of these conventional bus systems will be described later in detail with reference to the drawings.

An object of the present invention is to provide a bus system of an information processing device which maximizes the usage efficiency of each bus.

Another object of the present invention is to provide a bus system capable of simultaneously performing a linked operation of a processor bus and a memory bus and an independent operation of a system bus.

A further object of the present invention is to provide a bus system capable of simultaneously performing an interlocking operation of a system bus and a memory bus and an independent operation of a processor bus.

Still another object of the present invention is to provide an information processing apparatus which maximizes the usage efficiency of each bus when at least three buses of a system bus, a memory bus and a processor bus are interconnected. It is to provide a bus system for cars.

[0009]

In order to achieve the above object, in the present invention, three buses of a first bus, a second bus, and a third bus are connected in at least a trifurcated manner, and among three kinds of buses. While other two are operating in conjunction with each other, other buses can be operated independently.

That is, in the present invention, a processor, a main memory, an input / output device, a first bus connected to the processor, and a second bus connected to the main memory,
In an information processing device having a third bus connected to the input / output device, the first bus, the second bus, and the third bus are connected, and the processor, the main memory, and the input / output device are arbitrary. Connecting means for enabling data transfer between the two, the connecting means using the connected first bus and second bus, and connecting the first bus between the processor and the main memory. A first data transfer mode for transferring a data signal and a second data bus between the main memory and the input / output device using the connected second bus and third bus.
Second data transfer mode for transferring the third data signal, and a third data transfer mode for transferring the third data signal between the input / output device and the processor by using the connected third bus and first bus. The information processing apparatus is characterized by enabling independent data transfer modes including the data transfer modes of

This makes it possible to maximize the usage efficiency of the three types of buses.

Further, in order to achieve the above object, in the present invention, three kinds of buses, that is, a processor bus, a memory bus and a system bus are connected in at least a trifurcated manner, and any two kinds of the three kinds of buses are connected. During the interlocking operation, another type of bus is configured to be able to operate independently.

That is, according to the present invention, a connection device such as a processor bus to which at least one processor is connected, a memory bus connected to a main memory, and at least one input / output device (hereinafter referred to as I / O device) are connected. Further, a control means for connecting at least three types of system buses to each other is provided, and the control means enables interconnection of various buses.

That is, according to the present invention, the bus system of the information processing apparatus is a system in which a processor bus to which at least one processor is connected, a memory bus to which main memory is connected, and at least one connecting device are connected. A bus and these three types of buses are connected to each other, and a connection control means for interconnecting these three types of buses is provided.

According to the present invention, the connection control means includes data path switching means for connecting the data buses of the three types of buses to each other and transferring data on these buses, and control buses for the three types of buses. A bus which is connected to the address bus, transfers control signals and addresses on these buses to each other, and generates a data path control signal to the data path switching means.
It consists of a memory connection controller.

[0016] Preferably, the data path switching means and the bus / memory connection controller are individually or integrally formed on one integrated circuit.

Furthermore, in the present invention, the number of the three types of buses is not one, and even when any of the three types of buses is a plurality, the connection control means is similarly configured and these buses can be interconnected. Can be

In the above-described configuration of the present invention, three types of buses, that is, a processor bus, a memory bus, and a system bus are connected to each other in at least a trifurcated manner, so that, for example, a processor on the processor bus can store main memory on the memory bus. In the case of the processor main memory access for accessing the memory, the data is transferred only via the processor bus and the memory bus, and does not pass through the system bus, so that the system bus can operate independently. On the other hand, in the case of DMA in which the connected device on the system bus accesses the main memory on the memory bus, the data is transferred only via the system bus and the memory bus, and does not pass through the processor bus. Therefore, the processor bus operates independently. It becomes possible to do.

This makes it possible to maximize the use efficiency of the three types of buses.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. First, a first embodiment of the present invention will be described with reference to FIGS. Of these, FIGS. 2 and 3 show configuration diagrams of a bus system in the prior art, which will be described in detail here for comparison with the present invention.

1, 2 and 3, in common, 1
Reference numeral 01 is N (N is an integer) processors, 102 is a cache memory system (cache), 104 is a main memory, and 105 is an M (M is an integer) system bus connection device. As the system bus connection device 105, a disk / file controller,
A so-called input / output (I / O) device such as a drawing / display system controller or a network / communication system controller is shown. 111 is a processor bus, 112 is a memory bus, 1
Reference numeral 13 is a system bus. Then, in FIG.
3 is a three-way connection controller, 201 and 301 in FIGS. 2 and 3 are bus connection controllers, 202 and 3,
Reference numeral 02 is a memory connection controller.

In the conventional bus system shown in FIGS. 2 and 3, the system bus 113 and the memory bus 11 are shown in FIG.
2 is independently connected to the processor bus 111 by the bus connection controller 201 and the memory connection controller 202. On the other hand, in FIG. 3, the processor bus 111 and the memory bus 112 are independently connected to the system bus 113 by the bus connection controller 301 and the memory connection controller 302, respectively.

In the configuration of FIG. 2, the system bus 11
In the DMA operation for transferring data between the connection device 105 of No. 3 and the main memory on the memory bus 112,
Via the processor bus 111. Therefore, the independent operation of the processor bus 111 such as data transfer between the processor 101 and the cache 102 or between the plurality of processors 101 cannot be performed simultaneously with the DMA operation. On the other hand, in the configuration of FIG. 3, in the so-called processor main memory access in which data is transferred between the processor 101 and the main memory 104, the system bus 113 is used, so that a plurality of system bus connection devices are connected. System bus 1 for data transfer between 105
13 independent operations cannot be performed simultaneously with processor main memory access.

On the other hand, in the bus system of FIG. 1 which is the first embodiment of the present invention, the three types of buses, the processor bus 111, the memory bus 112 and the system bus 113, are
It is configured to be connected in a three-way path by the three-way path connection controller 103. Therefore, in the case of the DMA operation, it does not go through the processor bus 111.
Eleven independent operations can be performed simultaneously with the DMA operation. Further, in the case of processor main memory access, since it does not go through the system bus 113, the system bus 11
3 independent operations can be executed simultaneously with processor main memory access. As a result, even in the case of DMA and processor main memory access, the usage efficiency of the three types of buses can be maximized.

An example of performance evaluation of the bus system of the first embodiment of the present invention shown in FIG. 1 and the conventional bus system shown in FIGS. 2 and 3 will be described below, and the first embodiment of the present invention will be described. The effect of is quantitatively explained.

In the bus system of FIGS. 1, 2 and 3, the maximum data throughput of the processor bus 111 is 400 megabytes / second, the maximum data throughput of the memory bus 112 is 400 megabytes / second, and the system bus 1
The maximum data throughput of 13 is 200 megabytes / second. Further, the main memory access ratio in the processor bus 111 is 40%, the DMA ratio in the system bus 113 is 70%, and the bus connection controller 201
And the maximum bus acquisition ratio of 301 is 50%. Under the above conditions, the performance evaluation of each bus system when the processor bus 111 and the system bus 113 both attempt to operate at the maximum data throughput is as follows.

First, in the conventional bus system shown in FIG. 2, if the system bus 113 tries to operate at a maximum throughput of 200 megabytes / second, 70% of that is 140%.
A request for DMA of megabytes / second is sent to the bus connection controller 201. Since the bus connection controller 201 can acquire the bus up to 200 megabytes / second, which is 50% of 400 megabytes / second, with respect to the processor bus 111, the bus connection controller 201 acquires all the DMA requests of 140 megabytes / second. As a result, the system bus 113 can operate at 200 MB / sec, but the processor bus 111 can operate at D
Substantially (400-140) = 260 due to MA requirement
Can only operate at megabytes / second. At this time, the processor main memory access becomes 104 megabytes / second, which is 40% of 260 megabytes / second. Therefore, the request to the memory bus 112 is (140 + 104) = 254.
It becomes megabyte / second, and the memory bus 112 can meet this demand. Summarizing the above, regarding the usage efficiency of the three types of buses in the conventional bus system of FIG. 2, the processor bus 111 is 260/400 = 65%, and the memory bus 11 is
2 is 254/400 = 63.5%, system bus 113
Is 200/200 = 100%.

Next, in the conventional bus system shown in FIG. 3, when the processor bus 111 tries to operate at the maximum throughput of 400 megabytes / second, 40% of the main memory access request of 160 megabytes / second is 40% of the bus connection controller 301. Sent to. Bus connection controller 3
01 can acquire the bus only up to 100 MB / sec, which is 50% of 200 MB / sec with respect to the system bus 113. Therefore, processor main memory accesses are only processed at 100 megabytes / second, resulting in processor bus 111 being 40% at 100 megabytes / second.
Therefore, it can only operate at 250 MB / sec. At this time, the system bus 113 is substantially (200-
100) = 100 megabytes / second. Therefore,
DMA requests are 70% of 100 megabytes / second 70
It will be megabytes / second. As a result, the request to the memory bus 112 becomes (100 + 70) = 170 megabytes / second, and the memory bus 112 can meet this request. In summary, the processor bus 111 has a utilization efficiency of 250 /
400 = 62.5%, memory bus 112 is 170/40
0 = 42.5%, system bus 113 is 100/200
= 50%.

On the other hand, in the bus system of FIG. 1 which is the first embodiment of the present invention, the processor bus 111
Tries to operate at 400MB / s, part 4
A 0% 160 MB / sec main memory access request is sent to the three-way junction controller 103. or,
When the system bus 113 tries to operate at 200 Mbytes / sec, 70% of the 140 Mbyte DMA requests are sent to the three-way junction controller 103. The three-way junction controller 103 combines the processor main memory access request and the DMA request with (160
+140) = 300 megabytes / second request is sent to the memory bus 112, and the memory bus 112 can meet this request. Therefore, the processor bus 111 can operate at 400 megabytes / second and the system bus 113 can operate at 200 megabytes / second. From the above, the usage efficiency of the three types of buses in the bus system of the first embodiment of the present invention shown in FIG. 1 is 400/400 = 100 for the processor bus.
%, The memory bus 112 is 300/400 = 75%, and the system bus 113 is 200/200 = 100%.

The above results are shown in Table 1. As is clear from Table 1, it is understood that the bus system of FIG. 1 according to the present invention maximizes the usage efficiency of the three types of buses.

[0031]

[Table 1]

Prior to the embodiments showing the specific construction of the present invention, the bus systems of the second and third embodiments of the present invention will be described with reference to FIGS. 7 and 8.

In FIGS. 7 and 8, reference numerals 701 and 703 denote single configuration processors 1 to N capable of connecting individual cache memory systems (Cache), and 801 denotes N multi-configuration processors capable of connecting individual cache memory systems. Is. Reference numerals 711 and 712 denote processors 701 and 703 having a single configuration and a four-way connection controller 7, respectively.
Reference numeral 705 denotes a processor bus for connecting 05, and 705 denotes a four-way connection controller for connecting the processor buses 711 and 712, the memory bus 112 and the system bus 113. or,
Reference numerals 702, 704 and 802 denote processors 701 and 701, respectively.
703 and 801 are cache memory systems that are individually connected. The system bus connection device 10
Reference numeral 5 is an I / O device similar to that of the previous embodiment.

In the second embodiment of the present invention shown in FIG. 7, three kinds of four buses, that is, two processor buses 711 and 712, a memory bus 112 and a system bus 113 are connected by a four-way connection controller 705. They are connected in a fork shape. Processors 701 and 703 are stand-alone processors to which separate cache memory systems 702 and 704 can be connected. Therefore, the processor 70
Although 1 and 703 can directly access the respective individual cache memories 702 and 704 without going through the processor bus, they cannot share the processor bus.

In FIG. 7, the four-way junction controller 7
05 controls the connection of four buses of three types,
The communication between the processors 701 and 703 can be performed in parallel with the DMA, or the main memory access by the processor 701 and the system bus access by the processor 703 can be performed in parallel.

As a result, in the present embodiment as well as in the previous embodiments, it is possible to maximize the usage efficiency of the four buses of three types.

FIG. 8 is similar to the first embodiment shown in FIG.
The three types of buses, the processor bus 111, the memory bus 112, and the system bus 113, are the three-way connection controller 1.
03, it has the structure connected on the three-way road. Processor 801 is a separate cache memory system (cach
e) is a multi-configuration processor that can be connected. Therefore, each of the processors 801 can access the individual cache memory 802 without going through the processor bus,
Also, the processor bus 111 can be shared. Further, in the bus system of the third embodiment of the present invention shown in FIG.
Similar to FIG. 1, it is possible to perform an independent operation of the DMA and the processor bus 111 in parallel, or an operation of accessing the main memory from the processor bus 111 and the operation of the system bus 113 in parallel. Similar to the first embodiment, the usage efficiency of the three types of buses can be maximized.

Next, a concrete embodiment of the main part of the above-mentioned embodiment of the present invention will be described in detail with reference to FIGS. 4, 5 and 6. In particular, the detailed configuration of the three-way junction controller 103 of the first and third embodiments shown in FIGS. 1 and 7 will be described, but the four-way junction controller 705 shown in FIG. 7 can be similarly configured.

Now, FIG. 4 shows a three-way connection controller 10.
3 shows a configuration diagram of two integrated circuits 3; In FIG. 4, the three-way connection controller 103 includes a processor bus 111, a memory bus 112, and a system bus 113.
Are connected. These buses are address buses 411, 414, 417, control buses 412, 415, and
418 and data buses 413, 416, and 419. In this embodiment, the three-way junction controller 103 is composed of two integrated circuits, that is, a bus / memory connection controller 401 and a data path switch 402. However, the three-way junction controller 103 is
It can also be configured by one or three or more integrated circuits.

The data path switch 402 connects the three types of data buses, that is, the processor data bus 413, the memory data bus 416, and the system data bus 419 in a three-way path. Then, in accordance with the data path control signal 420 output from the bus / memory connection controller 401, the three types of data buses 413, 416, and 419 are connected and disconnected,
And control the data input / output direction. On the other hand, the bus / memory connection controller 401 is connected to the processor address bus 411, the processor control bus 412, the system address bus 417, and the system control bus 418. Then, the states of the processor bus 111 and the system bus 113 are monitored. The memory address bus 414, the memory control bus 415, and the data path control signal 412 are output to output the main memory 104 and the data path switch 40.
Control 2 The data path control signal 412 will be described in detail later.

The bus / memory connection controller 401 is
When a processor main memory access is requested from the processor bus 111, the processor bus 111 and the memory bus 112 are interlocked and the system bus 113 is independently operated. Further, when DMA is requested from the system bus 113, the system bus 113 and the memory bus 11
2 are interlocked to operate the processor bus 111 independently. Also, from the processor bus 111 to the system bus 1
When there is an access request to the processor bus 111 or an access request to the processor bus 111 from the system bus 113, the processor bus 111 and the system bus 113 are interlocked. Further, when the request from the processor bus 111 and the request from the system bus 113 compete with each other, for example, when both request memory access at the same time, a wait operation is performed on one of the buses. It has a function to perform arbitration control.

FIG. 5 shows the data path switch 40 shown in FIG.
It is a figure which shows the internal structure of one Example of No. 2. In FIG. 5, reference numerals 507, 508, and 509 denote data input / output drivers connected to the processor data bus 413, the memory data bus 416, and the system data bus 419, 501 and 5, respectively.
02 and 503 are data latch circuits (Latch), 504,
Reference numerals 505 and 506 are data selectors. The decoder circuit 510 decodes the data path control signal 420 output from the bus / memory connection controller 401, and outputs the output enable signals (Enable) 511, 512, 513 of the input / output buffers 507, 508, 509.
Then, select signals (Select) 514, 515, 516 of the data selectors 504, 505, 506 are generated.

The data latches 501, 502 and 503 have processor data buses 413 and memory data buses 4 respectively.
16. Input data from the system data bus 419 is latched. The selectors 504, 505 and 506 are respectively a processor data bus 413, a memory data bus 416,
The output data to the system data bus 419 is selected from the input data from the other two types of data buses. As a result, it is possible to control the input data from any one of the three types of data buses to be output to both of the other two types of data buses, or to output the data to only one side and not to the other side. It can be carried out. Therefore, according to the data path control signal 420, interlocking operation of all three data buses,
Alternatively, any two of the three types of interlocking actions and the other one type of independent actions can be performed.

FIG. 6 is a diagram showing an embodiment of the internal configuration of the bus / memory connection controller 401 in FIG. In FIG. 6, 601, 602, 603, and 604 are input / output drivers, and 605, 606, 607, and 608 are latch circuits (Latch). Reference numerals 609 and 610 are decoder circuits, 611 and 612 are encoder circuits, 613 is a sequencer which is a logical operation unit, and 614 is a decoder circuit.
Reference numeral 615 is a selector, 616 is a memory control signal generation unit, and 617 is a data path control signal generation unit.

Input signals from the processor address bus 411, the processor control bus 412, the system address bus 417, and the system control bus 418 are input / output drivers 601, 602, 603, and 604, respectively, and latch circuits 605, 607, and 606. , 608.
Input from two types of address buses, latch circuit 605,
The addresses latched by 606 are the decoder circuits 6 respectively.
It is decoded at 09 and 610. The decoding result is 2
Seed control buses 412, 418 and the data of the latch circuits 607, 608 which are the signal inputs from the control buses 412, 418, respectively, by the encoder circuits 611 and 612.
11 and the signal indicating the state of the system bus 113. As a result, the bus / memory connection controller 401 causes the processor bus 111 and the system bus 11 to operate.
The three states can be monitored.

Processor bus 111 and system bus 1 encoded by encoder circuits 611 and 612
The status signal of 13 is the sequencer 613 which is a logical operation unit.
Entered in. The sequencer 613 has two types of buses 11.
Correspondence to each bus and operation of the memory bus 112 are calculated from the status signals 1 and 113, and output as code information. The sequencer 613 includes a general-purpose microprocessor and a dedicated hardware configuration.

The code information output from the sequencer 613 is decoded by the decoder circuit 614, and the output enable signals 618, 619, 620, 621 of the input / output drivers 601, 602, 603, 604, the select signal 622 of the selector circuit 615, the memory. Control signal generator 6
16, a memory control code 623 to the data path control signal generation unit 617, a data path control code 624, and a control output signal 625 to the processor control bus 412 and the system control bus 418 via the input / output drivers 602 and 604, respectively. It is output as 626.

The input / output driver 601 is the system bus 1
When an access from 13 to the processor bus 111 occurs, the input / output address from the system address bus 417 is output to the processor address bus 411. The input / output driver 602 is also connected to the processor control bus 412 by
A control output signal 625 defined by the specifications of the processor bus 111 is output. On the other hand, the input / output driver 603 outputs the input / output address from the processor address bus 411 to the system address bus 417 when the processor bus 111 accesses the system bus 113. The input / output driver 604 also outputs a control output signal 626 defined by the specifications of the system bus 113 to the system control bus 418.

When an address is input from the processor address bus 411 and the system address bus 417 and an access to the memory bus 112 occurs, the selector circuit 615 selects one of them to select the memory address bus 4.
It outputs to 14. The memory control signal generation unit 616 functions as a code conversion circuit, converts the memory control code 623 output by the decoder circuit 614 into a memory control signal defined by the specifications of the memory bus 112, and converts the memory control signal.
Output to 15. The data path control signal generation unit 617 also functions as a code conversion circuit, and converts the data path control code 624 output from the decoder circuit 614 into a data path control signal 420 for the data path switch 402 and outputs the data path control signal 420.

The three-way junction controller 10 described in detail above.
The bus / memory connection controller 401 in 3 can control connection, disconnection, wait, etc. of three types of buses.

Next, one embodiment of various data and signals in the above-mentioned three-way junction controller 103 will be described in detail with reference to FIGS. 9 to 19.

FIG. 9 shows a data path control signal 420 output from the bus / memory connection controller 401 to the data path switch 402 and the decoder 51 corresponding thereto.
I / O drivers 507, 508, 5 decoded with 0
09 enable signals 511, 512, 513 and data selectors 504, 505, 506 select signal 51
4, 515 and 516 are shown. In the figure, the master, slave, and read / write columns at the top are the master / slave of data transfer, and the data transfer is read / write from master to slave. It means transfer. In the remaining part of the uppermost stage, the above-mentioned signal 5 in FIG.
The signal names corresponding to 11 to 516 are described. The DT-CNT in the rightmost column on the top is the data path control signal 420. The data path control signal (DT-CNT) 420 is represented by 3 bits in this embodiment. In the idle state (Idel) in which nothing is transferred, the DT-CNT 420 is 0 (“000”).

Each enable signal (DIR-P,
DIR-M, DIR-S) 511, 512, 513 are
Each of the input / output drivers 507, 508, and 509 is “0” when input, and is “1” when output. The select signal (SEL-P) 514 is “0” when the selector 504 selects the memory bus 112 side, the system bus 113.
It is "1" when the side is selected. In addition, the select signal (S
The EL-M) 515 is “0” when the selector 505 selects the processor bus 111 side and “1” when the system bus 113 side is selected. Furthermore, the select signal (S
EL-S) 516 is “0” when the selector 506 selects the processor bus 111 side and “1” when the memory bus 112 side is selected. According to this figure, the DT-CN input to the decoder 510 of the data path switch 402 is input.
By T420, the control of the selectors 504 to 506 and the input / output drivers 507 to 509 in the data path switch 402 can be executed, respectively, and the connection directions of the three types of buses can be controlled.

Next, the operation of the three-way junction controller 103 according to the present invention will be described with reference to FIG.
19 is a detailed block diagram of the bus connected to H.3 and FIG.
7, the timing chart of FIG. 18 will be described.

In these figures, the same symbols as those in FIGS. 1 and 4 mean the same items. Reference numerals 1910 and 1911 denote a DMA master I / O device and a slave I / O device corresponding to the previous system bus connection device 105, respectively. In FIG. 19, an acknowledge signal (ACK) 19
Reference numeral 02 denotes a response signal to the processor 101, which indicates confirmation of data at the time of reading and fetching of data at the time of writing.

Row address strobe signal (RAS) 1
903, column address strobe signal (CAS) 19
04 and write enable signal (WE) 1905 are part of the memory control signals sent to the memory control bus 415 of the main memory 104. The address selection signal (AD-MPX) is an internal signal of the bus / memory connection controller 401, and outputs a row address when the signal is high and a column address when the signal is low. System bus ground signal (S-GNT) 1906
Is a system bus connection device 105, which grants permission to use the system bus 113 to the I / O device 1910 that can be a DMA master, and enables it to become a DMA master. The address / data strobe signal (S-STB) 1907 is output by the system bus master, and is a DMA master I / O during DMA access.
The device 1910 outputs the data, and the bus / memory connection controller 401 outputs the data during processor I / O access, and outputs the address during a read operation, and outputs both the address and data during a write operation. The system bus slave response signal (S-ACK) 1908 is a response signal of the system bus slave, and is output by the bus / memory connection controller 401 in the case of DMA access, and slave I in the case of processor system bus I / O access.
/ O device 1911 outputs. Data is confirmed at the time of reading, and data is taken at the time of writing. S-GN
T1906, S-STB1907, S-ACK190
8 and a signal indicating whether read / write (S-REA
D) 1909 belongs to the control output signal 626 which is sent to the system control bus 418. System bus address (S
-ADD) is sent to the system address bus 417.
The system bus read / write signal (S-REA
D) indicates a lead when high (H).

FIG. 16 shows a bus memory connection controller 40.
It is a figure which shows one Example of the state transition of the sequencer 613 of No.1. 10 to 15 are diagrams showing signals output at a plurality of steps of each state transition of each transfer type shown in FIG. 16, respectively, processor main memory read, processor main memory write, and processor system bus device. It corresponds to read, processor system bus device write, DMA read, and DMA write.
The mark "○" indicates the assertion of the signal, and S-READ190
“H” and “L” in 9 mean that signal values high and low are output, respectively. Also, the bar above the signal name means that the signal is negative logic.

In FIG. 16, in step S2 of the processor system bus device read corresponding to FIG. 12, the system bus slave waits for data confirmation. In step S3 of the processor system bus device write corresponding to FIG. 13, a write response wait is performed. In step S1 of the DMA read corresponding to FIG. 14, the S-STB reception waiting is performed, and the transition destination to the next step S2 is determined according to the read / write determination when the S-STB is received. Also, in step S8 of DMA read,
In S5 of DMA write, negation waiting of the S-STB of the DMA master is performed.

In the time charts of FIGS. 17 and 18, which are the time charts of the transfer defined by FIGS. 9 to 16, what is indicated by () is the output source of each signal.

That is, (BMCC) is output from the bus memory connection controller 401, and (I / O) is a DMA master I / O device 1910 or a slave I that is a slave of the processor system bus I / O access. / O device 1911 respectively.

Now, the data path switch 40 shown in FIG.
The second latch circuits 501, 502, and 503 are composed of edge trigger flip-flops, and are latched at the rising edge of the clock (CLK) shown in FIGS. A start signal (START) 1901 is a transfer start signal output from the processor 1, and the address is latched at the rising edge of the clock (CLK) from which it is output for use. Otherwise, M-ADD indicates the memory address sent to memory address bus 414. Also, P-Dat
a, M-data, and S-data represent data sent to the processor data bus 413, the memory data bus 416, and the system data bus 419, respectively. Furthermore, P-Latc
h, M-Latch and S-Latch are latch 501,
Data latched in 502 and 503 are shown.

At the step S3 of the processor system bus device write shown in FIG. 13, one cycle is waited for by waiting for S-ACK assertion. Moreover, FIG.
In step S2 of the processor system bus device read indicated by 2, a wait is entered for two cycles due to the wait for S-ACK assertion. Then, the DM shown in FIG.
It is clear from FIG. 16 that the wait due to the S-STB assertion wait in the A read step S1 is one cycle, and the wait due to the S-STB negate wait is one cycle in the step S3.

In FIG. 18, in step S1 of the DMA write, the wait due to the S-STB assert wait is 1 as well.
Although the cycle has been entered, the waiting for negation in step S5 is executed without waiting.

By operating the bus memory connection controller 401 and the data path switch 402 shown in FIGS. 4, 5 and 6 by the method shown in FIGS. 9 to 18, which has been described in detail above, the operation shown in FIG. The operation of one embodiment of the trifurcated connection controller 103 has been understood.

Four-way connection controller 70 shown in FIG.
Although the configuration and operation of the 5 and the like will not be described in detail here,
It can be easily understood from the configuration and operation of the above-mentioned three-way connection controller.

Further, in the above description of FIG.
Although the processor bus 111, the memory bus 112, and the system bus 113 are all address / data separation type buses, it goes without saying that the present invention is also applicable to an address / data multiplex type bus. For example, when the processor bus 111 and the system bus 113 are address / data multiplexing buses, in FIG. 4, one processor address bus 411 and one processor data bus 413, and one system address bus 417 and one system data bus 419 are provided. Of the bus / memory connection controller 401 and the data path switch 402. In addition, it goes without saying that various modifications can be made under the basic concept of the present invention regardless of the above-described embodiments.

[0067]

As described above, according to the present invention described in detail above, while at least two of the at least three types of buses are operating in conjunction with each other, one or more other buses can operate independently. Therefore, there is an effect of maximizing the usage efficiency of each bus. In particular, when a plurality of processors are connected to the processor bus, or when a cache memory system is connected, etc., between the DMA operation and the plurality of processors,
Alternatively, the data transfer between the processor and the cache memory system can be performed simultaneously, and the processor main memory access and the data transfer between a plurality of system bus connection devices can be performed simultaneously.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of a bus system of the present invention.

FIG. 2 is a schematic configuration diagram of a conventional bus system.

FIG. 3 is another schematic configuration diagram of a conventional bus system.

FIG. 4 is a schematic configuration diagram showing an embodiment of the three-way junction controller 103 in the first embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a data path switch 402 in an example of the three-way junction controller 103 in the first example of the present invention.

FIG. 6 is a block diagram showing an example of a bus / memory connection controller 401 in an example of the three-way junction connection controller 103 in the first example of the present invention.

FIG. 7 is a schematic configuration diagram showing a second embodiment of the bus system of the present invention.

FIG. 8 is a schematic configuration diagram showing a third embodiment of the bus system of the present invention.

FIG. 9 is a data path switch 40 of the present invention shown in FIG.
2 is a diagram showing a correspondence between a data path control signal 420 decoded by a decoder 510 in 2 and a decoding result thereof. FIG.

FIG. 10 is a diagram showing a relationship between a data path control signal 420 and various signals in each step of state transition in the case of processor main memory read in the embodiment of the present invention.

FIG. 11 is a diagram showing a relationship between a data path control signal 420 and various signals in each step of state transition in the case of processor main memory write in the embodiment of the present invention.

FIG. 12 is a diagram showing the relationship between the data path control signal 420 and various signals in each step of the state transition in the case of processor system bus device read in the embodiment of the present invention.

FIG. 13 is a diagram showing a relationship between a data path control signal 420 and various signals in each step of state transition in the case of processor system bus device write in the embodiment of the present invention.

FIG. 14 is a data path control signal 4 in each step of the state transition in the case of DMA read in the embodiment of the invention.
The figure which shows the relationship between 20 and various signals.

FIG. 15 is a data path control signal 4 in each step of state transition in the case of DMA write in the embodiment of the invention.
The figure which shows the relationship between 20 and various signals.

FIG. 16 is a bus / memory connection controller 4 shown in FIG. 6;
The transition diagram which shows one Example of the state transition of the sequencer 601 in 01.

FIG. 17 is a time chart showing an example of data transfer defined by FIGS. 9 to 16.

FIG. 18 is another time chart diagram showing an example of data transfer defined by FIGS. 9 to 16;

19 is a diagram showing the signals appearing in FIGS. 17 and 18, and the three-way connecting controller 103 and each bus 11 in FIG.
The block diagram which showed concretely the connection with 1,112,113.

[Explanation of symbols]

101 ... N processors, 102 ... cache memory system, 103 ... Three-way connection controller, 104 ... main memory, 105 ... M system bus connection devices, 111 ... Processor bus, 112 ... Memory bus, 113 ... System bus.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Tetsuya Mochida             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi, Ltd. Microelectronics             Equipment Development Laboratory (72) Inventor Koichi Kimura             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi, Ltd. Microelectronics             Equipment Development Laboratory (72) Inventor Hitoshi Kawaguchi             Stock, 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa             Hitachi, Ltd. Microelectronics             Equipment Development Laboratory (72) Inventor Kazuharu Yuno             5-2-1 Omika-cho, Hitachi-shi, Ibaraki Stock             Hitachi, Ltd. Omika factory (72) Inventor Kazushi Kobayashi             810 Shimoimazumi, Ebina City, Kanagawa Prefecture Co., Ltd.             Hitachi Office System Design and Development Center             Within F-term (reference) 5B060 KA02 KA03 KA04 MB04                 5B061 FF07 GG02

Claims (12)

[Claims] 1. A processor bus for transferring data, control signals and data address signals, a processor connected to the processor bus, a memory bus for transferring data, control signals and data address signals, and connected to the memory bus A main memory, a system bus for transferring data, control signals, and data address signals, a display controller connected to the system bus, and a controller connected to the processor bus, the memory bus, and the system bus. And the controller transfers the first data between the processor and the memory by interlocking the processor bus and the memory bus among the processor bus, the memory bus, and the system bus. A first transfer mode, the processor bus, the A second transfer mode of transferring second data between the main memory and the display controller by interlocking the memory bus and the system bus among the memory bus and the system bus; A third transfer mode for transferring the third data between the display controller and the processor by interlocking the system bus and the processor bus among the memory bus and the system bus. A characteristic information processing device. 2. The information processing apparatus according to claim 1, wherein a cache memory is connected to the processor bus. 3. The information processing apparatus according to claim 1, wherein a cache memory is connected to the processor. 4. The controller controls the first data,
The information processing apparatus according to claim 1, further comprising a latch circuit that latches at least one of the second data and the third data. 5. A processor bus for transferring data, control signals and data address signals, a processor connected to the processor bus, a memory bus for transferring data, control signals and data address signals, and connected to the memory bus A main memory, a system bus for transferring data, control signals and data address signals, a network controller connected to the system bus, and a controller connected to the processor bus, the memory bus and the system bus. And the controller transfers the first data between the processor and the memory by interlocking the processor bus and the memory bus among the processor bus, the memory bus, and the system bus. A first transfer mode; A second transfer mode of transferring the second data between the main memory and the network controller by interlocking the memory bus and the system bus among the memory bus and the system bus; A third transfer mode for transferring the third data between the network controller and the processor by interlocking the system bus and the processor bus among the processor bus, the memory bus, and the system bus. An information processing apparatus having: 6. The information processing apparatus according to claim 5, wherein a cache memory is connected to the processor bus. 7. The information processing apparatus according to claim 5, wherein a cache memory is connected to the processor. 8. The controller controls the first data,
The information processing apparatus according to claim 5, further comprising a latch circuit that latches at least one of the second data and the third data. 9. A processor bus for transferring data, control signals and data address signals, a processor connected to the processor bus, a memory bus for transferring data, control signals and data address signals, and connected to the memory bus A main memory, a system bus for transferring data, control signals and data address signals, a file controller connected to the system bus, a controller connected to the processor bus, the memory bus and the system bus. And the controller transfers the first data between the processor and the memory by interlocking the processor bus and the memory bus among the processor bus, the memory bus, and the system bus. A first transfer mode, the processor bus, A second transfer mode of transferring the second data between the main memory and the file controller by interlocking the memory bus and the system bus among the memory bus and the system bus; A third transfer mode for transferring the third data between the file controller and the processor by interlocking the system bus and the processor bus among the bus, the memory bus, and the system bus An information processing device characterized by the above. 10. The information processing apparatus according to claim 9, wherein a cache memory is connected to the processor bus. 11. The information processing apparatus according to claim 9, wherein a cache memory is connected to the processor. 12. The information according to claim 9, wherein the controller has a latch circuit that latches at least one of the first data, the second data, and the third data. Processing equipment.