JP2003122328A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent display quality from degrading because the number of wiring and transistor elements is decreased substantially and also a write time of a video signal in pixels can be secured sufficiently. SOLUTION: For the period before a coincidence detection signal '1' is outputted from a coincidence detection circuit, a step voltage VS is continuously supplied to a pixel electrode 80 of each pixel by maintaining a gate transistor 20 in an ON state, and also when the coincidence detection signal '1' is outputted, the step voltage is cut off. Namely, an initial value of a reference voltage Vs is supplied to all the columns, the step voltage gradually increases with the increase in the reference voltage and the gate transistor is turned off when the reference voltage Vs gradually rises up to a voltage corresponding to a data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a DA for converting a digital video signal into an analog video signal.
The present invention relates to a display device including a converter.

[0002]

2. Description of the Related Art Generally, an active matrix type display device using liquid crystal or EL supplies an analog video signal to a pixel electrode of each pixel to change an electric field applied to the liquid crystal,
Liquid crystal display is performed by orienting the liquid crystal or changing the current supplied to the EL element. Here, a display device having a built-in DA converter for converting a digital video signal input from an external device into an analog video signal is known. Hereinafter, this type of display device will be described with reference to the drawings. FIG. 13 is a circuit diagram of a conventional liquid crystal display device. The pixel area is the pixel G in the first row.
S11, GS12, GS13, ... Are composed of a plurality of pixels arranged in a matrix of rows and columns as a whole by arranging the pixels G21, G22, G23 ,. ing.

An N-channel type pixel selection transistor 72 (thin film transistor) is provided for each pixel. The drain of the pixel selection transistor 72 has drain signal lines 61, 62, 6 from the horizontal drive circuit 30.
3, ... are connected. Further, gate signal lines 51, 52, ... From the vertical drive circuit 40 are connected to the gate of the pixel selection transistor 72, respectively.

For example, the specific structure of the pixel GS11 will be described. As shown in FIG. 14, the source 72s of the pixel selection transistor 72 is the pixel electrode 8 facing the liquid crystal 21.
It is connected to 0. An auxiliary capacitance 85 for holding the voltage of the pixel electrode 80 for one field period is provided. One terminal 86 of this auxiliary capacitance 85 is connected to the source 72s of the pixel selection transistor 72 and the other electrode 87. A common potential is applied to. Here, when the gate scanning signal (H level) is applied to the gate signal line 51, the pixel selection TFT 72 is turned on, the analog video signal is transmitted from the drain signal line 61 to the pixel electrode 80, and the auxiliary capacitor 85 is also provided. Held in. Pixel electrode 8
The video signal voltage applied to 0 is applied to the liquid crystal 21, and the liquid crystal 21 is oriented according to the voltage, whereby a liquid crystal display can be obtained. The configuration of each of the other pixels is exactly the same as above.

The structure of the horizontal drive circuit 30 is as follows. For example, 4-bit digital video signals D0 to D3 are supplied from the outside. Each column is provided with a first 4-bit latch circuit 1-1, 1-2, 1-3, ... For latching the digital video signals D0 to D3. These latch circuits 1-1, 1-2,
1-3 sequentially sample the digital video signals D0 to D3 in response to the sampling pulses SRP1, SRP2, SRP3, ... And hold data for one horizontal period.
Here, the sampling pulses SRP1, SRP2, SR
.. are created by the shift registers 10, 10, .... That is, the shift registers 10, 10, ...
Is a horizontal start signal STH according to the horizontal clock CKH
Sampling pulses are generated by sequentially shifting.

First latch circuits 1-1, 1-2, 1-3
The digital video signals D0 to D3 held by ... Are 4 based on the transfer pulse TP generated after the end of one horizontal period.
Bit-configured second latch circuits 2-1, 2-2, 2-
, 3 ... are simultaneously latched by the DA converters 3-1 and 3
After being converted into an analog video signal AD through -2, 3-3, ..., The drain signal lines 61, 62, 63 ...
Is output to.

Further, the vertical drive circuit 40 has a gate pulse obtained by sequentially shifting the vertical start signal STV according to the vertical clock CKV (becomes a high level for each horizontal period).
Are sequentially output to the gate signal lines 51, 52, ....

The DA converter 3-1 is shown in FIG.
Generally, a method using a decoding circuit as shown in FIG. This DA converter 3-1 is a digital video signal D0-
D3 is decoded by the decoding circuit 90, and one reference voltage Vj is selected from the 16 reference voltages V0 to V15 supplied to the 16 reference voltage lines and output from the output terminal 91. The decoding circuit 90 uses the digital video signal D
It is composed of a transistor array supplied with 0 to D3. For example, when the digital video signal is (0110), all the four series transistors 93 are turned on, at least one of the other series transistors is turned off, and the reference voltage V6 is selectively output. The DA converters 3-2, 3-3, ... Have the same configuration.

Next, the operation of the liquid crystal display device having the above structure will be described with reference to the timing chart shown in FIG. Here, one of the digital video signals D0 to D3 is
A description will be given focusing on the digital video signal D0 of the bit.
The same applies to the other bits. Digital video signal D
0 is data D0 in time series in synchronization with the horizontal clock CKH.
0, D01, D02 ... Therefore, the data D00 is
Latch circuit 1-1 according to the sampling pulse SRP1
And the data D01 is sampled by the sampling pulse SR.
It is latched by the latch circuit 1-1 according to P2.

Then, the all digital video signals D0 for one row are latched by the latch circuits 1-1, 1-2, 1- over one horizontal period.
After being latched by 3, ..., All data D00, D01, D02 latched by the latch circuits 1-1, 1-2, 1-3 ,. Two
Latched to -2,2-3. The latch data D00, D01, D02 are converted into DA converters 3-1, 3-2, 3
After being converted into an analog video signal AD through −3, ..., It is output to the drain signal lines 61, 62, 63.

[0011]

As described above, in the conventional liquid crystal display device, the DA converters 3-1, 3-2, 3-3, ... Are provided in the horizontal drive circuit 30 arranged in the peripheral region.・
Was provided. However, this type of DA converter
Since the method uses the decode circuit 90, the number of transistor elements and the number of reference voltage lines are significantly increased as the number of gray scales is increased. Therefore, there is a problem that it is difficult to achieve high definition and miniaturization. Therefore, the conventional liquid crystal display device has a limit in the number of gradations.

[0012]

The display device of the present invention comprises:
In a display device having a plurality of pixels and a DA converter for converting a digital video signal into an analog video signal, and supplying the analog video signal to each of the pixels for display, the DA converter is a reference digital signal. A reference data generation circuit that outputs data, a voltage generation circuit that changes in synchronization with a change in the reference digital data, and that generates a voltage corresponding to the reference digital data, a digital video signal data, and the reference digital data. Of the coincidence detection circuit that detects the coincidence and outputs the coincidence detection signal, and in the period before the coincidence detection signal is output, the voltage is continuously supplied to each pixel and the coincidence detection signal is output. It is characterized by comprising a gate circuit for interrupting the supply of the voltage at times.

According to such a configuration, unlike the conventional DA converter using the decoding circuit, the transistor array and the reference voltage line whose number increases exponentially depending on the number of bits are not included, and therefore, compared with the conventional one. The number of wires and the number of transistor elements can be significantly reduced.

Further, a gate circuit is provided for continuing the supply of the voltage to the pixels in the period before the coincidence detection signal is output, and for interrupting the supply of the voltage when the coincidence detection signal is output. Therefore, it is possible to sufficiently secure the writing time and prevent the deterioration of the display quality.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a display device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of the liquid crystal display device according to the first embodiment. For simplification, only one column of the horizontal drive circuit and one pixel of the pixel portion are shown. The vertical drive circuit 40 is similar to that described above.

It is assumed that 6-bit digital video signals D0 to D5 are supplied from the outside. The 6-bit first latch circuit 13 samples the digital video signals D0 to D5 in accordance with the sampling pulse SRP1 and holds data for one horizontal period. Here, the sampling pulse S
RP1 is created by the shift register 10. That is, the shift register 10 creates a sampling pulse by sequentially shifting the horizontal start signal STH according to the horizontal clock CKH.

The digital video signals D0 to D5 held in the first latch circuit 13 are simultaneously latched in the 6-bit second latch circuit 14 based on the transfer pulse TP generated after the end of one horizontal period. It is output to the drain signal line 61 after being converted into an analog video signal through a DA converter described later.

The DA converter comprises a reference data generating circuit 15,
It is composed of a staircase voltage generation circuit 16, a coincidence detection circuit 17, and an N-channel type gate transistor 20 (gate circuit). The reference data generation circuit 15 is composed of a kind of counter circuit and, as shown in FIG. 2, converts 6-bit reference digital data RD0 to RD5 into its initial value (0000
00), the maximum value (111111) =
Up to ²⁶ , it is incremented on the basis of the reference clock CLB and is output in time series over one horizontal period. In the next one horizontal period, the initial value (000000) is reset again and the maximum value (111111) is set. ) Is output cyclically. Here, the reference clock CKB
Is generated by dividing the horizontal clock CKH so that the number of clocks generated in one horizontal period becomes equal to the number of reference digital data (the number of gradations).

The staircase voltage generation circuit 16 has a staircase voltage VS corresponding to the reference digital data RD0 to RD5 which are incrementally output from the reference data generation circuit 15 in time series.
Generates (analog voltage). Where the staircase voltage VS
The change of (analog voltage) is synchronized with the change of the reference digital data RD0 to RD5 with the standard clock CLB (see FIG. 2). The staircase voltage generating circuit 16 can be simply configured by, for example, a ladder resistor that generates each staircase voltage VS and a switch group that switches and outputs each staircase voltage VS according to the reference digital data RD0 to RD5.

The coincidence detection circuit 17 includes 6-bit digital video signal data D0 to D5 and reference digital data RD0.
It is a circuit that detects a match of all corresponding bits of ˜RD5 and outputs a match detection signal. The coincidence detection circuit 17 is specifically six exclusive OR circuits 18-1 to which each bit of the digital video signal data D0 to D5 and each bit of the corresponding reference digital data RD0 to RD5 are input. 、…
18-6 and these exclusive OR circuits 18-1, ... 1
And a NOR circuit 19 to which the output of 8-6 is input. The exclusive OR circuit can be composed of, for example, the circuit shown in FIG. In FIG. 3, the input data XA is the inverted data of the input data A, and the input data XB is the inverted data of the input data B.

The exclusive OR circuit 18-1 outputs a logical value "0" when the digital video signal data D0 and the reference digital data RD0 match, and outputs a logical value "1" when they do not match. The same applies to the other exclusive OR circuits 18-1. Therefore, the digital video signal data D0-
When all the bit data of D5 and the reference digital data RD0 to RD0 match, the exclusive OR circuit 18-1, ... 18-
The outputs of 6 all have the logical value "0", and the NOR circuit 19 outputs the logical value "1" as the coincidence detection signal.

The gate transistor 20 is turned on in response to the coincidence detection signal "1", and outputs the staircase voltage VS (analog voltage) corresponding to the digital video signal data D0 to D5. As a result, digital / analog conversion is performed.

Next, the operation timing of the above-mentioned display device will be described. When the digital video signal is latched in the second latch 14, it is the same as that of the conventional example shown in FIG. Then, the scanning signal G1 is applied to the gate signal line 51.
The pixel selection transistor 72 is turned on by supplying (high level) only for one horizontal period. Then, the reference digital data RD0 ...
RD0 is output, and the staircase voltage VS in synchronization with it is output from the staircase voltage generation circuit 16. Then, the digital video signal data D0 to D5 and the reference digital data RD0 to R
During the period when D0 coincides, the gate transistor 20 is turned on, and the staircase voltage VS corresponding to the digital video signal data D0 to D5 is output to the drain line 61. As a result, the staircase voltage VS is applied to the pixel electrode 80 through the pixel selection transistor 72.

According to the DA converter having the above-described structure, the number of wirings and the number of transistor elements can be significantly reduced as compared with the case of using the conventional DA converter using the decoding circuit. When a 6-bit DA converter is configured with a conventional DA converter using a decoding circuit, 64 reference voltage lines and
384 transistors are required to configure the decoding circuit.

On the other hand, according to the DA converter of this embodiment,
The number of transistor elements in the coincidence detection circuit 17 is 97, and the number of wirings is 7. Further, since the reference data generation circuit 15 and the staircase voltage generation circuit 16 can be commonly used for all the coincidence detection circuits 17 arranged in the row direction, the increase in the number of transistor elements thereof is small from the whole.

The conventional voltage selection type DA converter, that is, the decoder circuit type, can instantly perform analog output with respect to input of digital data. On the contrary,
The timing selection DA converter of the present embodiment is rather inferior in responsiveness as compared with the conventional decoder circuit. However, since the DA converter incorporated in the active matrix type display device only needs to be able to perform digital / analog conversion in one horizontal period, the responsiveness of conversion is not so important. It is more important to reduce the number of components so that layout is possible between columns.

Although the display device having the above-described structure has a built-in 6-bit DA converter, the number of bits is not limited to this and can be appropriately selected as needed. Further, although the display device having the above-described configuration is a monochrome display, the present invention can be applied to a full color display. In this case, the first latch circuit 13, the second latch 14, and the DA converter may be provided for each of the R, G, and B digital video signals.

Although the present embodiment relates to a voltage-controlled liquid crystal display device, it can be applied to a current-controlled electroluminescence display device. In this case, as shown in FIG. 4, instead of the liquid crystal 21 of each pixel,
EL element 47 and drive transistor 48 of this EL element
Should be introduced. That is, a DA-converted analog voltage is applied to the gate of the drive transistor 48. The drive transistor 48 is driven by EL depending on its analog voltage.
By controlling the current flowing through the element 47, electroluminescence display can be performed. This point is
The same applies to the following embodiments.

Next, a display device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram of the liquid crystal display device according to the second embodiment. For simplicity, 1 bit of the horizontal drive circuit and 1 of the pixel section
Only bits are shown. The vertical drive circuit 40 is similar to that described above.

According to the display device of the first embodiment, the staircase voltage VS increases as the number of bits of the digital video signal increases.
The number of stairs increases. For example, in the case of 4 bits, the number of steps of the step voltage VS is 16, but in the case of 6 bits 64, 8
It is 256 bits. Since the staircase voltage VS changes cyclically with one horizontal period as a cycle, the period during which one staircase voltage VS is generated becomes shorter as the number of bits increases, and the digital video signal data D0 to D5 and the reference digital signal. The period in which the data RD0 to RD0 match, that is, the period in which the gate transistor 20 is turned on is also shortened.

Therefore, the data writing time, that is, the time for which the selected staircase voltage VS is applied to the pixel is shortened, and the writing becomes insufficient. For this reason, for example, when only one gradation is displayed, it is necessary to write a voltage to all the drain lines at the same time, so writing may not be in time and display quality may be deteriorated.

Therefore, in order to secure the data writing time, only the predetermined m bits of the n-bit digital video data are DA-converted by the timing selection DA converter of the first embodiment, and the remaining (N-
The m) bit is DA converted by a voltage selection DA converter. As a result, the write time can be secured and the number of bits can be further increased while suppressing the circuit scale.

In the present embodiment, when the digital video data is 6 bits, the lower 2 bits are DA-converted by the DA converter of the first embodiment, and the upper 4 bits are the conventional decoder. D by the system DA converter
A conversion is performed.

The display device according to this embodiment will be described below with reference to FIG. Since the configuration excluding the DA converter is the same as that of the first embodiment, detailed description thereof will be omitted.

The DA converter includes a reference data generation circuit 15
A, staircase voltage generation circuit 16A, 4-bit DA converter 10
0, a match detection circuit 17A, and N-channel type gate transistors 20A and 21A (gate circuit) connected in series. Hereinafter, the configurations of these circuits will be described in detail.

The reference data generation circuit 15A is composed of a kind of counter circuit, and as shown in FIG. 6, the reference digital data RD0 and RD1 of the lower 2 bits are converted into the initial value (0
Starting from 0), (01), (10), (11)
In this way, it increments based on the reference clock CLB and outputs in time series over one horizontal period. In the next one horizontal period, the initial value (00) is reset again and the maximum value (11 ) Is output cyclically. Here, the standard clock CKB is created by dividing the horizontal clock CKH, for example, so that the number of clocks generated in one horizontal period becomes equal to the number of reference digital data.

As shown in FIG. 6, the staircase voltage generation circuit 16A has a 2-bit reference digital data RD that is incrementally output from the reference data generation circuit 15A.
0, RD1 step voltage V0 to V that changes stepwise
Generates 15 (analog voltage). Step voltage V0 to V16
Is a reference voltage for a 4-bit DA converter 100 described later, and corresponds to lower 2-bit data for each of 16 types of analog voltages corresponding to higher 4-bit data R2 to R5 of a digital video signal. The small analog voltage is added stepwise.

Here, the change of the staircase voltage VS is synchronized with the change of the reference digital data RD0, RD1 with the standard clock CLB. As shown in FIG. 7, the staircase voltage generation circuit 16 selects one voltage VH among the four voltages divided by the ladder resistors RH1 to RH5 on the high voltage side according to the reference digital data RD0 and RD1. One of the four voltages VL divided by the switch SW1 for switching and the ladder resistors RL1 to RL5 on the low voltage side,
The switch SW2 is selected according to the reference digital data RD0, RD1 and ladder resistors R0 to R15 connected between the voltage VH and the voltage HL.
The staircase voltages V0 to V15 are taken out from the respective connection points of R16.

The 4-bit DA converter 100 has one step voltage Vj among 16 step voltages V0 to V16 (reference voltage) according to the 4-bit digital video signal data R2 to R5.
Select. As the 4-bit DA converter 100, the one using the decoder circuit described in the conventional example can be used.

The coincidence detection circuit 17A detects the coincidence between the lower 2 bits of the digital video signal data D0, D1 and the corresponding reference digital data RD0, RD1 and outputs a coincidence detection signal. The coincidence detection circuit 17A is, specifically, the exclusive OR circuits 18A-1 and 18A- to which each bit of the digital video signal data D0 and D1 and each bit of the corresponding reference digital data RD0 and RD1 are input. It can be composed of two. This exclusive OR circuit can be configured by the circuit shown in FIG. 3 as in the first embodiment.

The exclusive OR circuit 18A-1 outputs a logical value "0" when the digital video signal data D0 and the reference digital data RD0 match, and outputs a logical value "1" when they do not match. The exclusive OR circuit 18A-2 outputs a logical value "0" when the digital video signal data D1 and the reference digital data RD1 match, and outputs a logical value "1" when they do not match.

Therefore, the digital video signal data D0
~ D5 and all the bit data of the reference digital data RD0 to RD0 match, the match detection circuit 17A causes the logical value "0".
"0" is output. This logical value is inverted by an inverter, converted into a logical value “11”, and connected in series.
It is applied to the gates of the channel type gate transistors 20A and 21A.

The gate transistors 20A and 21A are turned on in response to the coincidence detection signal "00" and output the step voltage Vj corresponding to the digital video signal data D0 to D5. As a result, all bits of the digital video signal data D0 to D5 are converted from digital to analog. And
The staircase voltage Vj is output to the drain line 61 and applied to the pixel electrode 80 through the pixel selection transistor 72.

Contrary to the above-described embodiment, the upper 2 bits of the digital video data are detected by the coincidence detection circuit 1.
7A, and the lower 4-bit data is DA converter 1
00 may be input. As a result, the step voltage V0 to V15 which changes stepwise in response to the 2-bit reference digital data RD4 and RD5 which are incrementally output from the reference data generation circuit 15A are generated. In this case, as shown in FIG. 8, the staircase voltages V0 to V15 correspond to upper 2 bit data for each of 16 kinds of analog voltages corresponding to lower 4 bit data R0 to R3 of the digital video signal. A large analog voltage will be added stepwise.

Next, the number of bits allocated to the voltage selection type DA converter and the timing selection type DA converter will be described. By allocating as many bits as possible to the voltage selection method, it is possible to secure a long period of timing coincidence. On the other hand, voltage selection type DA
The number of transistors in the converter rapidly increases as the number of bits increases. Therefore, the voltage selection DA converter is set to 4 bits or less, and the remaining bits are timing selection DA.
It is desirable to use a converter.

Next, a display device according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a circuit diagram of the liquid crystal display device according to the third embodiment. For simplification, only one column of the horizontal drive circuit and one pixel of the pixel portion are shown. The vertical drive circuit 40 is similar to that described above.

The present embodiment solves the same problem as the second embodiment. That is, as described above, in the first embodiment, the data writing time, that is, the time for which the selected staircase voltage VS is applied to the pixel also becomes short, and writing becomes insufficient. For this reason, for example, when only one gradation is displayed, it is necessary to write a voltage to all the drain lines at the same time, so writing may not be in time and display quality may be deteriorated.

Therefore, in the present embodiment, in order to secure the data writing time, the gate transistor 20 is maintained in the ON state in the period before the coincidence detection signal "1" is output from the coincidence detection circuit 17. , Staircase voltage V
S is continuously supplied to the pixel electrode 80 of each pixel, and the supply of the staircase voltage VS is cut off when the coincidence detection signal "1" is output. That is, the reference voltage V
The initial value of s is supplied to all the columns, and gradually rises as the reference voltage Vs rises, and when it rises to a voltage according to the data, the gate transistor 20 turns off. As a result, a sufficient writing time for the drain line 61 and the pixel electrode 80 can be secured.

As shown in FIG. 9, the specific configuration is such that a P-channel type transistor 27 and an N-channel transistor 28 are connected in series between a power supply voltage Vdd and a ground voltage Vss, and the output at the connection point is an inverter INV1. , IN
It is supplied to the data holding circuit 29 which is composed of a holding loop formed by V2. P-channel transistor 2
The set signal SET is supplied to the gate of No. 7, and the output of the coincidence detection circuit 17 is supplied to the gate of the N-channel transistor 28. The output of the data holding circuit 29 (output of the inverter INV2) is supplied to the gate of the gate transistor 20.

That is, when the set signal is "0", the data "1" is set in the data holding circuit 29, and when the match detection circuit 17 outputs the match detection signal "1", the data holding circuit 29 is It is reset and holds the data “0”. In this respect, the circuit described above is a kind of flip-flop circuit. The rest of the configuration is similar to that of the first embodiment.

Next, the operation of the display device having the above configuration will be described. When the digital video signal is latched in the second latch circuit 14, it is the same as that of the conventional example shown in FIG. Then, the scanning signal G1 is applied to the gate signal line 51.
The pixel selection transistor 72 is turned on by supplying (high level) only for one horizontal period. Here, in the horizontal blank period before the start of the one horizontal period, the set signal SET becomes “0” and the data holding circuit 29 holds the data “1”, so that the gate transistor 20 is in the ON state. . Then, the reference data generation circuit 15 outputs reference digital data RD0 to RD5, and the staircase voltage generation circuit 16 outputs a staircase voltage VS synchronized with the reference digital data RD0 to RD5 so as to rise stepwise from the lowest level.

At this time, since the gate transistor 20 is maintained in the ON state, the staircase voltage VS is output to the drain line 61 through the gate transistor 20. As a result, the staircase voltage VS is always applied to the pixel electrode 80 through the pixel selection transistor 72. This ensures the writing time. Then, the digital video signal data D0 to D5 and the reference digital data RD0 to RD0
When the two match, the match signal “1” from the match detection circuit 17
Thus, the data in the data holding circuit 29 is rewritten to "0". Then, the transistor 20 is turned off, and the staircase voltage VS is no longer supplied to the drain line 61, so that the staircase voltage VS corresponding to the digital video signal data D0 to D5 can be finally written.

Next, a display device according to a fourth embodiment of the present invention will be described with reference to the drawings. Figure 10
It is a circuit diagram which shows the principal part of the liquid crystal display device which concerns on 4th Embodiment. This embodiment solves the same problem as that of the second embodiment. That is, as described above, in the first embodiment, for example, when only one gradation is displayed, it is necessary to write the voltage to all the drain lines at the same time. May be reduced.

Therefore, in this embodiment, in order to prevent such deterioration of display quality, each generation time of each staircase voltage VS is weighted.

As shown in FIG. 10, the concrete configuration is a data analysis circuit 31 for analyzing which gradation corresponds to a large amount of data in each data of the 6-bit digital video signals D0 to D5. Was set up. The data analysis circuit 31
64 comparators 32-1, 32-3, 32-3, which compare the digital video signals D0 to D5 with the 64 reference data (000000) to (111111) for a predetermined period.
..... Based on the comparison results of 32-64 and these comparators, 6-bit digital video signal D0 ...
64 counters 33-1, 33-2, 33-3, ... 33 for counting the number of times D5 matches each reference data
And -64. Thus, the number of appearances of data corresponding to the gradation can be known from the count value of the counter.

Then, the reference data generation circuit 15 outputs the reference digital data RD0 to RD5 obtained by incrementing the 6-bit data for a time proportional to the count value of the data analysis circuit 31. For example, the number of appearances of the digital video signal (0011) is counted by the counter 33-3, and when the count value is N, the time when the reference data (0011) is generated is N × Δt. Here, Δt is a unit time.

Then, the staircase voltage generating circuit 16 changes in synchronization with the change of the reference digital data RD0 to RD5 and generates the staircase voltage VS corresponding to the reference digital data RD0 to RD5. Here, the staircase voltage generation circuit 16
Is, for example, a ladder resistance generating each staircase voltage VS and each staircase voltage VS according to the reference digital data RD0 to RD5.
Can be easily configured by a switch group that switches and outputs. Note that the other configurations are similar to those of the first embodiment, and therefore description thereof will be omitted.

According to the above-described liquid crystal display device of the present embodiment, as shown in FIG. 11, each generation time of each staircase voltage VS is weighted according to the number of appearances of the digital video signals D0 to D5. You can For example, if the number of appearances of the digital video signals "2" and "12" (decimal conversion) is large, the generation time is lengthened in proportion thereto. In other words, the generation time is lengthened for data to which many pixels are supplied. On the contrary, for example, digital video signals “0”, “1”, “13”, ... (10
If the number of occurrences (decimal conversion) is small, the generation time is shortened proportionally. If a certain digital signal, for example, "10" (decimal conversion) is not counted at all, the data is skipped.

As described above, according to the present embodiment, each generation time of each staircase voltage VS is weighted. Therefore, if the number of appearances of the digital video signal is large, it is proportional to it.
Since the generation time of the corresponding reference digital data RD0 to RD5 is set long, it is possible to prevent the display quality from deteriorating when only one gradation is displayed.

In the above-described fourth embodiment, since the data analysis circuit 31 is newly provided as compared with the first embodiment, the circuit configuration becomes complicated accordingly. Therefore, as a modification of the fourth embodiment, as shown in FIG. 12, the generation time is longer than other gradations centering on the staircase voltage VS corresponding to the intermediate gradation, which is generally easy to visually recognize the decrease in brightness. Good to do. Here, the digital video signal D0
Since (100000) of D5 to D5 corresponds to the intermediate gradation, the reference digital data RD0 to RD5 should always have the data generation time around the data (100000) longer than the others. The reference data generation circuit 15 may be designed. Other circuit configurations are the same as those in the first embodiment.

As described above, since the generation time is set to be long centering on the staircase voltage VS corresponding to the intermediate gradation where it is easy to visually recognize the decrease in brightness, the decrease in brightness is less visible. Further, for other gradations, even if the number of data is large, it is considered that there is no problem because the decrease in brightness is relatively hard to be visually recognized.

In the above-described first to fourth embodiments, the reference data generating circuit 15 increments the reference digital data RD0 to RD5 and outputs them in time series, and the staircase voltage generating circuit 16 The staircase voltage VS that rises corresponding to the reference digital data RD0 to RD5 that is incrementally (increase) output from the reference data generation circuit 15 is generated. However, the reference data generation circuit 15 may decrement (decrease) the reference digital data RD0 to RD5 in time series, and output them. Along with this, the staircase voltage generation circuit 16 outputs the falling staircase voltage VS.

Further, the staircase voltage generating circuit 16 outputs the staircase voltage VS, but it does not necessarily have to be a staircase.

[0064]

According to the display device of the present invention, since the timing selection system is adopted, the number increases exponentially with the number of bits like a voltage selection system DA converter using a decoding circuit. Does not include transistor arrays or reference voltage lines. Therefore, the number of wirings and the number of transistor elements can be significantly reduced as compared with the related art.

Furthermore, since it is possible to secure a sufficient time for writing the video signal into the pixel, it is possible to prevent the display quality from deteriorating.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation of the liquid crystal display device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing an exclusive OR circuit.

FIG. 4 is a circuit diagram of a pixel of an electroluminescence display device.

FIG. 5 is a circuit diagram of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a timing diagram showing an operation of the liquid crystal display device according to the second embodiment of the present invention.

FIG. 7 is a circuit showing a staircase voltage generating circuit according to a second embodiment of the present invention.

FIG. 8 is a timing diagram showing an operation of the liquid crystal display device according to the second embodiment of the present invention.

FIG. 9 is a circuit diagram of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 10 is a circuit diagram showing a main part of a liquid crystal display device according to a fourth embodiment.

FIG. 11 is a timing chart showing an operation of the liquid crystal display device according to the fourth embodiment.

FIG. 12 is a timing chart showing an operation of the liquid crystal display device according to the fourth embodiment.

FIG. 13 is a circuit diagram of a conventional liquid crystal display device.

FIG. 14 is a circuit diagram showing a configuration of a pixel of a conventional liquid crystal display device.

FIG. 15 is a circuit diagram of a DA converter used in a conventional liquid crystal display device.

FIG. 16 is a timing chart showing an operation of a conventional liquid crystal display device.

[Explanation of symbols]

10 shift register 13,14 Latch circuit 15 Reference data generation circuit 16 staircase voltage generator 17 Match detection circuit 18 Exclusive OR circuit 19 Noah circuit 20 N-channel gate transistor 25 Precharge transistor 21 liquid crystal 25 Precharge transistor 27 P-channel transistor 28 N-channel transistor 29 Data holding circuit 30 Horizontal drive circuit 31 Data analysis circuit 40 Vertical drive circuit 47 EL element 48 drive transistor 51 gate signal line 61 drain wire 72 Pixel selection transistor 80 pixel electrodes 85 auxiliary capacity 90 Decoding circuit 93 series transistor 100 4-bit DA converter

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 623 G09G 3/20 623F 623R 641 641C F term (reference) 2H093 NA53 NC03 NC23 NC24 NC26 NC32 ND06 ND32 ND33 ND49 5C006 AA01 AA16 AF73 AF83 BB16 BC12 BC20 BF03 BF04 BF11 BF26 BF43 FA43 FA56 5C080 AA06 AA10 BB05 DD03 DD22 DD28 EE29 FF11 JJ02 JJ03 JJ04

Claims (7)

[Claims] 1. A display device comprising a plurality of pixels and a DA converter for converting a digital video signal into an analog video signal, and supplying the analog video signal to each of the pixels for display, wherein the DA conversion is performed. And a reference data generation circuit for outputting reference digital data, a voltage generation circuit for generating a voltage corresponding to the reference digital data while changing in synchronization with the change of the reference digital data, and digital video signal data. A coincidence detection circuit that detects a coincidence with the reference digital data and outputs a coincidence detection signal; and, in a period before the coincidence detection signal is output, continuously supplies the voltage to each of the pixels and detects the coincidence. A display device comprising: a gate circuit that cuts off the supply of the voltage when a signal is output. 2. The display device according to claim 1, wherein the reference data generation circuit generates reference digital data in which a plurality of bits of data is increased or decreased in time series. 3. The display device according to claim 1, wherein the voltage generation circuit generates a staircase voltage corresponding to the reference digital data. 4. A first latch circuit for latching the digital video signal in response to a sampling pulse, and a second latch circuit for latching the output of the first latch circuit in response to a transfer pulse generated after the end of one horizontal period. And a latch circuit,
4. The display device according to claim 1, wherein the output of the second latch circuit is input to the DA converter. 5. A flip-flop circuit that is set by a set signal generated in a horizontal blank period and reset by the coincidence detection signal, and an output of the flip-flop circuit is applied to a gate of the gate circuit, The display device according to claim 1, comprising a transistor to which the voltage is applied to a source. 6. The coincidence detection circuit includes n exclusive OR circuits to which each bit data of the digital video signal and each corresponding bit data of the reference digital data are input. The display device according to any one of claims 1 to 5. 7. The display device according to claim 6, further comprising a NOR circuit to which outputs of the n exclusive OR circuits are input.