JP2003116263A - Gate drive circuit of voltage-driven semiconductor device - Google Patents

Gate drive circuit of voltage-driven semiconductor device

Info

Publication number
JP2003116263A
JP2003116263A JP2001309421A JP2001309421A JP2003116263A JP 2003116263 A JP2003116263 A JP 2003116263A JP 2001309421 A JP2001309421 A JP 2001309421A JP 2001309421 A JP2001309421 A JP 2001309421A JP 2003116263 A JP2003116263 A JP 2003116263A
Authority
JP
Japan
Prior art keywords
circuit
voltage
gate
gate drive
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001309421A
Other languages
Japanese (ja)
Other versions
JP3882988B2 (en
Inventor
Akitake Takizawa
聡毅 滝沢
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2001309421A priority Critical patent/JP3882988B2/en
Publication of JP2003116263A publication Critical patent/JP2003116263A/en
Application granted granted Critical
Publication of JP3882988B2 publication Critical patent/JP3882988B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Power Conversion In General (AREA)
  • Inverter Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To make an actual output voltage match a command voltage of an inverter while the oscillation phenomenon of a voltage waveform, in an antiparallel recovery time of a diode connected in parallel with a device such as an IGBT or the like constituting an inverter or the like, is avoided. SOLUTION: A gate drive circuit of an IGBT comprises a filter circuit 18, a one-shot circuit 20, a logic operation circuit 22, etc. If the pulse period width of a gate command signal is shorter than 1/2 of a minimum off-period T, an off-operation is prohibited by the circuit 18 and, if the pulse period width is T/2-T, an off-period is forcibly changed to be T by the circuit 20, and, if the pulse period width is not shorter than T, the operation is continued as it is.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】この発明は、IGBT(絶縁
ゲート形バイポーラトランジスタ)などの電圧駆動形半
導体素子のゲート駆動回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate drive circuit for a voltage drive type semiconductor device such as an IGBT (insulated gate type bipolar transistor).

【0002】[0002]

【従来の技術】図2にIGBTを用いたインバータの主
回路図を示す。1は直流電源回路(交流入力のインバー
タの場合は整流器+電解コンデンサとなる)、2は直流
を交流に変換するIGBTおよびダイオードからなるイ
ンバータ部、3,4はIGBTの駆動(ドライブ)回
路、5はIGBT、6はIGBTに逆並列接続されたダ
イオード、7はモータなどの負荷である。
2. Description of the Related Art FIG. 2 shows a main circuit diagram of an inverter using an IGBT. 1 is a DC power supply circuit (in the case of an AC input inverter, it is a rectifier + electrolytic capacitor), 2 is an inverter section composed of an IGBT and a diode for converting DC to AC, 3 and 4 are IGBT drive circuits, 5 Is an IGBT, 6 is a diode connected in anti-parallel to the IGBT, and 7 is a load such as a motor.

【0003】図3に駆動(ドライブ)回路の詳細を示
す。この回路は、IGBT5aとダイオード6aおよび
IGBT5bとダイオード6bのそれぞれに対応して設
けられるが、以下では一方の回路について説明する。符
号8は駆動回路用電源、9,10はIGBTをそれぞれ
ターンオン,ターンオフさせるためのスイッチ素子、1
1,12はそれぞれターンオン用,ターンオフ用のゲー
ト抵抗で、上位および制御部13からオン指令信号S1
またはオフ指令信号S2を与えられて動作する。また、
反転回路14は上アーム側IGBTと下アーム側IGB
Tを交互にオン,オフさせるために接続されている。な
お、実際には上下アームが同時にオンしないようデッド
タイムを設ける必要があるが、ここでは直接関係がない
ので、無視することとした。
FIG. 3 shows details of the drive circuit. This circuit is provided corresponding to each of the IGBT 5a and the diode 6a and the IGBT 5b and the diode 6b, but one circuit will be described below. Reference numeral 8 is a power supply for a drive circuit, 9 and 10 are switch elements for turning on and off the IGBT, respectively.
Reference numerals 1 and 12 denote turn-on and turn-off gate resistors, respectively, which are turned on signal S1 from the host and control unit 13.
Alternatively, it operates by being supplied with the off command signal S2. Also,
The inverting circuit 14 includes an upper arm side IGBT and a lower arm side IGBT.
It is connected to alternately turn on and off T. It should be noted that in reality it is necessary to provide a dead time so that the upper and lower arms do not turn on at the same time, but since it is not directly related here, it was decided to ignore it.

【0004】[0004]

【発明が解決しようとする課題】図4にIGBTターン
オン時(時刻t0)における、対向アームダイオードの
逆回復時の電圧(VF)波形例を示す。図4(a)はダ
イオードがオンしている期間(対向アームのIGBTが
オフしている期間)が充分に長い通常の場合、図4
(b)はその期間が短くなった場合を示す。つまり、ダ
イオードがオンしている期間が充分に長いときはVF
形は図4(a)のように滑らかとなるのに対し、オンし
ている期間が短いと図4(b)のように激しく振動し、
最悪の場合は素子破壊を招く。
FIG. 4 shows an example of the voltage (V F ) waveform at the time of reverse recovery of the opposing arm diode at the time of IGBT turn-on (time t 0 ). FIG. 4A shows a case where the diode is on (the IGBT of the opposing arm is off) for a sufficiently long period in a normal case.
(B) shows the case where the period is shortened. That is, when the diode is on for a sufficiently long period, the V F waveform becomes smooth as shown in FIG. 4A, whereas when the diode is on for a short period, as shown in FIG. 4B. Vibrate violently,
In the worst case, the device is destroyed.

【0005】そこで、従来は図3に示すように振動現象
を生じない一定時間(T)以内のオンまたはオフパルス
を通過させないようフィルタ回路17,18を設けた
り、または特開2000−023471号公報(以下、
引用公報とも言う)のように、オフ時間の最小値を一定
時間Tになるように設定して対処している。しかし、こ
のようにすると、指令電圧値と実際の出力電圧値とが異
なる場合が生じることになり、モータ低速時の回転むら
の発生など、精度の良い制御ができなくなると言う問題
がある。したがって、この発明の課題は、振動現象を回
避しつゝ精度の良い制御を可能にすることにある。
Therefore, conventionally, as shown in FIG. 3, filter circuits 17 and 18 are provided so as not to pass an ON or OFF pulse within a fixed time (T) at which an oscillation phenomenon does not occur, or Japanese Patent Laid-Open No. 2000-023471. Less than,
(Also referred to as a cited document), the minimum value of the off time is set to be a constant time T to deal with the problem. However, in this case, the command voltage value and the actual output voltage value may be different from each other, which causes a problem that accurate control cannot be performed, such as occurrence of uneven rotation at low motor speed. Therefore, an object of the present invention is to avoid the vibration phenomenon and enable accurate control.

【0006】[0006]

【課題を解決するための手段】このような課題を解決す
るため、請求項1の発明では、電力変換装置を構成する
電圧駆動形半導体素子のゲート駆動回路において、一定
時間幅以内のパルス幅を持つゲート指令信号の通過を阻
止するフィルタ回路と、このフィルタ回路の出力信号を
トリガとして一定時間のワンショットパルス信号を生成
するワンショット回路と、このワンショットパルス信号
と前記フィルタ回路からの出力信号とを論理演算する論
理演算回路とを設け、この論理演算回路からの出力信号
をゲート指令信号とすることを特徴とする。この請求項
1の発明においては、前記電圧駆動形半導体素子の許容
オフ期間の最小時間幅をTとするとき、前記フィルタ回
路で阻止するゲート指令信号のパルス幅をT/2とし、
前記ワンショットパルス信号のパルス幅をTとすること
ができる(請求項2の発明)。
In order to solve such a problem, according to the invention of claim 1, in a gate drive circuit of a voltage drive type semiconductor element constituting a power converter, a pulse width within a fixed time width is set. A filter circuit that blocks passage of the gate command signal that it has, a one-shot circuit that generates a one-shot pulse signal for a fixed time by using the output signal of this filter circuit as a trigger, and this one-shot pulse signal and the output signal from the filter circuit And a logic operation circuit for performing a logic operation on the logic circuit, and an output signal from the logic operation circuit is used as a gate command signal. In the invention of claim 1, when the minimum time width of the allowable off period of the voltage driven semiconductor element is T, the pulse width of the gate command signal blocked by the filter circuit is T / 2,
The pulse width of the one-shot pulse signal can be T (the invention of claim 2).

【0007】[0007]

【発明の実施の形態】図1はこの発明の第1の実施の形
態を示す回路図である。これは、図3に示す従来例に対
し、フィルタ回路18の設定時間をT/2(T:振動現
象を生じない一定時間、または許容オフ期間の最小幅)
にするとともに、フィルタ回路18の出力信号S3の立
ち上がりエッジをトリガとするワンショット回路(ワン
ショットはTとする)20と、その出力信号S4と信号
S3との論理演算(論理和)を行なう論理演算回路22
とを付加して構成される。なお、オン側も基本的には同
様であり、図示の回路に代えて論理演算回路22の出力
を反転させて用いるようにしても良い。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention. This is because the setting time of the filter circuit 18 is set to T / 2 (T: a fixed time in which the vibration phenomenon does not occur, or the minimum width of the allowable off period) in comparison with the conventional example shown in FIG.
In addition, the one-shot circuit (one-shot is T) 20 triggered by the rising edge of the output signal S3 of the filter circuit 18, and the logic operation (logical sum) of the output signal S4 and the signal S3. Arithmetic circuit 22
It is configured by adding and. The ON side is basically the same, and the output of the logical operation circuit 22 may be inverted and used instead of the illustrated circuit.

【0008】上記のような構成により、オフ期間が短い
場合(T/2以内)はフィルタ回路18によってオフ動
作がなされず、また、オフ期間がT/2〜Tの場合はワ
ンショット回路20によってオフ期間は強制的にTとさ
れ、さらに、オフ期間がT以上の場合は従来と同様その
まま出力される。因みに、図3の従来例の場合はオフ期
間がT以下の場合は「0」とするものであり、また、引
用公報の場合はオフ期間がT以下の場合は「T」とする
ものと言うことができ、この発明は期間TをT/2以内
とT/2〜Tに分けることで、指令電圧値と実際のイン
バータ出力電圧値とを、上記のものに比べてより平均的
に等しくするものと言える。
With the above structure, the off operation is not performed by the filter circuit 18 when the off period is short (within T / 2), and by the one-shot circuit 20 when the off period is T / 2 to T. The off period is forcibly set to T, and when the off period is equal to or longer than T, it is output as it is as in the conventional case. Incidentally, in the case of the conventional example of FIG. 3, it is said that when the off period is T or less, it is set to “0”, and in the case of the cited publication, when the off period is T or less, it is set to be “T”. According to the present invention, by dividing the period T into within T / 2 and within T / 2 to T, the command voltage value and the actual inverter output voltage value are made more equal on average as compared with the above. Can be said to be a thing.

【0009】[0009]

【発明の効果】この発明によれば、短いオフパルスによ
る振動現象を回避しながら、平均的に指令電圧値と実際
のインバータ出力電圧値とを等しくすることが可能とな
り、その結果、モータ低速時の回転むらの発生などをな
くし、高精度のモータ制御が可能となる利点が得られ
る。
According to the present invention, the command voltage value and the actual inverter output voltage value can be made equal on average while avoiding the vibration phenomenon due to the short off pulse, and as a result, the motor output voltage value at the time of low motor speed can be made equal. It is possible to obtain the advantage that high-precision motor control can be performed by eliminating the occurrence of uneven rotation.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の第1の実施の形態を示す回路図であ
る。
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

【図2】IGBTを用いたインバータの一般的な例を示
す構成図である。
FIG. 2 is a configuration diagram showing a general example of an inverter using an IGBT.

【図3】図2のゲート駆動部を詳細に示す回路図であ
る。
FIG. 3 is a circuit diagram showing the gate driver of FIG. 2 in detail.

【図4】図3の動作説明図である。FIG. 4 is an operation explanatory diagram of FIG. 3;

【符号の説明】[Explanation of symbols]

1…直流電源回路、2…インバータ回路、3,4…ゲー
ト駆動部、5…IGBT(絶縁ゲート形バイポーラトラ
ンジスタ)、6…ダイオード、7…負荷(モータ)、8
…駆動用電源、9,10…スイッチ素子、11,12…
抵抗、13…制御部、14…反転回路、17,18…フ
ィルタ回路、20…ワンショット回路、22…論理演算
回路。
DESCRIPTION OF SYMBOLS 1 ... DC power supply circuit, 2 ... Inverter circuit, 3, 4 ... Gate drive part, 5 ... IGBT (insulated gate type bipolar transistor), 6 ... Diode, 7 ... Load (motor), 8
... Drive power supply, 9, 10 ... Switch element, 11, 12 ...
Resistors, 13 ... Control unit, 14 ... Inversion circuit, 17, 18 ... Filter circuit, 20 ... One-shot circuit, 22 ... Logical operation circuit.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 電力変換装置を構成する電圧駆動形半導
体素子のゲート駆動回路において、 一定時間幅以内のパルス幅を持つゲート指令信号の通過
を阻止するフィルタ回路と、このフィルタ回路の出力信
号をトリガとして一定時間のワンショットパルス信号を
生成するワンショット回路と、このワンショットパルス
信号と前記フィルタ回路からの出力信号とを論理演算す
る論理演算回路とを設け、この論理演算回路からの出力
信号をゲート指令信号とすることを特徴とする電圧駆動
形半導体素子のゲート駆動回路。
1. A gate drive circuit for a voltage-driven semiconductor element that constitutes a power conversion device, wherein a filter circuit that blocks passage of a gate command signal having a pulse width within a fixed time width, and an output signal of this filter circuit are provided. A one-shot circuit that generates a one-shot pulse signal for a certain period of time as a trigger and a logical operation circuit that logically operates the one-shot pulse signal and the output signal from the filter circuit are provided, and the output signal from the logical operation circuit Is a gate command signal, which is a gate drive circuit for a voltage drive type semiconductor device.
【請求項2】 前記電圧駆動形半導体素子の許容オフ期
間の最小時間幅をTとするとき、前記フィルタ回路で阻
止するゲート指令信号のパルス幅をT/2とし、前記ワ
ンショットパルス信号のパルス幅をTとすることを特徴
とする請求項1に記載の電圧駆動形半導体素子のゲート
駆動回路。
2. When the minimum time width of the allowable off period of the voltage-driven semiconductor element is T, the pulse width of the gate command signal blocked by the filter circuit is T / 2, and the pulse of the one-shot pulse signal is The gate drive circuit for a voltage-driven semiconductor device according to claim 1, wherein the width is T.
JP2001309421A 2001-10-05 2001-10-05 Gate drive circuit of voltage driven semiconductor device Expired - Fee Related JP3882988B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001309421A JP3882988B2 (en) 2001-10-05 2001-10-05 Gate drive circuit of voltage driven semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001309421A JP3882988B2 (en) 2001-10-05 2001-10-05 Gate drive circuit of voltage driven semiconductor device

Publications (2)

Publication Number Publication Date
JP2003116263A true JP2003116263A (en) 2003-04-18
JP3882988B2 JP3882988B2 (en) 2007-02-21

Family

ID=19128576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001309421A Expired - Fee Related JP3882988B2 (en) 2001-10-05 2001-10-05 Gate drive circuit of voltage driven semiconductor device

Country Status (1)

Country Link
JP (1) JP3882988B2 (en)

Also Published As

Publication number Publication date
JP3882988B2 (en) 2007-02-21

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