JP2003115616A - Tunnel junction device and method of fabricating the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tunnel junction device having good under-damp characteristic and a method of fabricating the same. SOLUTION: A superconducting device 100 comprises a substrate 101 formed of an oxide such as LSAT (La-Sr-Al-Ta-O) or magnesium oxide (MgO), a superconducting lower electrode 102 formed of high-temperature superconductor such as YBCO (Y-Ba2 -Cu3 -O7-x ), a barrier layer 103 obtained by conducting surface process to the superconducting lower electrode 102, a superconducting upper electrode 104 formed of a high temperature superconductor such as YBCO (Y-Ba2 -Cu3 -O7-x ), and a high dielectric constant insulator 105 formed of a high dielectric constant material such as STO (Sr-Ti-O3 ) or BTO (Ba-Ti-O3 ) and is provided closely to the junction area with between the superconducting lower electrode 102 and superconducting upper electrode 104.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tunnel junction device and a method of manufacturing the same, and more particularly to a tunnel junction device having an under dump characteristic and a method of manufacturing the same.

Superconducting devices have attracted attention as devices using tunnel junctions. The Josephson element is one of the superconducting devices. The superconducting single-flux quantum circuit using the Josephson device has the characteristics of ultra-high speed and low energy, and is expected as a constituent element of future high-speed information processing systems.

[0003]

2. Description of the Related Art The signal amplitude of a single flux quantum circuit using a Josephson element is as small as about 1 mV, and in order to exchange data with an existing semiconductor device, it is necessary to first amplify the voltage by a superconducting driver. As a superconducting driver, a non-latch type driver using a Josephson junction that can obtain an overdamped characteristic and a latch type driver using a Josephson junction that can obtain an underdamped characteristic have been proposed.

FIG. 1 is a voltage-current characteristic diagram showing the overdamped characteristic and the underdamped characteristic.

In FIG. 1, the horizontal axis represents applied voltage and the vertical axis represents current. Further, in FIG. 1, the solid line shows the over-dump characteristic and the broken line shows the under-dump characteristic.

A high temperature superconducting Josephson junction having an over-dump characteristic used for a non-latch type driver is relatively easy to manufacture, but has a problem that the output amplitude is small.

On the contrary, the high temperature superconducting Josephson device having the under-dump characteristic used for the latch type driver has a feature that a high output amplitude can be obtained with a small number of junctions. Not obtained yet.

In order to make the Josephson junction have an under dump characteristic, the junction capacitance may be increased. According to the computer simulation, the optimum junction capacitance is about 0.1 to 1 pF. The simplest method is to form a capacitor on the chip and connect it in parallel with the Josephson junction.

FIG. 2 is a block diagram of a conventional Josephson device having a large junction capacitance.

The Josephson element 1 has a structure including a substrate 11, a superconducting lower electrode 12, a superconducting upper electrode 13, an insulating layer 14, a Josephson junction 15 and a capacitor electrode 16.

The substrate 11 is composed of, for example, an oxide substrate. A superconducting lower electrode 12 is formed on the substrate 11. An insulating layer 14 is stacked on the superconducting lower electrode 12. The end faces of the superconducting lower electrode 12 and the insulating layer 14 are formed on the slope. Further, a barrier layer is formed on the end surface of the superconducting lower electrode 12, and the tunnel junction, that is,
The Josephson junction 15 is formed. Furthermore, the substrate 1
The superconducting upper electrode 13 is laminated on the end faces of the superconducting lower electrode 12 and the insulating layer 14 from 1. A Josephson junction is formed on the contact surface between the end surface of the superconducting lower electrode 12 and the superconducting upper electrode 13. Further, a capacitor electrode layer 16 is laminated on the insulating layer 14 so as to face the superconducting lower electrode 12. The capacitor electrode layer 16 is formed continuously with the superconducting upper electrode 13.

[0012]

However, since the superconducting device shown in FIG. 2 uses an ordinary insulating film having a low dielectric constant, it occupies a large area. Further, since the junction and the capacitor are connected by the wiring, there is a problem that parasitic inductance of the wiring is generated. It is known from computer simulations that the parasitic inductance cancels the effect of the capacitor and deteriorates the junction characteristics.

The present invention has been made in view of the above points, and an object of the present invention is to provide a tunnel junction device having good under-dump characteristics and a method for manufacturing the same.

[0014]

SUMMARY OF THE INVENTION The present invention is a tunnel junction device in which a first electrode and a second electrode are coupled via a tunnel junction, the device including a first electrode and a second electrode. A high-dielectric-constant insulator portion that increases the junction capacitance of the tunnel junction is arranged between them. According to a second aspect of the present invention, a high dielectric constant insulator portion is provided at a corner of a contact portion between the first electrode and the second electrode.

According to a third aspect of the present invention, the high-dielectric-constant insulator part is flattened by the low-dielectric-constant insulator part.

According to a fourth aspect of the present invention, the high dielectric constant insulator portion is embedded in a substrate on which at least the first electrode and the second electrode are mounted.

According to a fifth aspect of the present invention, after laminating the first electrode and the high dielectric constant insulator on the substrate, the edge thereof is formed into a ramp shape, and the ramp edge surface of the first electrode and the high dielectric constant insulator are formed. A tunnel junction device is manufactured by forming a second electrode in contact with the second electrode and selectively removing the second electrode and the high dielectric constant insulator.

According to the present invention, since the junction capacitance is increased by disposing the high-dielectric-constant insulator in the vicinity of the tunnel junction, connection by wiring is not required, so that the parasitic inductance can be reduced, and The use of high-dielectric constant material also minimizes the increase in area.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION The present invention arranges a high dielectric constant material around a Josephson junction which is a superconducting device,
Equivalently, the capacitance of the Josephson junction is increased to obtain a good under dump characteristic.

A first embodiment of the superconducting device of the present invention will be described.

FIG. 3 is a block diagram of the first embodiment of the present invention, and FIG.
6A to 6D are views for explaining the method for manufacturing the Josephson device according to the first embodiment of the present invention. Further, FIG. 3A is a sectional configuration diagram and FIG. 3B is a perspective view.

The superconducting device 100 of this embodiment is configured to include a substrate 101, a superconducting lower electrode 102, a barrier layer 103, a superconducting upper electrode 104, and a high dielectric constant insulator portion 105.

The substrate 101 is made of LSAT (La-Sr-A).
1-Ta-O) or magnesium oxide (MgO). Superconducting lower electrode 102, the superconducting upper electrode _{104, YBCO (Y-Ba 2 -Cu} 3
-O _7-X ) and other high temperature superconductors. The barrier layer 103 is formed by subjecting the superconducting lower electrode 102 to a surface treatment such as ion irradiation. The high dielectric constant insulator film 105 is formed of STO (Sr—Ti—O ₃ ) or BTO.
It is composed of a high dielectric constant material such as (Ba—Ti—O ₃ ).

The end portion of the superconducting lower electrode 102 is formed in a ramp edge shape, and the barrier layer 1 is formed on the ramp edge.
03 is formed. The superconducting upper electrode 104 is wired along the ramp edge of the superconducting lower electrode 102. Superconducting lower electrode 102, Barrier layer 103, Superconducting upper electrode 10
4 forms a lamp-edge type Josephson junction. The high-dielectric-constant insulating portion 105 is provided in a wedge-shaped portion composed of the superconducting lower electrode 102 and the superconducting upper electrode 104 above the lamp edge type Josephson junction.

According to this embodiment, the superconducting lower electrode 102
Since the high-dielectric-constant insulator portion 105 is provided at a position adjacent to the Josephson junction between the superconducting upper electrode 104 and the superconducting upper electrode 104, a large capacitance is provided in parallel to the Josephson junction. Further, since it is provided very close to the lamp edge type Josephson junction, the parasitic inductance can be suppressed to the minimum, so that the reduction of the junction capacitance due to the parasitic inductance can be prevented.

Next, a method of manufacturing the superconducting device 100 of this embodiment will be described with reference to FIG.

First, on the substrate 101 shown in FIG.
As shown in FIG. 4B, after forming the superconducting lower electrode layer 112 by a film forming method such as laser ablation or sputtering, a high dielectric constant insulator is formed on the upper portion of the superconducting lower electrode layer 112 by a similar film forming method. The layer 113 is formed.
The high dielectric constant insulator layer 113 has, for example, an absolute temperature of 1
A dielectric constant of about 1000 is obtained at 0 ° K.

Next, the superconducting lower electrode layer 112 and the high dielectric constant insulator layer 113 are patterned and etched using a mask material such as photoresist. At this time, the end faces of the superconducting lower electrode layer 112 and the high dielectric constant insulator layer 113 are formed into a ramp edge shape by performing anisotropic etching. As described above, the superconducting lower electrode 102 is formed.

Next, as shown in FIG. 4C, the barrier layer 103 is formed by subjecting the lamp edge surface of the superconducting lower electrode layer 112 to surface treatment such as ion irradiation. Next, as shown in FIG. 4D, the superconducting upper electrode layer 1
14 is formed by a film forming method such as laser ablation or sputtering.

Next, as shown in FIG. 4E, a mask material such as photoresist is further used to remove unnecessary portions of the superconducting upper electrode 105 and the high dielectric constant barrier layer 103 by etching. As described above, the superconducting device 100 as shown in FIG. 3 is formed.

In the superconducting device 100 shown in FIG. 3, a step is formed between the portion where the high dielectric constant barrier layer 103 remains and the portion where it does not remain, which is not desirable in terms of integration. Therefore, flattening may be performed by using a low dielectric constant insulating film.

FIG. 5 is a block diagram of the second embodiment of the present invention, and FIG.
Shows a diagram for explaining a method for manufacturing the Josephson device according to the second embodiment of the present invention. Further, FIG. 5A is a cross-sectional configuration diagram and FIG. 5B is a perspective view. In the figure, the same components as those in FIGS. 3 and 4 are the same. The first embodiment of the superconducting device 200 includes a superconducting lower electrode 102 and a high dielectric constant insulator portion 1.
The step with respect to 05 is flattened by the low dielectric constant insulator portion 201.

In the method of manufacturing the superconducting device 200 of this embodiment, the superconducting lower electrode layer 112 is formed on the substrate 101 shown in FIGS. 6A and 6B by a film forming method such as laser ablation or sputtering. After that, the high dielectric constant insulator layer 113 is formed on the superconducting lower electrode layer 112 by the same film forming method.

Next, as shown in FIG. 6C, the high dielectric constant insulator layer 113 is patterned and etched using a mask material such as photoresist.

Next, as shown in FIG. 6D, a low dielectric constant insulator layer 211 is formed by a film forming method such as laser ablation or sputtering. Next, as shown in FIG. 6E, a portion of the low dielectric constant insulator layer 211 formed so as to project above the high dielectric constant insulator layer 113 is removed by polishing or etching.

Next, as shown in FIG. 6 (E), anisotropic etching is performed to form the end faces of the superconducting lower electrode layer 112 and the high dielectric constant insulator layer 113 in a ramp-edge shape. As described above, the superconducting lower electrode 102 and the high dielectric constant insulator portion 105 are formed.

Next, the ramp edge surface of the superconducting lower electrode layer 112 is subjected to surface treatment such as ion irradiation to form the barrier layer 103. Next, as shown in FIG. 6G, a superconducting upper electrode layer 212 is formed by a film forming method such as laser ablation or sputtering.

Next, as shown in FIG. 6H, a mask material such as photoresist is further used to remove unnecessary portions of the superconducting upper electrode layer 212 and the low dielectric constant insulator layer 211 by etching to remove the superconducting upper electrode. 104 and the low dielectric constant insulator portion 201 are formed. As described above, the superconducting device 100 as shown in FIG. 5 is formed.

In the first and second embodiments, the high dielectric constant insulator portion 103 is provided in the wedge-shaped portion composed of the superconducting lower electrode 102 and the superconducting upper electrode 104. However, the superconducting lower electrode 102 and the superconducting lower electrode 102 are not provided. It may be provided below the upper electrode 104.

Next, an embodiment in which a high dielectric constant insulator is provided below the superconducting lower electrode 102 and the superconducting upper electrode 104 will be described.

FIG. 7 is a block diagram of the third embodiment of the present invention, and FIG.
[FIG. 7] is a view for explaining the manufacturing method of the third embodiment of the present invention. 7A is a cross-sectional view and FIG. 7B is a perspective view. Also, in the figure, the same components as those in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted.

In the superconducting device 300 of this embodiment, a substrate 101 is provided with a superconducting lower electrode 102 and a superconducting upper electrode 104.
And a high-dielectric-constant insulator portion 301 is embedded so as to extend over both of them.

The high-dielectric-constant insulator portion 301 is formed so as to straddle the superconducting lower electrode 102 and the superconducting upper electrode 104, and imparts capacitance in parallel to the Josephson junction.
As a result, the junction capacitance of the Josephson junction can be increased. By increasing the junction capacitance, it is possible to obtain the under dump characteristic.

Next, a method of manufacturing the superconducting device 300 will be described with reference to FIG.

First, a photoresist is applied to the upper portion of the substrate 101 shown in FIG. 8 (A), and light is irradiated to a position other than the position where the high-dielectric-constant insulator portion 301 is to be patterned to perform etching, and then, as shown in FIG. ) As shown in FIG.
11 is formed. Next, a high dielectric constant insulator layer 312 is formed on the entire surface of the substrate 101 by laser ablation or sputtering. Next, using a mask material such as a photoresist in FIG. 8D, patterning is performed by etching so that the high dielectric constant insulator layer 312 remains in the high dielectric constant insulator portion 301. Further, as shown in FIG. 8E, the protruding portion of the high dielectric constant insulating layer 312 is flattened by a method such as polishing or etching.

Next, after forming the superconducting lower electrode layer 112 and the low dielectric constant insulator layer 313 by laser ablation or sputtering, the superconducting lower electrode 112 and the low dielectric constant are masked with a mask material such as photoresist. The rate insulator layer 313 is patterned by anisotropic etching or the like. At this time, a ramp edge is formed as shown in FIG. The barrier layer 103 is formed by subjecting the lamp edge portion of the superconducting lower electrode 112 to surface treatment such as ion irradiation.

Next, a superconducting upper electrode layer is formed and a Josephson junction is formed. Further, a mask material such as a photoresist is used as a mask, and unnecessary portions are removed by etching to form a superconducting upper electrode 104 as shown in FIG.

As described above, the superconducting device 300 as shown in FIG. 7 is formed.

In the third embodiment, the high dielectric constant insulator portion 301 is embedded in the substrate 101. However, the high dielectric constant insulator portion 301 is formed on the substrate 101, and a low dielectric constant insulator layer is formed around the periphery of the substrate 101 to flatten it. Good.

FIG. 9 is a block diagram of the fourth embodiment of the present invention, FIG.
Reference numeral 0 indicates a drawing for explaining the manufacturing method of the fourth embodiment of the present invention. 9A is a sectional view and FIG. 9B is a perspective view. Further, in the figure, the same components as those in FIGS. 7 and 8 are designated by the same reference numerals, and the description thereof will be omitted.

The superconducting device 400 of this embodiment has a structure in which a high dielectric constant insulator portion 401 is formed on a substrate 101 and the periphery thereof is flattened by a low dielectric constant insulator portion 402. The high-dielectric-constant insulator part 401 is the superconducting lower electrode 1
02 and the superconducting upper electrode 104, the capacitance is applied in parallel to the Josephson junction. As a result, the junction capacitance of the Josephson junction can be increased. By increasing the junction capacitance, it is possible to obtain the under dump characteristic.

Next, a method of manufacturing the superconducting device 400 will be described with reference to FIG.

First, a high dielectric constant insulator layer 411 is formed on the substrate 101 shown in FIGS. 10 (A) and 10 (B).
The high dielectric constant insulator layer 411 is formed of STO (Sr-Ti-
O ₃₎ or composed of a high dielectric constant material such as _{BTO (Ba-Ti-O 3} ).

Next, as shown in FIG. 10C, a portion of the high-dielectric-constant insulator layer 411 where the high-dielectric-constant insulator portion 401 is formed is masked with a mask material such as photoresist, and then etched to form a high The high dielectric constant insulator part 401 is formed by removing unnecessary portions of the dielectric constant insulator layer 411. Next, as shown in FIG. 10D, a low dielectric constant insulator layer 412 is formed.
Is formed by laser ablation or sputtering. Further, as shown in FIG. 10E, the protruding portion of the low dielectric constant insulating layer 412 is flattened by a method such as polishing or etching.

Next, after forming the superconducting lower electrode layer 112 and the low dielectric constant insulator layer 313 by laser ablation or sputtering, the necessary portions are masked with a mask material such as photoresist, and the superconducting lower electrode 112 is formed. And the low dielectric constant insulator layer 313 is patterned by anisotropic etching or the like. At this time, a ramp edge is formed as shown in FIG. The barrier layer 103 is formed by subjecting the lamp edge portion of the superconducting lower electrode 112 to surface treatment such as ion irradiation.

Next, a superconducting upper electrode layer is formed and a Josephson junction is formed. Further, masking is performed with a mask material such as photoresist, and unnecessary portions are removed by etching to form superconducting upper electrode 104 as shown in FIG.

As described above, the superconducting device 400 as shown in FIG. 9 is formed.

In the third and fourth embodiments, the high-dielectric-constant insulators 301 and 401 are formed below the superconducting lower electrode 102 and the superconducting upper electrode 103. It may be formed on the upper part of the superconducting upper electrode 102 and the superconducting upper electrode 103.

Next, the high-dielectric-constant insulator portion is connected to the superconducting lower electrode 1
No. 02 and the superconducting upper electrode 103 will be described.

FIG. 11 is a configuration diagram of the fifth embodiment of the present invention, and FIG. 12 is a diagram for explaining a manufacturing method of the fifth embodiment of the present invention. 11A is a cross-sectional view and FIG. 11B is a perspective view. Also, in the figure, the same components as those in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted.

In the superconducting device 500 of this embodiment, the superconducting upper electrode 501 and the superconducting lower electrode 102 are formed in a planar shape, and the superconducting upper electrode 501 and the superconducting lower electrode 102 are formed.
And a high dielectric constant insulator portion 502 is formed so as to extend over both of them.

According to this embodiment, the superconducting lower electrode 102
The superconducting upper electrode 501 is connected to the superconducting upper electrode 501 by the high dielectric constant insulator 502. For this reason, it is equivalent to connecting a capacitor made of the high dielectric constant insulator 502 in parallel with the Josephson junction. Therefore, the junction capacitance can be increased. By increasing the junction capacitance, it is possible to obtain the under dump characteristic.

Next, a method of manufacturing the superconducting device 500 will be described with reference to FIG.

First, as shown in FIG. 12B, the superconducting lower electrode layer 112 is formed on the substrate 101 shown in FIG. 12A.
Is formed by a film forming method such as laser ablation or sputtering, and then a low dielectric constant insulator layer 313 is formed on the upper part of the superconducting lower electrode layer 112 by the same film forming method.

Next, as shown in FIG. 12C, the superconducting lower electrode layer 112 and the low dielectric constant insulating layer 313 are patterned and etched using a mask material such as photoresist. At this time, the end faces of the superconducting lower electrode layer 112 and the low dielectric constant insulator layer 313 are formed into a ramp edge shape by performing anisotropic etching.

Next, the barrier layer 103 is formed by subjecting the lamp edge surface of the superconducting lower electrode layer 112 to a surface treatment such as ion irradiation. Next, as shown in FIG. 12D, the superconducting upper electrode layer 114 is formed by a film forming method such as laser ablation or sputtering.

Next, as shown in FIG. 12E, the low dielectric constant insulator layer 313 and the superconducting upper electrode layer 114, which are projected by polishing, are removed and planarized. Next, the high dielectric constant insulator layer 511 is formed by laser ablation or sputtering. Further, the electrode forming portion is masked by using a mask material such as photoresist, and the unnecessary portion of the high dielectric constant insulator layer 511 is removed by etching. As described above, the superconducting device 500 as shown in FIG. 11 is formed.

The superconducting device 100 shown in FIG. 3 and the superconducting device 400 shown in FIG. 10 may be combined.

FIG. 13 is a block diagram of a sixth embodiment of the present invention, and FIGS. 14 and 15 are views for explaining a method of manufacturing a Josephson device of the sixth embodiment of the present invention. In addition, FIG.
FIG. 13A is a sectional configuration view, and FIG. 13B is a perspective view. 5, those parts that are the same as those corresponding parts in FIGS. 5, 6, 9, and 10 are designated by the same reference numerals, and a description thereof will be omitted.

The superconducting device 600 of this embodiment includes a substrate 101, a superconducting lower electrode 102, a barrier layer 103, a superconducting upper electrode 104, high dielectric constant insulators 105 and 401, and low dielectric constant insulators 201 and 402. It is configured. The high-dielectric-constant insulating portion 105 is provided in a wedge-shaped portion composed of the superconducting lower electrode 102 and the superconducting upper electrode 104 above the lamp edge type Josephson junction.

According to this embodiment, the superconducting lower electrode 102
The high-dielectric-constant insulator portion 105 is provided at a position adjacent to the Josephson junction between the superconducting upper electrode 104 and the superconducting upper electrode 104, and the high-dielectric-constant insulator portion 402 is provided below the Josephson junction.
Therefore, two capacitors are provided in parallel to the Josephson junction. Therefore, the junction capacitance can be increased. The ramp-edge type Josephson junction makes it possible to easily obtain the under dump characteristic.

Next, a method of manufacturing the superconducting device 600 of this embodiment will be described with reference to FIGS.

First, a high dielectric constant insulator layer 411 is formed on the substrate 101 shown in FIGS. 14A and 14B. Next, as shown in FIG. 14C, a portion of the high-dielectric-constant insulator layer 411 where the high-dielectric-constant insulator portion 401 is formed is masked with a mask material such as a photoresist and then etched to obtain a high-dielectric-constant insulating material. The high-dielectric-constant insulator part 401 is formed by removing unnecessary portions of the body layer 411. Next, FIG.
As shown in FIG. 4D, a low dielectric constant insulator layer 412 is formed by laser ablation or sputtering. Further, as shown in FIG. 14E, the protruding portion of the low dielectric constant insulating layer 412 is flattened by a method such as polishing or etching.

Next, as shown in FIG. 14F, after forming the superconducting lower electrode layer 112 by a film forming method such as laser ablation or sputtering, a similar film forming method is formed on the upper portion of the superconducting lower electrode layer 112. Thus, the high dielectric constant insulator layer 113 is formed.

Next, as shown in FIG. 14G, the high dielectric constant insulator layer 113 is patterned and etched using a mask material such as photoresist.

Next, as shown in FIG. 14H, a low dielectric constant insulator layer 211 is formed by a film forming method such as laser ablation or sputtering. Next, as shown in FIG. 15A, the portion of the low dielectric constant insulator layer 211 formed so as to project above the high dielectric constant insulator layer 113 is removed by polishing or etching.

Next, as shown in FIG. 15B, the end faces of the superconducting lower electrode layer 112 and the high dielectric constant insulator layer 113 are formed in a ramp shape by performing anisotropic etching.
As described above, the superconducting lower electrode 102 and the high dielectric constant insulator portion 105 are formed.

Next, the ramp edge surface of the superconducting lower electrode layer 112 is subjected to surface treatment such as ion irradiation to form the barrier layer 103. Next, as shown in FIG. 15C, a superconducting upper electrode layer 212 is formed by a film forming method such as laser ablation or sputtering.

Next, as shown in FIG. 15D, a mask material such as a photoresist is further used to remove unnecessary portions of the superconducting upper electrode layer 212 and the low dielectric constant insulator layer 211 by etching, and the superconducting upper electrode is removed. 104 and the low dielectric constant insulator portion 201 are formed. As described above, the superconducting device 600 as shown in FIG. 13 is formed.

Further, a superconducting ground plane may be provided to increase the junction capacitance.

FIG. 16 is a constitutional view of a seventh embodiment of the present invention, and FIGS. 17 and 18 are views for explaining a method of manufacturing a Josephson device of the seventh embodiment of the present invention. In addition, FIG.
16A is a sectional configuration view, and FIG. 16B is a perspective view. 9, those parts which are the same as those corresponding parts in FIG. 9 are designated by the same reference numerals, and a description thereof will be omitted.

In the superconducting device 700 of this embodiment, a low dielectric constant insulator 701 is provided below the junction, a high dielectric constant insulator 702 is embedded in the upper surface of the low dielectric constant insulator 701, and the substrate 101 is formed. Superconducting ground plane 703
Is provided. The high dielectric constant insulator layer 3
In FIG. 9, the low dielectric constant insulator layer 302 is formed around 01, but in this embodiment, 01 is embedded in the upper portion of the low dielectric constant insulator layer 302.

According to this embodiment, since the junction capacitance can be increased by the superconducting ground plane 701, it is possible to obtain the under dump characteristic.

Next, a method of manufacturing the superconducting device 700 will be described with reference to FIGS.

First, as shown in FIGS. 17A and 17B, a groove 711 is formed in the substrate 101 by etching or the like. Next, as shown in FIG. 17C, the superconducting layer 71
2 is formed by a film forming method such as laser ablation or sputtering. The superconducting layer 712 is YBCO
_{(Y-Ba 2 -Cu 3 -O} 7-X) composed of high-temperature superconductors, such as. Next, the groove portion 711 is masked with a mask material such as photoresist, and etching is performed, so that the superconducting layer 7 is formed in the groove portion 711 as shown in FIG.
12 is formed. Next, as shown in FIG. 17E, the protruding portion of the superconducting layer 712 is flattened by a method such as polishing or etching to form a superconducting plane 712 on the substrate 101.

Next, the low dielectric constant insulator layer 713 is formed as shown in FIG.
As shown in (F), a film is formed by a film forming method such as laser ablation or sputtering. Next, FIG.
As shown in (G), a concave portion 714 is formed by masking the junction forming portion on the upper surface of the low dielectric constant insulator layer 713 and etching. Next, as shown in FIG. 17H, a high dielectric constant insulating layer 715 is formed on the low dielectric constant insulating layer 713 by a film forming method such as laser ablation or sputtering.

Next, the periphery of the recess 714 is masked and etched to form the recess 7 as shown in FIG.
A high dielectric constant insulator layer 715 is embedded in the layer 14. Next, as shown in FIG. 18A, the protruding portion of the high-dielectric-constant insulator layer 715 is flattened by a method such as polishing or etching, so that the low-dielectric-constant insulating portion 701 is a low-dielectric-constant insulating material. A high dielectric constant insulator 702 is embedded on the body layer 713. Next, as shown in FIG. 18B, the superconducting lower electrode 102 and the low dielectric constant insulator portion 402 are formed in a ramp edge shape. Next, as shown in FIG. 18C, the ramp edge portion of the superconducting lower electrode 102 is subjected to surface treatment such as ion irradiation to form a barrier layer 103, and the superconducting upper electrode 1 is formed.
To form 04.

As described above, the superconducting device 700 as shown in FIG. 16 is formed. In the figure, x indicates a Josephson junction.

19 and 20 are circuit configuration diagrams of application examples of the superconducting device.

FIG. 19 shows a circuit for inputting a current to the junctions connected in series and parallel. The driver circuit 800 is
It is configured to include Josephson junctions J1 to J9 and resistors R1 and R2. The Josephson junctions J1 to J9 are switched according to the input current supplied to the input, and the output is controlled.

FIG. 20 shows a circuit for magnetically coupling to the quantum interferometer.

The quantum interferometer 900 is a Josephson junction J
11, J12, J21, J22, J31, J32, J41, J42, inductance L11, L12, L21, L22, L31, L41, L42
It is configured to include. The Josephson junctions J11, J12, J21, J22, J31, J32, J41, J42 are switched according to the input, and the output is controlled.

Superconducting device 1 of the first to seventh embodiments
Nos. 00 to 700 are ramp-edge type Josephson junctions, but since a large junction capacitance can be obtained, an under dump characteristic can be realized. Therefore, FIG. 19 and FIG.
By using the circuit shown in FIG. 0, a large output amplitude can be obtained.

It is also possible to combine the techniques for increasing the capacities used in the superconducting devices 100 to 700 of the first to seventh embodiments.

Further, although the above first to seventh embodiments have been described by taking the high temperature superconducting device as an example, the present invention is not limited to this and can be applied to a normal superconducting device.

Further, the substrate material, the superconducting conductive electrode material, the high dielectric constant insulating material and the low dielectric constant insulating material are not limited to the above. For example, the superconducting electrode material is
It may be an R-Ba-Cu-O-based compound or a La-Ba-Cu-O-based compound.

(Supplementary Note 1) A tunnel junction device in which a first electrode and a second electrode are coupled to each other through a tunnel junction, the device being disposed between the first electrode and the second electrode. A tunnel junction device having a high-dielectric-constant insulator portion for increasing the junction capacitance of the tunnel junction. (Supplementary Note 2) The tunnel junction device according to Supplementary Note 1, wherein the high-dielectric-constant insulator portion is provided at a corner of a contact portion between the first electrode and the second electrode.

(Supplementary Note 3) The tunnel junction device according to Supplementary Note 1 or 2, further comprising a low dielectric constant insulator portion for flattening the high dielectric constant insulator portion.

(Supplementary Note 4) The high dielectric constant insulator portion is formed by being embedded in a substrate on which at least the first electrode and the second electrode are mounted. Tunnel junction device.

(Supplementary Note 5) The tunnel junction according to Supplementary Note 1 or 2, wherein the high dielectric constant insulator portion is formed on a substrate on which at least the first electrode and the second electrode are mounted. device.

(Supplementary Note 6) The tunnel junction device according to Supplementary Note 1, 4 or 5, wherein the high dielectric constant insulator portion is provided on at least upper surfaces of the first electrode and the second electrode. .

(Supplementary Note 7) After laminating the first electrode and the high-dielectric-constant insulator on the substrate, the edge thereof is formed in a ramp shape, and the ramp-edge surface of the first electrode and the high-dielectric-constant insulator are formed. A method of manufacturing a tunnel junction device, wherein a second electrode is formed in contact with, and the second electrode and the high dielectric constant insulator are selectively removed.

(Supplementary Note 8) The first electrode and the high-dielectric-constant insulator are laminated on the substrate, the high-dielectric-constant insulator is patterned, and then the low-dielectric-constant insulator is formed and planarized. And forming a ramp-shaped edge of the high-dielectric-constant insulator, and contacting the first electrode and the high-dielectric-constant insulator to form a second electrode.
Forming an electrode and selectively removing the unnecessary second electrode and the high dielectric constant insulator.

(Supplementary Note 9) By forming a recess in the substrate, laminating a high dielectric constant insulator, and then planarizing the surface,
A method of manufacturing a tunnel junction device, characterized in that a high-dielectric-constant insulator is embedded in the recess, and a ramp-edge-shaped tunnel junction is formed on the high-dielectric-constant insulator.

(Supplementary Note 10) After laminating a high dielectric constant insulator on a substrate and selectively removing the high dielectric constant insulator,
A method of manufacturing a tunnel junction device, characterized in that a low-dielectric-constant insulator is formed and then flattened to form a ramp-edge tunnel junction on the high-dielectric-constant insulator.

(Supplementary Note 11) A first electrode is formed in a ramp edge shape on a substrate, and a second electrode is formed on the first electrode via an interlayer insulating film. A tunnel junction is formed at a ramp edge, and after removing the interlayer insulating film and the second electrode selectively, a high dielectric constant insulator is formed so as to straddle the first and second electrodes and the tunnel junction. A method for manufacturing a tunnel junction device characterized by the above.

(Supplementary Note 12) A high-dielectric-constant insulator is formed and patterned on a substrate, a low-dielectric-constant insulator is formed on the high-dielectric-constant insulator, and then planarized. A method of manufacturing a tunnel junction device, characterized in that a tunnel junction is formed in the substrate.

(Supplementary Note 13) A recess is formed on the surface of the substrate,
13. The tunnel junction device according to any one of appendices 7 to 12, characterized in that the tunnel junction is formed on the substrate in which the ground plane is selectively formed in the recess by laminating the ground plane layers and then flattening the layers. Production method.

[0109]

According to the present invention, since the junction capacitance is increased by disposing the high-dielectric-constant insulator in the vicinity of the tunnel junction, the connection by wiring is not required, and the parasitic inductance can be reduced. In addition, since it uses a high dielectric constant material, it has the advantage of minimizing the increase in area.

[Brief description of drawings]

FIG. 1 is a voltage-current characteristic diagram showing an overdamped characteristic and an underdamped characteristic.

FIG. 2 is a diagram showing a configuration of a conventional under-dump type high temperature superconducting Josephson junction.

FIG. 3 is a configuration diagram of a first embodiment of the present invention.

FIG. 4 is a drawing for explaining the manufacturing method according to the second embodiment of the present invention.

FIG. 5 is a configuration diagram of a second embodiment of the present invention.

FIG. 6 is a drawing for explaining the manufacturing method according to the second embodiment of the present invention.

FIG. 7 is a configuration diagram of a third embodiment of the present invention.

FIG. 8 is a drawing for explaining the manufacturing method according to the third embodiment of the present invention.

FIG. 9 is a configuration diagram of a fourth embodiment of the present invention.

FIG. 10 is a drawing for explaining the manufacturing method according to the fourth embodiment of the present invention.

FIG. 11 is a configuration diagram of a fifth embodiment of the present invention.

FIG. 12 is a drawing for explaining the manufacturing method according to the fifth embodiment of the present invention.

FIG. 13 is a configuration diagram of a sixth embodiment of the present invention.

FIG. 14 is a drawing for explaining the manufacturing method of the Josephson device according to the sixth embodiment of the present invention.

FIG. 15 is a drawing for explaining the manufacturing method of the Josephson device according to the sixth embodiment of the present invention.

FIG. 16 is a configuration diagram of a seventh embodiment of the present invention.

FIG. 17 is a drawing for explaining the manufacturing method of the Josephson device according to the seventh embodiment of the present invention.

FIG. 18 is a drawing for explaining the manufacturing method of the Josephson device according to the seventh embodiment of the present invention.

FIG. 19 is a circuit configuration diagram of an application example of a superconducting device.

FIG. 20 is a circuit configuration diagram of an application example of a superconducting device.

[Explanation of symbols]

100, 200, 300, 400, 500, 600, 7
00 superconducting device 101 substrate 102 superconducting lower electrode 103 insulating film 104, 501 superconducting upper electrode 105, 301, 401, 502, 702 high dielectric constant insulators 201, 302, 402 low dielectric constant insulator 703 superconducting ground plane

Continued front page    F-term (reference) 4M113 AA06 AA16 AA25 AA37 AD04                       AD18 AD36 AD37 AD42 AD68                       BA04 BB07 BC08 BC22 CA33                       CA34

Claims (5)

[Claims] 1. A tunnel junction device in which a first electrode and a second electrode are coupled via a tunnel junction, the device being disposed between the first electrode and the second electrode,
A tunnel junction device comprising a high-dielectric-constant insulator portion that increases the junction capacitance of the tunnel junction. 2. The tunnel junction device according to claim 1, wherein the high dielectric constant insulator is provided at a corner of a contact portion between the first electrode and the second electrode. 3. A low dielectric constant insulator part for flattening the high dielectric constant insulator part.
The tunnel junction device described. 4. The tunnel according to claim 1, wherein the high-dielectric-constant insulator part is formed by being embedded in a substrate on which at least the first electrode and the second electrode are mounted. Joining device. 5. A first electrode and a high-dielectric-constant insulator are laminated on a substrate, and then the edge is formed into a ramp shape, and the ramp-edge surface of the first electrode and the high-dielectric-constant insulator are contacted. Forming a second electrode by selectively removing the second electrode and the high dielectric constant insulator.