JP2003115592A - Semiconductor device and manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device having an element separation structure for reducing a leak current in an MOSFET formed on an SOI substrate. SOLUTION: After an oxide film 14 is formed on an SOI semiconductor substrate, the oxide film 14 and a silicon film 13 are etched to form an element separation groove 21 [(c)]. After the element separation groove 21 is filled with an STI-embedded nitride film 15, the upper edge of the oxide film 14 and the STI buried nitride film 15 is planarized [(e)]. The oxide film 14 is removed by wet-etching [(f)]. After a gate oxide film is formed by heat treatment, a first gate material is deposited, and the upper edge part of the STI- embedded nitride film 15 and the first gate material is flattened. Then, a second gate material is deposited, and a patterning step is carried out to form a gate electrode, and after that, a source/drain region is formed.

Description

Detailed Description of the Invention

[0001]

The present invention relates to an SOI (Silicon) having a semiconductor layer formed on a semiconductor substrate via an insulating layer.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device using a con On Insulator (substrate) substrate and a method for manufacturing the same, and particularly to a MOSFET (Metal Oxide Semiconductor Fi
The present invention relates to a semiconductor device having an eld effect transistor and its manufacturing method.

[0002]

2. Description of the Related Art An SOI substrate having a silicon thin film on a semiconductor supporting substrate via an insulating layer is used as a MOSFET (hereinafter referred to as S
(Abbreviated as OI-MOSFET), an insulating film is formed under the source region and the drain region, so that the parasitic capacitance related to the source / drain region can be made smaller than that of a normal bulk substrate. Become. Therefore, it is advantageous in increasing the speed of the device, and therefore, research and development are currently being actively pursued. When using this SOI substrate,
Since the lower layers of the elements are formed of an insulating film, when the elements are separated by a trench isolation technique such as STI (Shallow Trench Isolation), the elements can be completely electrically insulated. . Conventionally, this kind of ST
Method I is used to form a fine semiconductor element isolation structure.

A few conventional SOI-MOSFETs will be described below. 13 (a) to 14
(H) is a process order sectional view of a first conventional example to which the STI method is applied. Semiconductor support substrate 51, buried oxide film 5
2 and a silicon oxide film 54 and a silicon nitride film 5 on an SOI semiconductor substrate [FIG. 13A] composed of a silicon thin film 53 having a thickness of 100 nm or more.
5 is formed using a chemical vapor deposition (hereinafter, CVD) method [FIG. 13 (b)]. Next, the silicon nitride film 5 excluding the portion corresponding to the element region
5, the silicon oxide film 54 and the silicon thin film 53 are removed by etching to form an element isolation groove 59 [FIG.
(C)]. After that, an STI-buried oxide film 56 filling the element isolation trench 59 is deposited [FIG. 13 (d)], and then chemical mechanical polishing (hereinafter, referred to as C).
MP) method is used to polish the STI buried oxide film 56 to expose the silicon nitride film 55 on the surface. At this time, the silicon nitride film 55 having a lower polishing rate than the STI buried oxide film 56 acts as a stopper to form a flattened surface [FIG. 14 (e)]. Next, the silicon nitride film 55 is removed by hot phosphoric acid, and then the silicon oxide film 54 is removed by hydrofluoric acid [FIG. 14 (f)]. Next, a gate oxide film 57 is formed, and a gate material 58 to be a gate electrode is deposited [FIG. 14 (g)]. After that, the gate material 58 is patterned to form the gate electrode 58.
After a is formed [FIG. 14 (h)], and the steps of forming the source / drain regions and the like, the manufacturing process of the SOI-MOSFET is completed.

FIG. 15 is a sectional view of an SOI-MOSFET (hereinafter, referred to as a second conventional example) disclosed in Japanese Patent Laid-Open No. 8-213494. This conventional example relates to an element isolation structure having a so-called MESA type isolation shape in which an insulating film formed higher than an upper surface of a silicon thin film is formed on a sidewall portion of a silicon thin film 53 on an SOI semiconductor substrate forming a MOSFET. A buried oxide film 52 is formed on a semiconductor supporting substrate 51, and a silicon thin film 53 having a film thickness of about 100 nm is further formed. Further, a silicon nitride film 60 having a film thickness of 20 nm is formed on the side wall of the silicon thin film 53. Further, on the side wall portion of the silicon nitride film 60, the silicon oxide film 61 protruding above the silicon thin film 53 is formed.
Are formed. On the other hand, a gate oxide film 57 and a gate material 58 are formed on the silicon thin film 53. As described above, since the side wall of the silicon thin film 53 is covered with the silicon nitride film 60, there is an advantage that it is possible to prevent the generation of leak current and the occurrence of dielectric breakdown at the upper end of the silicon thin film 53. ing.

Next, regarding the manufacturing method of the third conventional example,
This will be described with reference to the process sequence cross-sectional views of FIGS. 16A to 17J. This conventional example is a method of manufacturing a semiconductor device using a damascene gate process in which a gate material is embedded in a gate formation region after an opening is formed in the gate formation. Semiconductor support substrate 51, buried oxide film 52, silicon thin film 53 having a thickness of 100 nm or more
An SOI semiconductor substrate composed of
(A)], a silicon oxide film 54 and a silicon nitride film 55 are sequentially deposited [FIG. 16 (b)]. Next, except the portion corresponding to the element region, the silicon nitride film 55, the silicon oxide film 54, and the silicon thin film 53 are selectively etched to form an element isolation groove 59 [FIG.
(C)]. After that, an STI buried oxide film 56 is deposited on the entire surface to fill the element isolation trench 59 [FIG.
(D)], the STI buried oxide film 5 is formed by the CMP method.
6 is polished until the silicon nitride film 55 is exposed on the surface [FIG. 16 (e)]. At this time, the STI buried oxide film 5
The silicon nitride film 55 having a polishing rate lower than that of 6 acts as a stopper in the polishing process, and a structure in which the upper end portion is flattened is formed.

Then, the silicon nitride film 55 and the silicon oxide film 54 on the silicon thin film 53 are removed by using hot phosphoric acid, hydrofluoric acid or the like [FIG. 17 (f)]. Next, after thermally oxidizing the surface of the silicon thin film 53 to form a dummy gate oxide film 67, for example, a silicon nitride film or a polycrystalline silicon film is deposited and then patterned to form a dummy gate 68 [FIG. 17 (g)]. And
Source / drain regions are formed. Next, after depositing a planarizing oxide film 70, a dummy gate 68 is formed by a CMP method.
Until it is exposed and the upper end is flattened [Fig. 1
7 (h)]. Next, as shown in FIG. 17I, the dummy gate 68 and the dummy gate oxide film 67 are removed.
In this process, the dummy gate oxide film 6 is formed by hydrofluoric acid.
When performing wet etching of No. 7, the STI buried oxide film 56 is also side-etched at the same time. Subsequently, a gate oxide film 57 is formed on the surface of the silicon thin film 53 by thermal oxidation or the like, and a gate electrode 58a is embedded in a region where the dummy gate 68 is removed [FIG. 17 (j)], and SOI.
Forming a MOSFET.

[0007]

One of the problems of the prior art is that when the thickness of the silicon thin film becomes thin, the electrical characteristics of the thin film SOI transistor formed by the STI method or the damascene gate process method cause the sub-threshold. That is, the leak current in the drain region becomes large. As a result, it has been difficult to manufacture a thin film SOI transistor device aiming at lower voltage and higher speed operation. The reason will be described below.

In the first and third conventional examples, the silicon nitride film 55 is continuously heated with hot phosphoric acid and then the silicon oxide film 54 is removed.
Is removed by etching with hydrofluoric acid, but at this time, a part of the STI buried oxide film 56 covering the side surface of the silicon thin film 53 is also removed [FIG. 14 (f), FIG. 17].
(F)]. In the third conventional example, when the dummy gate oxide film 67 is subsequently removed by etching with hydrofluoric acid, the STI
Part of the buried oxide film 56 is removed [FIG.
(I)]. As described above, the STI buried oxide film 56 is subjected to the hydrofluoric acid treatment one or more times, so that immediately before the gate oxide film 57 is formed, the upper end portion of the STI buried oxide film 56 filling the isolation trench is the element region. Lower than the surface height.

At this time, particularly when the thickness of the silicon thin film 53 is made thinner than 100 nm, the buried oxide film 52 under the silicon thin film 53 is exposed and the lower end of the silicon thin film 53 is exposed. There was a possibility. Even if the buried oxide film 52 is not exposed, if the gate oxide film 57 and the gate material 58 are formed in a later step, the height of the element isolation region is partially lowered from the element region surface. When the gate electrode 58a is formed, an abnormal shape 62 in which the gate electrode wraps around the element end region occurs [FIG. 14 (h), FIG. 17 (j)].

When such an abnormal shape 62 occurs, a gate electric field is concentrated on the abnormal shape 62 during operation of the transistor, so that a parasitic transistor is formed in the silicon thin film 53 near the abnormal shape. Therefore, in the sub-threshold region where the gate voltage is low, the drain current characteristic rises and the hump characteristic is observed.
When an abnormal voltage characteristic occurs or the gate width of a transistor is shortened, there arises a problem that an inverse narrow channel effect in which a threshold value of an element is lowered appears. In particular, the hump characteristic of the drain current means an increase in the leak current of the device. Further, when the gate length of the device is reduced for the purpose of improving the circuit characteristics, in the case of the SOI transistor, it is necessary to reduce the silicon film thickness by the same ratio. , The leak current will increase further.

In the second conventional example having the MESA type insulating film on the side surface of the silicon thin film, the side wall portions of the silicon thin film 53 and the gate oxide film 57 are covered with the nitride film (FIG. 15). ), The problem of abnormal shape described above does not occur. However, in the second conventional example, a large step is formed around the silicon thin film 53. Therefore, in the step of forming the gate wiring, overetching for the step may be required, or a process defect such that the gate wiring material is likely to remain in the step portion may occur. In particular, the rest of the gate wiring material is between the gate electrodes or between the gate electrode and the source.
It also causes an electrical short circuit between the drain regions. In addition, the film thickness of the gate material is likely to be thin at the protrusion of the silicon oxide film 61, and the possibility of disconnection increases. An object of the present invention is to solve the above-mentioned problems of the prior art, and firstly, the parasitic transistor is not formed even in a semiconductor device including a thin SOI transistor having a silicon film of 100 nm or less. Moreover, it is to provide an element isolation structure and a manufacturing method thereof capable of suppressing a leak current. Secondly, it is possible to eliminate the need for over-etching at the time of patterning a gate material and to short-circuit the gate electrode / wiring. / To prevent disconnection.

[0012]

In order to achieve the above object, according to the present invention, an island-shaped silicon thin film separated by an element isolation groove filled with a buried insulating film is formed on an insulating film, In a semiconductor device in which a gate electrode is formed on the silicon thin film via a gate insulating film, the surface of the embedded insulating film is flat and its height is substantially equal to the surface height of the gate electrode, and the embedded Provided is a semiconductor device, wherein the insulating film is formed of a material having a high resistance to an oxide film etching material.
The film made of a material having a high resistance to the oxide film etching material may be formed only on a side surface portion of the buried insulating film. And, preferably, a silicon oxide film is formed at a contact portion between the silicon thin film and the buried insulating film. Further, preferably, the material having high resistance to the etching agent for oxide film is silicon nitride.

Further, in order to achieve the above object, according to the present invention, MOSFETs isolated by an element isolation groove filled with a buried insulating film on an SOI substrate having a semiconductor supporting substrate, a buried oxide film and a silicon thin film. In the method for manufacturing a semiconductor device having: (1) a step of forming a thick film material layer on the silicon thin film; and (2) selectively etching the thick film material layer and the silicon thin film to form an element isolation groove. Forming step, (3) burying the element isolation trench with an insulating material having high resistance to the oxide film etching material, and (4) flattening a film of an insulating material burying the element isolation trench. A method of manufacturing a semiconductor device, comprising:

In order to achieve the above object, according to the present invention, MOSFETs isolated by an element isolation groove filled with a buried insulating film on an SOI substrate having a semiconductor supporting substrate, a buried oxide film and a silicon thin film. In the method for manufacturing a semiconductor device having: (1) a step of forming a gate insulating film and a gate electrode forming material layer on the silicon thin film; and (2) the gate electrode forming material layer thick film material layer, the gate insulating film. Forming a device isolation groove by selectively etching the film and the silicon thin film;
(3) A step of forming a side surface spacer on a side surface of the element isolation groove with an insulating material having high resistance to an oxide film etching material, and (4) a step of burying the element isolation groove with a burying insulating material. And (5) a step of flattening the film of the insulating insulating material for burying the element isolation trench, the method for manufacturing a semiconductor device is provided. Further, to achieve the above object, according to the present invention, a semiconductor having a MOSFET separated by an element isolation groove filled with a buried insulating film on an SOI substrate having a semiconductor supporting substrate, a buried oxide film and a silicon thin film. In the method of manufacturing a device, (1) a step of forming a gate insulating film and a gate electrode forming material layer on the silicon thin film; (2) the gate electrode forming material layer thick film material layer;
A step of selectively etching the gate insulating film and the silicon thin film to form an element isolation groove, and (3) an insulating material having a high resistance to an oxide film etching material is smaller than the depth of the element isolation groove. A step of depositing a film having a thickness to form an etching resistant film; (4) a step of burying the element isolation groove with a burying insulating material; and (5) a burying insulating material burying the element isolation groove. And a step of exposing the surface of the gate electrode forming material layer by subjecting the film and the etching resistant film to a planarization process, and a method of manufacturing a semiconductor device.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. (Embodiment 1) FIGS. 1A to 2K are cross-sectional views in order of the steps, showing a manufacturing method in Embodiment 1 of the present invention. As shown in FIG. 1A, the SOI semiconductor substrate is composed of a semiconductor support substrate 11, a buried oxide film 12 and a silicon thin film 13. At this time, the thickness of the silicon thin film 13 is preferably 100 nm to 200 nm,
Even if it is 100 nm or less, it can be sufficiently used. First, the silicon oxide film 14 is formed on the silicon thin film 13 by 50
Deposit to a thickness of 200 nm to 200 nm [Fig. 1
(B)]. Next, a portion of the surface of the silicon oxide film 14 that is to be an element forming region is protected by using a mask such as a resist, and the silicon oxide film 14 and the silicon thin film 13 are etched to form an element isolation groove 21. [(FIG. 1 (c)]] Next, the STI embedded nitride film 15 is formed.
Is deposited so as to be thicker than the step between the silicon oxide film 14 and the silicon thin film 13, and the element isolation trench 21 is buried [FIG. 1 (d)].

Next, after polishing a predetermined amount of the STI buried nitride film 15 by the CMP method, ST is formed by the plasma etching method until the silicon oxide film 14 is exposed on the surface.
The I-buried nitride film 15 is etched to form a structure in which the upper end portion is flattened [FIG. 1 (e)]. Although the steps using the CMP method and the plasma etching method have been described here, the present invention is not limited to this, and any method that can flatten the surface may be used, for example, only the CMP method. Then, the silicon oxide film 14 on the silicon thin film 13 is removed by hydrofluoric acid [FIG. 1 (f)]. Next, a gate oxide film 17 is formed on the silicon thin film 13, and a first gate material 18 to be a gate electrode is deposited [FIG.
(G)]. Here, the material of the gate oxide film 17 is not limited to the oxide film, and may be another material such as a nitrided oxynitride film (the same applies to other embodiments). A polycrystalline silicon film or the like can be used as the first gate material 18. After that, CM
By the P method, the first gate material 18 on the STI buried nitride film 15 is polished to planarize the upper end portion [FIG.
(H)]. After that, the second gate material 19 is formed by the CVD method so as to have a film thickness of, for example, 50 nm to 200 nm [FIG. 2 (i)]. Subsequently, the first and second gate materials 18 and 19 are patterned to form a gate electrode 18a and a gate wiring 19a, and a source / drain region 20 is formed [FIGS. 2 (j) and (k)]. 2 (j) is a sectional view taken along the gate length direction.
(K) is a cross-sectional view in the gate width direction.

Here, in FIG. 2G, the method of polishing the first gate material 18 by the CMP method has been described, but the present invention is not limited to this. For example, it is possible to form the gate electrode after processing the first gate material 18 without flattening it. In this case, the second gate material 19 need not be used. In this method, the side wall of the silicon thin film 13 is covered with the STI buried nitride film 15 having high etching resistance. Therefore, in the step of removing the silicon oxide film 14 by etching with hydrofluoric acid or the like [FIG.
(F)], the side wall of the silicon thin film 13 is not exposed. Therefore, the abnormal shape that occurs in the conventional example does not occur, and as a result, stable transistor operation without increase in leak current becomes possible. Also, the second
Since the gate material 19 is formed on a flat surface, short-circuiting does not occur due to generation of etching residue, and disconnection does not occur due to thin film thickness.

(Embodiment 2) Next, a manufacturing method according to Embodiment 2 of the present invention will be described with reference to sectional views in order of steps of FIGS. 3 (a) to 4 (j). Semiconductor support substrate 11
An SOI semiconductor substrate having the buried oxide film 12 and the silicon thin film 13 formed thereon is prepared as in the first embodiment [FIG. 3 (a)]. First, a gate oxide film 1 is formed on this substrate.
7, first gate material 18, followed by silicon oxide film 14
Are sequentially deposited [FIG. 3 (b)]. The film thickness at this time is about 2 nm for the gate oxide film 17, 20 to 100 nm for the first gate material 18, and 50 nm for the silicon oxide film 14.
To 200 nm is desirable. Moreover, polycrystalline silicon can be used for the first gate material 18. Next, the silicon oxide film 14, the first gate material 18, the gate oxide film 17, and the silicon thin film 13 are left only in the portion corresponding to the element region, and etching processing is performed on the portion other than that portion to form the element isolation groove 21. It is formed [Fig. 3 (c)]. Next, the silicon oxide film 14, the first
The element isolation trench 21 is buried by depositing the STI buried nitride film 15 so as to be thicker than the steps of the gate material 18, the gate oxide film 17, and the silicon thin film 13 of FIG. After that, a predetermined amount of the STI embedded nitride film 15 is polished by the CMP method, and then the STI embedded nitride film 15 is etched by the plasma etching method until the silicon oxide film 14 is exposed on the surface to planarize the upper end portion [ FIG. 3 (e)]. Although the steps of performing the planarization by the CMP method and the plasma etching method are shown here, the present invention is not limited to this, and any method can be used as long as it can be planarized, for example, only the CMP method. There is no problem even if processed. continue,
The silicon oxide film 14 on the first gate material 18 is removed using hydrofluoric acid [FIG. 4 (f)].

Next, a second gate material 19 to be a gate electrode is deposited so as to have a thickness of preferably 50 nm to 200 nm to form the structure shown in FIG. Gate material 18 is not shown). The second
For the gate material 19 of, for example, polycrystalline silicon can be used. Then, the second gate material 19 on the STI buried nitride film 15 is polished by CMP,
The upper end is flattened [FIG. 4 (h)]. Next, CVD
The third gate material 30 is, for example, 50 nm to 20 nm
It is formed so as to have a film thickness of 0 nm [FIG.
Second and first gate materials 30, 19 and 18 (1
8 is not shown in the drawing) to perform gate electrode 19
b, the gate wiring 30a is formed, and the source / drain regions 20 are formed [FIG. 4 (j)]. Embodiment 2 of the present invention
Then, as in the first embodiment, since the sidewall portion of the silicon thin film 13 is configured to be protected by the STI buried nitride film 15, the hydrofluoric acid treatment does not cause an abnormal shape. In addition, the upper end surface of the silicon thin film 13 is
The gate oxide film 17 formed before the element isolation step and the first gate material 18 are covered [FIG.
(B)]. As a result, when the silicon oxide film 14 is wet-etched with hydrofluoric acid in a later step [FIG.
(F)], the surface of the silicon thin film 13 is prevented from being damaged. This has the advantage of enabling the production of high mobility surface channel devices. Even if the silicon oxide film 14 is removed by dry etching, the same effect can be obtained.

(Third Embodiment) Next, a manufacturing method according to a third embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to the step-by-step sectional view of (j). First, on the SOI semiconductor substrate [FIG. 5 (a)] including the semiconductor support substrate 11, the buried oxide film 12, and the silicon thin film 13,
After forming the gate oxide film 17 and the first gate material 18 made of, for example, a polycrystalline silicon film, the silicon oxide film 14 is deposited [FIG. 5 (b)]. The gate oxide film 17 has a thickness of about 2 nm, the first gate material 18 has a thickness of 50 nm to 200 nm, and the silicon oxide film 14 has a thickness of 50 nm.
To 200 nm is desirable. Next, the silicon oxide film 14, the first gate material 18, the gate oxide film 17, and the silicon thin film 13 except the portion corresponding to the element region are removed by etching to form an element isolation groove 21 [FIG.
(C)]. Next, a buffer oxide film 2 having a thickness of preferably 5 nm to 50 nm is formed on the side surface of the silicon thin film 13 by a thermal oxidation method.
After forming 3, the STI buried nitride film 15 is deposited [FIG. 5 (d)]. In this step, when a polycrystalline silicon film is used as the first gate material 18, the side wall portion of the first gate material 18 is also the silicon thin film 1.
Oxidation is performed in the same manner as the side wall portion 3 to form an oxide film (not shown). Then, a certain amount of S is obtained by the CMP method.
After polishing the TI buried nitride film 15, the STI buried nitride film 15 is etched by plasma etching until the silicon oxide film 14 is exposed on the surface to form a structure in which the upper end portion is flattened [FIG. e)]. In addition,
Here, the steps of processing by the CMP method and the plasma etching method have been described, but the present invention is not limited to this, and the CMP method alone may be used as long as planarization is possible. Then, using hydrofluoric acid,
The silicon oxide film 14 on the gate material 18 is removed [FIG. 6 (f)]. In this hydrofluoric acid treatment, when polycrystalline silicon is used as the first gate material 18,
Of the oxide film (not shown) formed on the side wall of the gate material 18 of the first gate material 18 may be removed, and the gate oxide film 17 under the first gate material 18 and even the buffer oxide film 23 may be damaged. There is. Therefore, it is necessary to sufficiently control the etching conditions so that overetching does not occur. Further, setting the film thickness of the first gate material 18 to a sufficient thickness in advance is also one method. This is because even if the oxide film formed on the side wall portion of polycrystalline silicon is etched, it is possible to control so that the buffer oxide film 23 on the side wall portion of the silicon thin film 13 is not damaged.

Next, a second gate material 19 to be a gate electrode, for example, a polycrystalline silicon film is formed preferably from 50 nm.
It is deposited to a thickness of 200 nm [FIG. 6 (g)] (note that the first gate material 18 is not shown here). afterwards,
The second gate material 19 on the STI buried nitride film 15 is polished by the CMP method to flatten the upper end portion as shown in FIG. After this, by the CVD method, the third
The gate material 30 is formed to have a film thickness of, for example, 50 nm to 200 nm [FIG. 6 (i)]. Next, the gate materials 30, 19 and 18 (18 is not shown) are patterned to form a gate electrode 19b and a gate wiring 30a, and a source / drain region 20 is formed [FIG. 6].
(J)]. Also in this method, similar to the first embodiment, the method described with reference to FIGS.
It is possible to omit the planarization step of CMP of the second gate material 19. (At this time, the third gate material is not necessary.) Since the third embodiment of the present invention is substantially the same as the second embodiment, it exhibits the same effect as the second embodiment. The difference is that the buffer oxide film 23 is formed before depositing the STI buried nitride film 15. Therefore, in addition to the effects of the second embodiment, the following effects are obtained. That is, the buffer oxide film 23 is the STI buried nitride film 15 and the silicon thin film 13.
Since it exists on the boundary surface of the STI buried nitride film 15, the stress of the silicon thin film 13 generated by the STI embedded nitride film 15 can be relieved. As a result, it is possible to suppress the leakage current due to the stress generated at the end of the element region.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to sectional views in order of steps of FIGS. 7A to 8I. First, SO having a semiconductor support substrate 11, a buried oxide film 12 and a silicon thin film 13
The gate oxide film 17 is formed on the I semiconductor substrate [FIG. 7 (a)].
Then, a first gate material 18 of, for example, a polycrystalline silicon film having a film thickness of preferably 50 nm to 200 nm is deposited [FIG. 7 (b)]. Next, the first gate material 1
8, the gate oxide film 17 and the silicon thin film 13 are removed by etching except the portion corresponding to the element region to form the element isolation groove 21 [FIG. 7 (c)]. Then, the silicon nitride film 16 is deposited by a CVD method, preferably from 100 nm to 2 nm.
After being deposited to a film thickness of 00 nm [FIG. 7 (d)], the spacer nitride film 16a is formed by etching by anisotropic plasma etching [FIG. 7 (e)]. After this,
An STI buried oxide film 22 is buried in the element isolation trench 21 [FIG. 8 (f)], and then polishing is performed by CMP until the first gate material 18 appears on the surface to planarize the upper end portion [FIG. 8]. (G)]. In this polishing step, the spacer nitride film 16a acts as a polishing stopper to polish the STI buried oxide film 22.

Next, the second gate material 19 is formed by CVD, for example, to a film thickness of 50 nm to 200 nm [FIG. 8 (h)]. Subsequently, the second gate material 19 and the first
Patterning of the gate material 18 of the gate electrode 1
8a and the gate wiring 19a are formed, and the source / drain regions 20 are formed [FIG. 8 (i)]. This method is
This embodiment differs from the previous embodiments in that silicon oxide is used as the filling material for I. Silicon oxide is C
The MP method has an advantage of excellent workability. Further, this method has a configuration in which the sidewall portion of the silicon thin film 13 is protected by the spacer nitride film 16a. Therefore, the abnormal shape due to hydrofluoric acid or the like as seen in the first conventional example and the third conventional example does not occur.
Further, the present embodiment has a structure similar to the MESA type isolation shape shown in the second conventional example in that it has a spacer nitride film 16a beside the silicon thin film and an oxide film beside it. . However, since the first gate material 18 and the STI buried oxide film 22 are planarized during the process [FIG. 8 (g)], it is not necessary to overetch the gate material as in the conventional example. In addition, since no etching residue remains when the gate electrode is formed, no electrical short circuit occurs. Also in the present embodiment, after the element region is formed in an island shape as in the third embodiment [FIG. 7C], heat treatment is performed to perform the silicon thin film 1
A buffer oxide film may be formed on the side surface such as 3.

(Embodiment 5) FIGS. 9A to 10
(J) is a process order cross-sectional view of the manufacturing method in the fifth embodiment of the present invention. First, a dummy gate oxide film 31 having a thickness of about 10 nm is formed on an SOI semiconductor substrate [FIG. 9A] having a semiconductor supporting substrate 11, a buried oxide film 12 and a silicon thin film 13, and then, for example, polycrystalline silicon. A dummy gate material 32 having a film thickness of about 100 nm is formed [FIG. 9 (b)]. After that, leaving a portion corresponding to the element region, the dummy gate material 32, the dummy gate oxide film 31, and the silicon thin film 13 in the other regions are selectively removed by etching to form the element isolation trench 21 [FIG.
(C)]. Next, the STI buried nitride film 15 is deposited to a thickness of preferably 200 nm to 500 nm [FIG. 9 (d)]. Next, the buried nitride film 15 is flattened by the CMP method, and a dummy gate polycrystalline silicon film 33 is formed to have a film thickness of preferably 50 nm to 200 nm [FIG.
(E)]. Subsequently, the dummy gate polycrystalline silicon film 33
Then, the dummy gate material 32 is selectively etched into the shape of the gate wiring / gate electrode [FIG. 10 (f)]. After that, a source / drain region (not shown) is formed by an ion implantation method, and then a planarizing oxide film 34 is deposited by a CVD method so as to have a film thickness of preferably 200 nm to 500 nm, and then an upper end by a CMP method. The part is flattened [Fig. 10
(G)].

Next, the dummy gate polycrystalline silicon film 33 and the dummy gate material 3 which have been processed into the gate shape.
2 is removed by a plasma etching method, and the exposed dummy gate oxide film 31 is removed by selectively etching it with hydrofluoric acid [FIG. 10 (h)]. Next, the silicon thin film 1
A gate oxide film 17 having a thickness of about 2 nm is formed on the surface of No. 3 by, for example, a thermal oxidation method, and then a gate material 18 is deposited [FIG. 10 (i)]. Next, the CMP method is used to planarize the upper end portion of the gate material 18 to form the gate electrode 18a and the gate wiring 18b [FIG. 10].
(J)]. In this manufacturing method, the dummy gate oxide film 31
Since the sidewall portion of the STI buried nitride film 15 is covered [FIG. 9 (d) and others], the dummy gate oxide film 31 is also removed by hydrofluoric acid [FIG. 10 (h)]. The nitride film 15 is not etched by hydrofluoric acid. That is, it has the same effect as that of the first embodiment. Here, as the gate material 18, not only polycrystalline silicon but also a metal-based material can be used. At this time, if a metal-based material such as TiN is used,
Since the work function of the gate material can be changed,
The advantage is that the threshold voltage can be controlled. As described above, the present invention can be applied to a so-called damascene gate process in which a gate electrode is embedded and formed.

(Sixth Embodiment) Next, a sixth embodiment of the present invention will be described with reference to sectional views in order of steps of FIGS. 11A to 12I. First, the semiconductor support substrate 1
1. On a SOI semiconductor substrate [FIG. 11 (a)] having a buried oxide film 12 and a silicon thin film 13, a gate oxide film 17 and, for example, a polycrystalline silicon film having a film thickness of preferably 50 nm to 200 nm are formed. The first gate material 18 is formed [FIG. 11 (b)]. Next, the first gate material 18, the gate oxide film 17 and the silicon thin film 13 except for the portion corresponding to the element region are removed by etching to form an element isolation groove 21 [FIG. 11 (c)]. Then, the silicon nitride film 16 is preferably deposited to 100 nm to 200 nm by the CVD method.
CV after being deposited to have a film thickness of [Fig. 11 (d)].
Using the D method, the STI buried oxide film 22 is grown to fill the element isolation trench 21 [FIG. 11 (e)]. Next, using the silicon nitride film 16 as a stopper, the upper end portion is flattened by the CMP method [FIG. 12 (f)]. Then, the silicon nitride film 1 is formed using an anisotropic plasma etching method.
6 is etched to expose the first gate material 18 [FIG. 12 (g)]. At this time, the silicon nitride film 16 is processed into a spacer nitride film 16b whose upper end portion is removed and which covers the side wall portion of the silicon thin film 13.

Next, the second gate material 1 is formed by the CVD method.
9 is formed to have a film thickness of, for example, 50 nm to 200 nm [FIG. 12 (h)]. Then, the second gate material 19
Then, the first gate material 18 is patterned to form the gate electrode 18a and the gate wiring 19a, and the source / drain regions 20 are formed [FIG. 12 (i)]. This method has an advantage that an oxide film having excellent workability in the CMP method can be used as an STI filling material. In addition to this, since the silicon nitride film 22 can be used as a stopper in this CMP process, the surface of the first gate material 18 is not exposed to CMP. Furthermore, the fourth embodiment
Similarly to the first gate material 18 and the buried oxide film 22.
Since and are flattened, it is not necessary to perform overetching, and no etching residue remains. Note that, also in this embodiment, after the element region is formed in an island shape as in the third embodiment [FIG. 11 (c)], heat treatment is performed to form a buffer oxide film on the side surface of the silicon thin film 13 or the like. May be.

[0028]

According to the method of manufacturing a semiconductor device of the present invention, the STI structure is adopted in which the side wall portion of the silicon thin film which becomes the end of the element region is covered with the nitride film. Therefore, SOI-
In the process of forming the MOSFET, when the oxide film is etched with hydrofluoric acid or the like, the insulating film covering the sidewall portion of the silicon thin film is not etched and the sidewall portion of the silicon thin film is not exposed. It is possible to prevent the formation of leak current and suppress the generation of leak current. As a result, even if the thickness of the silicon thin film is 100 nm or less, it has excellent characteristics.
It becomes possible to form T. Further, since the surface height of the insulating film filling the element isolation trench is almost equal to the surface height of the gate electrode and the surface is flat, there is no need to perform overetching when etching the gate material on the element isolation insulating film. Further, stable gate formation can be achieved by suppressing electrical short circuits and disconnections.

[Brief description of drawings]

1A to 1C are cross-sectional views in order of the steps, showing a manufacturing method in a first embodiment of the present invention (No. 1).

FIG. 2 is a sectional view in order of the steps (No. 2) showing the manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a sectional view in order of steps (No. 1) showing the manufacturing method according to the second embodiment of the present invention.

FIG. 4 is a sectional view in order of the steps (No. 2) showing the manufacturing method according to the second embodiment of the present invention.

5A to 5C are cross-sectional views in order of the steps, showing a manufacturing method in a third embodiment of the present invention (No. 1).

6A to 6C are sectional views (2) in order of the steps, showing the manufacturing method according to the third embodiment of the present invention.

FIG. 7 is a process order cross-sectional view (No. 1) showing the manufacturing method according to the fourth embodiment of the present invention.

FIG. 8 is a step-by-step cross-sectional view showing the manufacturing method according to the fourth embodiment of the present invention (No. 2).

FIG. 9 is a sectional view in order of steps (No. 1) showing the manufacturing method according to the fifth embodiment of the present invention.

FIG. 10 is a sectional view in order of the steps (No. 2) showing the manufacturing method according to the fifth embodiment of the present invention.

FIG. 11 is a sectional view in order of the steps (1) showing the manufacturing method according to the sixth embodiment of the present invention.

FIG. 12 is a step-by-step cross-sectional view (No. 2) showing the manufacturing method according to the sixth embodiment of the present invention.

FIG. 13 is a process sequential cross-sectional view (No. 1) showing the element isolation method of the first conventional example.

FIG. 14 is a sectional view in order of the steps (No. 2) showing the element isolation method of the first conventional example.

FIG. 15 is a sectional view of a second conventional example.

16A to 16C are cross-sectional views in order of the processes (No. 1) showing the element isolation method of the third conventional example.

FIG. 17 is a process sectional view (2) showing the element isolation method of the third conventional example.

[Explanation of symbols]

11,51 Semiconductor support substrate 12,52 Buried oxide film 13,53 Silicon thin film 14, 54 Silicon oxide film 15 STI embedded nitride film 16, 55, 60 Silicon nitride film 16a, 16b spacer nitride film 17,57 Gate oxide film 18 First gate material 18a, 19b, 58a Gate electrode 18b, 19a, 30a Gate wiring 19 Second gate material 20 Source / drain region 21, 59 Element isolation groove 22,56 STI buried oxide film 23 Buffer oxide film 30 Third gate material 31, 67 Dummy gate oxide film 32, 68 dummy gate 33 Dummy gate polycrystalline silicon film 34, 70 Flattening oxide film 58 gate material 61 Silicon oxide film 62 abnormal shape

Front page continuation (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/08 H01L 29/78 617J 627C 21/76 L (72) Inventor Yukishige Saito 5-7 Shiba, Minato-ku, Tokyo No. 1 Inside NEC Corporation (72) Inventor Hisamu Takemura 5-7-1 Shiba, Minato-ku, Tokyo F-Term Inside NEC Corporation (reference) 5F032 AA09 AA34 AA46 AA77 AA84 BA01 BA05 CA17 DA28 DA30 DA33 DA78 5F048 AA04 AA07 AC01 BA16 BB05 BB12 BG05 BG14 DA25 DA27 5F110 AA06 AA18 AA26 CC02 DD05 DD13 EE01 EE09 EE14 EE15 EE45 EE50 FF02 FF04 FF23 GG02 GG25 HJ13 NN62 NN65 QQ01 QQ19

Claims (15)

[Claims] 1. An island-shaped silicon thin film separated by an element isolation groove filled with a buried insulating film is formed on an insulating film, and a gate electrode is formed on the silicon thin film via a gate insulating film. In the semiconductor device, the surface of the buried insulating film is flat and its height is substantially equal to the surface height of the gate electrode, and the buried insulating film is formed of a material having high resistance to an etching agent for oxide film. A semiconductor device characterized in that. 2. An island-shaped silicon thin film separated by an element isolation groove filled with a buried insulating film is formed on the insulating film, and a gate electrode is formed on the silicon thin film via a gate insulating film. In the semiconductor device, the surface of the buried insulating film is flat and its height is substantially equal to the surface height of the gate electrode, and a portion of the buried insulating film near the silicon thin film has a top height of the gate. A semiconductor device comprising a spacer film formed of a material having a high resistance to an oxide film etching material that is substantially equal to the surface height of an electrode. 3. An island-shaped silicon thin film isolated by an element isolation groove filled with a buried insulating film is formed on the insulating film, and a gate electrode is formed on the silicon thin film via a gate insulating film. In the semiconductor device, the surface of the buried insulating film is flat and its height is substantially equal to the surface height of the gate electrode, and the bottom surface and the side surface of the buried insulating film are resistant to the oxide film etching material. A semiconductor device characterized by being formed of a high material. 4. The semiconductor device according to claim 1, wherein a silicon oxide film is formed at a contact portion between the silicon thin film and the buried insulating film. 5. A gate wiring connected to the gate electrode extends on the buried insulating film, and the gate electrode and the gate wiring are buried in a planarizing oxide film. The semiconductor device according to claim 1. 6. The semiconductor device according to claim 1, wherein the material having high resistance to the oxide film etching material is silicon nitride. 7. A MOSFET isolated on a SOI substrate having a semiconductor supporting substrate, a buried oxide film and a silicon thin film, by element isolation trenches filled with a buried insulating film.
In the method for manufacturing a semiconductor device having: (1) a step of forming a thick film material layer on the silicon thin film; and (2) selectively etching the thick film material layer and the silicon thin film to form an element isolation groove. A step of forming, (3) a step of burying the element isolation trench with an insulating material having a high resistance to an oxide film etching material, and (4) a flattening of a film of an insulating material burying the element isolation trench. A method of manufacturing a semiconductor device, comprising: 8. The thick film material layer is a silicon oxide film, the thick film material layer is removed after the step (4), and a gate electrode forming material layer is deposited after forming a gate insulating film. 8. The method for manufacturing a semiconductor device according to claim 7, wherein 9. The thick film material layer is formed of a gate insulating film, a thin thin film gate electrode forming material layer and a silicon oxide film, and after the step (4), the silicon oxide film is removed to form a gate. 8. The method of manufacturing a semiconductor device according to claim 7, wherein an electrode forming material layer is deposited. 10. The step (3) after the step (2)
10. The method of manufacturing a semiconductor device according to claim 9, wherein a step of forming a silicon oxide film on the side surface of the silicon thin film is added prior to the step of. 11. The thick film material layer is formed of a dummy gate insulating film and a dummy gate electrode forming material layer, and after the step (4), a dummy gate wiring forming material layer is formed and the dummy gate is formed. The electrode forming material layer and the dummy gate wiring forming material layer are patterned,
The dummy gate electrode forming material layer and the dummy gate wiring forming material layer are removed after the formation of the planarization film that fills the dummy gate electrode forming material layer and the dummy gate wiring forming material layer, and then the planarization is performed. 8. The method for manufacturing a semiconductor device according to claim 7, wherein a gate electrode and a gate wiring embedded in the film are formed. 12. A MOSFE separated by a device isolation groove filled with a buried insulating film on an SOI substrate having a semiconductor supporting substrate, a buried oxide film and a silicon thin film.
In the method of manufacturing a semiconductor device having T, (1) a step of forming a gate insulating film and a gate electrode forming material layer on the silicon thin film, and (2) the gate electrode forming material layer, the gate insulating film, and the above A step of selectively etching a silicon thin film to form an element isolation groove, and (3)
A step of forming a side surface spacer on a side surface of the element isolation groove with an insulating material having high resistance to an oxide film etching material; and (4) a step of burying the element isolation groove with a burying insulating material. 5) A step of flattening a film of an insulating insulating material for burying the element isolation trench, the method for manufacturing a semiconductor device. 13. A MOSFET separated on an SOI substrate having a semiconductor supporting substrate, a buried oxide film and a silicon thin film, by an element isolation groove filled with a buried insulating film.
In the method of manufacturing a semiconductor device having T, (1) a step of forming a gate insulating film and a gate electrode forming material layer on the silicon thin film, and (2) the gate electrode forming material layer thick film material layer, the gate. A step of selectively etching the insulating film and the silicon thin film to form an element isolation groove, and (3) an insulating material having a high resistance to an oxide film etching material having a film thickness smaller than the depth of the element isolation groove. A step of depositing an etching resistant film on the substrate, and (4) burying the element isolation trench with a burying insulating material.
(5) a step of exposing the surface of the gate electrode forming material layer by performing a flattening process on the film of the insulating insulating material for burying the element isolation trench and the etching resistant film. Of manufacturing a semiconductor device. 14. The patterning of the gate electrode forming material layer, or the gate electrode forming material layer and the gate wiring forming material layer is performed immediately after the planarizing step or after forming the gate wiring forming material layer. 14. The method of manufacturing a semiconductor device according to claim 8, 9, 10, 12 or 13. 15. The method of manufacturing a semiconductor device according to claim 7, wherein the insulating material having high resistance to the etching agent for oxide film is silicon nitride.