JP2003115510A - Method for manufacturing semiconductor mounting body and manufacturing equipment of semiconductor mounting body - Google Patents

Method for manufacturing semiconductor mounting body and manufacturing equipment of semiconductor mounting body

Info

Publication number
JP2003115510A
JP2003115510A JP2002086616A JP2002086616A JP2003115510A JP 2003115510 A JP2003115510 A JP 2003115510A JP 2002086616 A JP2002086616 A JP 2002086616A JP 2002086616 A JP2002086616 A JP 2002086616A JP 2003115510 A JP2003115510 A JP 2003115510A
Authority
JP
Japan
Prior art keywords
sheet
manufacturing
semiconductor element
semiconductor package
package according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2002086616A
Other languages
Japanese (ja)
Other versions
JP3896017B2 (en
Inventor
Yoshitaka Sunakawa
義隆 砂川
Yoshitake Hayashi
林　　祥剛
Masayoshi Koyama
雅義 小山
Yoshihiro Tomura
善広 戸村
Toshiyuki Kojima
俊之 小島
Osamu Shibata
修 柴田
Ryuichi Saito
龍一 斎藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2002086616A priority Critical patent/JP3896017B2/en
Publication of JP2003115510A publication Critical patent/JP2003115510A/en
Application granted granted Critical
Publication of JP3896017B2 publication Critical patent/JP3896017B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/751—Means for controlling the bonding environment, e.g. valves, vacuum pumps
    • H01L2224/75101—Chamber
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75314—Auxiliary members on the pressing surface
    • H01L2224/75315—Elastomer inlay
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301—Bonding head
    • H01L2224/75314—Auxiliary members on the pressing surface
    • H01L2224/75317—Removable auxiliary member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

PROBLEM TO BE SOLVED: To solve the problem of a plurality of semiconductor elements being unable to be pressed uniformly in the conventional cases, when the plurality of semiconductor elements are mounted on a circuit board. SOLUTION: In the mounting body, one or a plurality of semiconductor element 2 are mounted on the circuit board 1, and resin 11 is arranged between the board 1 and the elements 2. This manufacturing equipment of the semiconductor mounting body is provided with a suction mechanism 4 which arranges a sheet material 3 whose form changes flexibly on the surface of the mounting body of which the surface does not face the board 1 of the element 2, an elevating mechanism 5 and an upper chamber 6 and a pressurization port 8 and an exhaust vent B which press the semiconductor element 3 with the sheet material 3 by applying an atmospheric pressure difference between a side where the element 2 does not exist and a side where the element 2 exists, in such a manner that the pressure on the side where the element 2 does not exist becomes higher than that on the side where the element exists, setting the arranged sheet material 3 as reference.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、回路基板上に半導
体素子を実装して半導体実装体を製造するための、半導
体実装体の製造方法、および半導体実装体の製造装置で
ある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package manufacturing method and a semiconductor package manufacturing apparatus for mounting a semiconductor element on a circuit board to manufacture a semiconductor package.

【０００２】[0002]

【従来の技術】半導体プロセスの微細化技術の進歩に伴
い半導体パッケージの形態もＱＦＰからμＢＧＡ、ＣＳ
Ｐ（チップサイズパッケージ）さらには、半導体ベアー
チップを直接回路基板上に接続するフリップチップ実装
へと進化している。2. Description of the Related Art With the progress of miniaturization technology of semiconductor processes, the form of semiconductor package is changed from QFP to μBGA, CS.
P (chip size package) Furthermore, it has evolved to flip chip mounting in which a semiconductor bare chip is directly connected to a circuit board.

【０００３】中でもフリップチップ実装は、半導体素子
と回路基板とが直接実装されているため、高速信号処理
を必要とする機器への応用展開が今後より一層加速する
ものと思われる。前述の実装技術を実現するためには、
実装プロセス技術が必要不可欠であり、半導体素子と回
路基板との接合を短時間でかつ確実な信頼性が確保でき
るように行う製造設備およびプロセス技術が特に重要で
ある。Among them, the flip-chip mounting is expected to further accelerate the application and development to devices requiring high-speed signal processing because the semiconductor element and the circuit board are directly mounted. In order to realize the above-mentioned mounting technology,
A mounting process technology is indispensable, and a manufacturing facility and a process technology for bonding a semiconductor element and a circuit board in a short time and ensuring reliable reliability are particularly important.

【０００４】以下、前記フリップチップ実装技術を用い
て実装を行った場合の一例について図面を参照して説明
する。図１０は、従来の半導体実装体の製造装置を用い
て、半導体素子を回路基板上にフリップチップ実装した
構造体の構成とその製造手順を説明するための図面であ
り、図１１は、熱源と半導体素子が当接する位置に弾性
体を配置し、フリップチップ実装を行う場合の模式図で
ある。尚、図１０〜図１１において、同一部分には同一
符号を付している。An example of mounting using the flip chip mounting technique will be described below with reference to the drawings. FIG. 10 is a drawing for explaining a structure of a structure in which a semiconductor element is flip-chip mounted on a circuit board and a manufacturing procedure thereof by using a conventional semiconductor mounting body manufacturing apparatus, and FIG. It is a schematic diagram in the case of arranging an elastic body at a position where a semiconductor element abuts and performing flip-chip mounting. 10 to 11, the same parts are designated by the same reference numerals.

【０００５】図１０に示すように、半導体素子２の電極
パッド１５上にＡｕ線を溶融して２段突起形状を有する
バンプ１６を形成した後、バンプ１６の２段突起部に導
電性接着剤１７を転写する。次に、半導体素子２をフェ
ースダウンし、回路基板１にパターン形成した端子電極
１８と接合し、前記導電性接着剤１７を硬化する。As shown in FIG. 10, after the Au wire is melted on the electrode pad 15 of the semiconductor element 2 to form the bump 16 having a two-step protrusion shape, a conductive adhesive is applied to the two-step protrusion portion of the bump 16. Transfer 17 Next, the semiconductor element 2 is faced down, joined to the terminal electrodes 18 patterned on the circuit board 1, and the conductive adhesive 17 is cured.

【０００６】次に、前記半導体素子２と回路基板１との
隙間に液状のエポキシ系封止樹脂１１を充填した後、図
１１に示すように、熱源７と半導体素子２が当接される
位置に弾性体２２を配置し、その弾性体２２で半導体素
子２の裏面を押圧しながら、前記封止樹脂１１を硬化す
る。Next, after filling the gap between the semiconductor element 2 and the circuit board 1 with a liquid epoxy-based encapsulating resin 11, as shown in FIG. 11, the heat source 7 and the semiconductor element 2 are in contact with each other. The elastic body 22 is disposed on the above, and the sealing resin 11 is cured while pressing the back surface of the semiconductor element 2 with the elastic body 22.

【０００７】尚、ベース台２１は、回路基板１を取り付
けるためのものである。このように、封止樹脂１１の加
熱時の熱膨張による半導体素子２の突き上げ力より、大
きな荷重で半導体素子２を押圧させながら硬化すること
で、接続抵抗値の増大や接合状態の不具合を最小限に防
ぐことができる。The base 21 is for mounting the circuit board 1. As described above, the semiconductor element 2 is hardened while being pressed with a large load by the pushing force of the semiconductor element 2 due to the thermal expansion during the heating of the sealing resin 11, so that the increase of the connection resistance value and the failure of the bonding state can be minimized. You can prevent it to the limit.

【０００８】[0008]

【発明が解決しようとする課題】しかしながら、図１０
で示した従来の構成の様に、回路基板１自体が、厚みが
あり比較的剛性が高く、半導体素子２に近い熱膨張係数
を有しかつ、少数の半導体素子２をフリップチップ実装
する場合に関しては特に問題はないと思われるが、図１
１に示すように、厚みおよび形状が異なった半導体素子
２を回路基板１にフリップチップ実装する場合、必然的
に厚い半導体素子２から順に低い方へと押圧が加わるた
め、一番高い半導体素子２に応力が集中し、大きなダメ
ージを与える。However, as shown in FIG.
Regarding the case where the circuit board 1 itself is thick and has relatively high rigidity, has a coefficient of thermal expansion close to that of the semiconductor element 2, and has a small number of semiconductor elements 2 mounted by flip-chip mounting, as in the conventional configuration shown in FIG. Is not considered to be a problem, but Fig. 1
As shown in FIG. 1, when the semiconductor elements 2 having different thicknesses and shapes are flip-chip mounted on the circuit board 1, the thicker semiconductor elements 2 are inevitably pressed in order from the lower side. The stress concentrates on the and causes great damage.

【０００９】なお、このダメージを抑制させるための手
段として、熱源７と半導体素子２が当接する位置に弾性
体２２Ａ、２２Ｂ、２２Ｃなどの緩衝材を用いて、各半
導体素子２の高さバラツキを吸収する方法を用いても、
各半導体素子２の厚みバラツキが大きい程、弾性体２２
Ｂに応力集中が作用するため、他の弾性体２２Ａおよび
２２Ｃに均一な押圧を与えることは困難である。As a means for suppressing this damage, a cushioning material such as elastic bodies 22A, 22B, 22C is used at the position where the heat source 7 and the semiconductor element 2 are in contact with each other, so that the height variation of each semiconductor element 2 is prevented. Even if you use the absorption method,
The greater the thickness variation of each semiconductor element 2, the elastic body 22
Since stress concentration acts on B, it is difficult to apply uniform pressure to the other elastic bodies 22A and 22C.

【００１０】また、弾性体２２Ｂの弾性変形体により、
半導体素子２に位置ズレが生じる危険性がある。Further, due to the elastically deformable body of the elastic body 22B,
There is a risk that the semiconductor element 2 may be displaced.

【００１１】また、回路基板１に異なった厚みおよび形
状を有する多数個の半導体素子２が存在する場合は、前
述の弾性体も全ての半導体素子２と相対した位置形状と
なるように取り付ける必要性がある。したがって製造装
置的には、必然的に一品種だけに限定された専用機とな
るため多品種の場合においては、品種別に都度弾性体を
設ける必要が生じるため、汎用性に問題を有する。When a large number of semiconductor elements 2 having different thicknesses and shapes are present on the circuit board 1, it is necessary to attach the above-mentioned elastic body so as to have a position and shape facing all the semiconductor elements 2. There is. Therefore, the manufacturing apparatus is necessarily a dedicated machine limited to one type, and in the case of multiple types, it is necessary to provide an elastic body for each type, which causes a problem in versatility.

【００１２】このように、異なった厚みおよび形状を有
する多数個の半導体素子をフリップチップ実装するため
には、従来の製造方法では困難を要する。As described above, in order to flip-chip mount a large number of semiconductor elements having different thicknesses and shapes, it is difficult for the conventional manufacturing method.

【００１３】本発明は、上記の従来の問題点を考慮し、
異なった厚みおよび形状を有する複数の半導体素子を回
路基板上に実装する際、それら複数の半導体素子を実質
上均一に加圧し半導体実装体を製造することができる半
導体実装体の製造方法、および半導体実装体の製造装置
を提供することを目的とするものである。The present invention takes the above-mentioned conventional problems into consideration,
When mounting a plurality of semiconductor elements having different thicknesses and shapes on a circuit board, the semiconductor mounted body can be manufactured by pressing the plurality of semiconductor elements substantially uniformly, and a semiconductor mounting method. It is an object to provide an apparatus for manufacturing a mounted body.

【００１４】[0014]

【課題を解決するための手段】第一の本発明（請求項１
に対応）は、回路基板上に１個又は複数個の半導体素子
が実装され、前記回路基板と前記半導体素子との隙間に
封止樹脂が配置された半導体実装体の、前記半導体素子
の前記回路基板と対向しない方の面に、形状がフレキシ
ブルに変形するシートを配置する第１工程と、その第１
工程の後に、前記シートを基準にして、前記半導体素子
が存在しない側の気圧が、前記半導体素子が存在する側
の気圧より高くなるように、前記半導体素子が存在しな
い側と前記半導体素子が存在する側とに気圧差を設け、
前記シートで前記半導体素子を加圧する第２工程とを備
えた半導体実装体の製造方法である。[Means for Solving the Problems] The first invention (Claim 1)
Corresponds to the circuit of the semiconductor element of a semiconductor mounting body in which one or a plurality of semiconductor elements are mounted on a circuit board, and a sealing resin is arranged in a gap between the circuit board and the semiconductor element. The first step of arranging a sheet whose shape is flexibly deformed on the surface not facing the substrate, and the first step
After the step, with the sheet as a reference, the pressure on the side where the semiconductor element does not exist is higher than the pressure on the side where the semiconductor element exists, so that the side where the semiconductor element does not exist and the semiconductor element exists. There is a pressure difference between the
And a second step of pressing the semiconductor element with the sheet.

【００１５】第二の本発明（請求項２に対応）は、前記
第２工程において、前記シートは少なくとも一部が前記
回路基板に接しない第一の本発明の半導体実装体の製造
方法である。A second aspect of the present invention (corresponding to claim 2) is the method for producing a semiconductor package according to the first aspect of the present invention, wherein at least a part of the sheet is not in contact with the circuit board in the second step. .

【００１６】第三の本発明（請求項３に対応）は、前記
第２工程は、前記シートの前記半導体素子が存在しない
側の面に所定の気体を供給するとともに、前記半導体素
子が存在する側の気体を排除することによって行う第一
又は第二の本発明の半導体実装体の製造方法である。In a third aspect of the present invention (corresponding to claim 3), in the second step, a predetermined gas is supplied to the surface of the sheet on the side where the semiconductor element does not exist, and the semiconductor element exists. It is a method for manufacturing a semiconductor package according to the first or second aspect of the present invention, which is performed by eliminating the gas on the side.

【００１７】第四の本発明（請求項４に対応）は、前記
第２工程において、前記シートは前記加圧が行われる少
なくとも直前には前記半導体素子および／または前記封
止樹脂に接しない第一又は第二の本発明の半導体実装体
の製造方法である。In a fourth aspect of the present invention (corresponding to claim 4), in the second step, the sheet does not come into contact with the semiconductor element and / or the sealing resin at least immediately before the pressure is applied. It is a method for manufacturing a semiconductor package according to the first or second aspect of the present invention.

【００１８】第五の本発明（請求項５に対応）は、前記
シートを加圧する少なくとも直前に、前記半導体素子に
配置された前記シートの周辺を固定する第３工程を備え
た第一又は第二の本発明の半導体実装体の製造方法であ
る。In a fifth aspect of the present invention (corresponding to claim 5), the first or the third step comprises a third step of fixing the periphery of the sheet arranged on the semiconductor element at least immediately before pressing the sheet. Second, it is a method for manufacturing a semiconductor package according to the present invention.

【００１９】第六の本発明（請求項６に対応）は、前記
シートを加圧する前に、前記シートの弛みをとる第五の
本発明の半導体実装体の製造方法である。A sixth aspect of the present invention (corresponding to claim 6) is the method for producing a semiconductor package according to the fifth aspect of the present invention, in which the sheet is slackened before the sheet is pressed.

【００２０】第七の本発明（請求項７に対応）は、前記
シートの弛みをとるとは、前記シートの外側から内側の
順に前記シートの周辺を固定することである第六の本発
明の半導体実装体の製造方法である。In the seventh aspect of the present invention (corresponding to claim 7), "to loosen the sheet" means to fix the periphery of the sheet in order from the outer side to the inner side of the sheet. It is a method for manufacturing a semiconductor package.

【００２１】第八の本発明（請求項８に対応）は、前記
シートを加圧する際、前記半導体素子が存在しない側か
ら前記シートをヒータで加熱する第４工程を備えた第一
又は第二の本発明の半導体実装体の製造方法である。An eighth aspect of the present invention (corresponding to claim 8) is the first or second aspect, which comprises a fourth step of heating the sheet with a heater from the side where the semiconductor element is not present, when the sheet is pressed. Is a method of manufacturing a semiconductor package according to the present invention.

【００２２】第九の本発明（請求項９に対応）は、前記
配置されたシートと前記ヒータとの間の距離を調節する
第八の本発明の半導体実装体の製造方法である。A ninth aspect of the present invention (corresponding to claim 9) is the method for manufacturing a semiconductor package according to the eighth aspect of the present invention, which adjusts the distance between the arranged sheet and the heater.

【００２３】第十の本発明（請求項１０に対応）は、前
記シートは、シリコン又はブナーＳで形成され、０．０
１ｍｍ〜３ｍｍの厚みを有するゴムシートである第一又
は第二の本発明の半導体実装体の製造方法である。In a tenth aspect of the present invention (corresponding to claim 10), the sheet is formed of silicon or Bunner S,
A method for manufacturing a semiconductor package according to the first or second aspect of the present invention, which is a rubber sheet having a thickness of 1 mm to 3 mm.

【００２４】第十一の本発明（請求項１１に対応）は、
前記シートは、ポリイミド、フッ素樹脂、ポリフェニレ
ンサルファイド、ポリプロピレン、ポリエーテル、ポリ
カーボネート、若しくはクロルスルホン化ポリエチレ
ン、又はそれらの複合体で形成され、０．０１ｍｍ〜１
ｍｍの厚みを有する樹脂シートである第一又は第二の本
発明の半導体実装体の製造方法である。The eleventh invention (corresponding to claim 11) is
The sheet is made of polyimide, fluororesin, polyphenylene sulfide, polypropylene, polyether, polycarbonate, chlorosulfonated polyethylene, or a composite thereof, and has a thickness of 0.01 mm to 1
A method for manufacturing a semiconductor package according to the first or second aspect of the present invention, which is a resin sheet having a thickness of mm.

【００２５】第十二の本発明（請求項１２に対応）は、
前記シートは、アルミニウム、銅、又はステンレスで形
成され、０．０１ｍｍ〜０．５ｍｍの厚みを有する金属
シートである第一又は第二の本発明の半導体実装体の製
造方法である。The twelfth aspect of the present invention (corresponding to claim 12) is
The sheet is a method for manufacturing a semiconductor package according to the first or second aspect of the present invention, which is a metal sheet formed of aluminum, copper or stainless steel and having a thickness of 0.01 mm to 0.5 mm.

【００２６】第十三の本発明（請求項１３に対応）は、
前記シートの前記半導体素子と接する側の面には、離型
処理が施されている第一又は第二の本発明の半導体実装
体の製造方法である。The thirteenth invention (corresponding to claim 13) is
The method for producing a semiconductor package according to the first or second aspect of the present invention, wherein a mold release treatment is applied to a surface of the sheet that is in contact with the semiconductor element.

【００２７】第十四の本発明（請求項１４に対応）は、
前記シートの前記半導体素子と接しない方の面には、熱
吸収を高めるための着色処理が施されている第一又は第
二の本発明の半導体実装体の製造方法である。The fourteenth invention (corresponding to claim 14) is
A method for manufacturing a semiconductor package according to the first or second aspect of the present invention, in which a surface of the sheet that is not in contact with the semiconductor element is subjected to a coloring treatment for enhancing heat absorption.

【００２８】第十五の本発明（請求項１５に対応）は、
前記シートには、熱吸収を高めるための着色添加物が含
まれている第一又は第二の本発明の半導体実装体の製造
方法である。The fifteenth invention (corresponding to claim 15) is
The sheet is the method for producing a semiconductor package according to the first or second aspect of the present invention, in which a coloring additive for enhancing heat absorption is contained.

【００２９】第十六の本発明（請求項１６に対応）は、
前記シートを配置する前に、前記半導体素子の近傍に前
記シートを支持するための支持枠を配置する第５工程を
備えた第一又は第二の本発明の半導体実装体の製造方法
である。The sixteenth invention (corresponding to claim 16) is
A method for manufacturing a semiconductor package according to the first or second aspect of the present invention, which comprises a fifth step of disposing a support frame for supporting the sheet in the vicinity of the semiconductor element before disposing the sheet.

【００３０】第十七の本発明（請求項１７に対応）は、
回路基板上に１個又は複数個の半導体素子が実装され、
前記回路基板と前記半導体素子との隙間に封止樹脂が配
置された半導体実装体の、前記半導体素子の前記回路基
板と対向しない方の面に、形状がフレキシブルに変形す
るシートを配置する配置手段と、前記配置されたシート
を基準にして、前記半導体素子が存在しない側の気圧
が、前記半導体素子が存在する側の気圧より高くなるよ
うに、前記半導体素子が存在しない側と前記半導体素子
が存在する側とに気圧差を設け、前記シートで前記半導
体素子を加圧する加圧手段とを備えた半導体実装体の製
造装置である。The seventeenth invention (corresponding to claim 17) is
One or more semiconductor elements are mounted on the circuit board,
Arrangement means for arranging a sheet whose shape is flexibly deformed on a surface of the semiconductor mounting body in which a sealing resin is arranged in a gap between the circuit board and the semiconductor element, the surface not facing the circuit board of the semiconductor element. With reference to the arranged sheet, the air pressure on the side where the semiconductor element does not exist is higher than the air pressure on the side where the semiconductor element exists, so that the side where the semiconductor element does not exist and the semiconductor element are An apparatus for manufacturing a semiconductor package, comprising: a pressurizing unit that presses the semiconductor element with the sheet by providing a pressure difference between the existing side and the existing side.

【００３１】第十八の本発明（請求項１８に対応）は、
前記加圧が行われる際、前記シートは少なくとも一部が
前記回路基板に接しない第十七の本発明の半導体実装体
の製造装置である。The eighteenth invention (corresponding to claim 18) is
At least a part of the sheet is not in contact with the circuit board when the pressing is performed, and is a device for manufacturing a semiconductor package according to the seventeenth aspect of the present invention.

【００３２】第十九の本発明（請求項１９に対応）は、
前記加圧手段は、前記シートの前記半導体素子が存在し
ない側の面に所定の気体を供給するとともに、前記半導
体素子が存在する側の気体を排除することによって前記
加圧を行う第十七又は第十八の本発明の半導体実装体の
製造装置である。The nineteenth invention (corresponding to claim 19) is
The pressurizing means supplies a predetermined gas to the surface of the sheet on the side where the semiconductor element does not exist, and performs the pressurization by eliminating the gas on the side where the semiconductor element exists. It is an apparatus for manufacturing a semiconductor package according to an eighteenth invention.

【００３３】第二十の本発明（請求項２０に対応）は、
前記加圧が行われる際、前記シートは前記加圧が行われ
る少なくとも直前には前記半導体素子および／または前
記封止樹脂に接しない第十七又は第十八の本発明の半導
体実装体の製造装置である。The twentieth invention of the present invention (corresponding to claim 20) is
When the pressure is applied, the sheet does not come into contact with the semiconductor element and / or the sealing resin at least immediately before the pressure is applied. The manufacture of the seventeenth or eighteenth aspect of the semiconductor package of the present invention. It is a device.

【００３４】第二十一の本発明（請求項２１に対応）
は、前記シートが加圧される少なくとも直前に、前記半
導体素子に配置された前記シートの周辺を固定する固定
手段を備えた第十七又は第十八の本発明の半導体実装体
の製造装置である。The twenty-first invention (corresponding to claim 21)
Is a semiconductor package manufacturing apparatus according to the seventeenth or eighteenth aspect of the present invention, comprising fixing means for fixing the periphery of the sheet arranged on the semiconductor element at least immediately before the sheet is pressed. is there.

【００３５】第二十二の本発明（請求項２２に対応）
は、前記シートを加圧する前に、前記シートの弛みをと
る弛み除去手段を備えた第二十一の本発明の半導体実装
体の製造装置である。Twenty-second invention (corresponding to claim 22)
Is a device for manufacturing a semiconductor package according to the twenty-first aspect of the present invention, which is provided with a slack removing means for removing the slack of the sheet before pressing the sheet.

【００３６】第二十三の本発明（請求項２３に対応）
は、前記シートの弛みをとるとは、前記シートの外側か
ら内側の順に前記シートの周辺を固定することである第
二十二の本発明の半導体実装体の製造装置である。The twenty third invention (corresponding to claim 23)
Is a device for manufacturing a semiconductor package according to the twenty-second aspect of the present invention, wherein "to loosen the sheet" means to fix the periphery of the sheet in order from the outer side to the inner side of the sheet.

【００３７】第二十四の本発明（請求項２４に対応）
は、前記シートが加圧される際、前記半導体素子が存在
しない側から前記シートを加熱する加熱手段を備えた第
十七又は第十八の本発明の半導体実装体の製造装置であ
る。24th invention (corresponding to claim 24)
Is a device for manufacturing a semiconductor package according to the seventeenth or eighteenth aspect of the present invention, which comprises heating means for heating the sheet from the side where the semiconductor element does not exist when the sheet is pressed.

【００３８】第二十五の本発明（請求項２５に対応）
は、前記配置されたシートと前記加熱手段との間の距離
を調節する距離調節手段を備えた第二十四の本発明の半
導体実装体の製造装置である。The twenty-fifth invention (corresponding to claim 25)
Is a manufacturing apparatus for a semiconductor package according to the twenty-fourth aspect of the present invention, which is provided with a distance adjusting means for adjusting a distance between the arranged sheet and the heating means.

【００３９】第二十六の本発明（請求項２６に対応）
は、前記シートは、シリコン又はブナーＳで形成され、
０．０１ｍｍ〜３ｍｍの厚みを有するゴムシートである
第十七又は第十八の本発明の半導体実装体の製造装置で
ある。The twenty-sixth invention (corresponding to claim 26)
The sheet is formed of silicon or Bunner S,
It is an apparatus for manufacturing a semiconductor package according to the seventeenth or eighteenth aspect of the present invention, which is a rubber sheet having a thickness of 0.01 mm to 3 mm.

【００４０】第二十七の本発明（請求項２７に対応）
は、前記シートは、ポリイミド、フッ素樹脂、ポリフェ
ニレンサルファイド、ポリプロピレン、ポリエーテル、
ポリカーボネート、若しくはクロルスルホン化ポリエチ
レン、又はそれらの複合体で形成され、０．０１ｍｍ〜
１ｍｍの厚みを有する樹脂シートである第十七又は第十
八の本発明の半導体実装体の製造装置である。The twenty-seventh invention (corresponding to claim 27)
The above-mentioned sheet is polyimide, fluororesin, polyphenylene sulfide, polypropylene, polyether,
Made of polycarbonate or chlorosulfonated polyethylene, or a composite thereof,
A seventeenth or eighteenth aspect of the present invention is a semiconductor package manufacturing apparatus which is a resin sheet having a thickness of 1 mm.

【００４１】第二十八の本発明（請求項２８に対応）
は、前記シートは、アルミニウム、銅、又はステンレス
で形成され、０．０１ｍｍ〜０．５ｍｍの厚みを有する
金属シートである第十七又は第十八の本発明の半導体実
装体の製造装置である。The twenty-eighth invention (corresponding to claim 28)
Is a manufacturing apparatus of a semiconductor package according to the seventeenth or eighteenth aspect of the present invention, wherein the sheet is a metal sheet formed of aluminum, copper or stainless steel and having a thickness of 0.01 mm to 0.5 mm. .

【００４２】第二十九の本発明（請求項２９に対応）
は、前記シートの前記半導体素子と接する側の面には、
離型処理が施されている第十七又は第十八の本発明の半
導体実装体の製造装置である。The twenty-ninth invention (corresponding to claim 29)
On the surface of the sheet on the side in contact with the semiconductor element,
It is an apparatus for manufacturing a semiconductor package according to the seventeenth or eighteenth aspect of the present invention, which has been subjected to a release treatment.

【００４３】第三十の本発明（請求項３０に対応）は、
前記シートの前記半導体素子と接しない方の面には、熱
吸収を高めるための着色処理が施されている第十七又は
第十八の本発明の半導体実装体の製造装置である。The thirtieth invention (corresponding to claim 30) is
A semiconductor package manufacturing apparatus according to the seventeenth or eighteenth aspect of the present invention, wherein the surface of the sheet that is not in contact with the semiconductor element is colored to enhance heat absorption.

【００４４】第三十一の本発明（請求項３１に対応）
は、前記シートには、熱吸収を高めるための着色添加物
が含まれている第十七又は第十八の本発明の半導体実装
体の製造装置である。Thirty-first invention (corresponding to claim 31)
Is a device for manufacturing a semiconductor package according to the seventeenth or eighteenth aspect of the present invention, wherein the sheet contains a coloring additive for increasing heat absorption.

【００４５】第三十二の本発明（請求項３２に対応）
は、前記シートが配置される前に、前記半導体素子の近
傍に前記シートを支持するために配置されるべき支持枠
を備えた第十七又は第十八の本発明の半導体実装体の製
造装置である。32nd invention (corresponding to claim 32)
Is a device for manufacturing a semiconductor package according to the seventeenth or eighteenth aspect of the present invention, which is provided with a support frame to be arranged in order to support the sheet in the vicinity of the semiconductor element before the sheet is arranged. Is.

【００４６】[0046]

【発明の実施の形態】以下に、本発明の実施の形態を図
面を参照して説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

【００４７】（第１の実施の形態）まず、本発明の第１
の実施の形態を図面を参照して説明する。(First Embodiment) First, the first embodiment of the present invention
Embodiments will be described with reference to the drawings.

【００４８】図１は、本発明の第１の実施の形態におけ
る半導体実装体の製造装置の構成を示すとともに、半導
体素子を回路基板上にフリップチップ実装した実装体の
全体構成と製造手順を説明するための図であり、図２
は、その詳細図である。FIG. 1 shows the configuration of a semiconductor package manufacturing apparatus according to the first embodiment of the present invention, and describes the overall configuration and manufacturing procedure of a package in which semiconductor elements are flip-chip mounted on a circuit board. FIG. 2 is a diagram for
Is a detailed view thereof.

【００４９】以下に、図１及び図２を用いて、本第１の
実施の形態における半導体実装体の製造方法及び製造装
置を説明する。The method and apparatus for manufacturing a semiconductor package according to the first embodiment will be described below with reference to FIGS. 1 and 2.

【００５０】図１および図２に示すように、回路基板１
上にフリップチップ実装にて搭載された複数個の半導体
素子２の上面に配置した、フレキシブルに変形するシー
ト材３の下面には、枠状のフレームに凹形状の溝加工が
施された吸着機構４と、シート材３を半導体素子２の裏
面近傍まで移動させる昇降機構５が設けられている。そ
の昇降機構５は例えばバネ等の弾性体で構成されてい
る。シート材３の上方には、上チャンバー６に熱源７が
内蔵された一体構造体Ｓが配置され、かつ上チャンバー
６の一部に加圧口８が構成されている。なお、図１およ
び図２において、回路基板１と各半導体素子２との隙間
には封止樹脂１１が配置されているものとする。その封
止樹脂１１は、ペースト状のものであってもよいし、シ
ート状のものであってもよい。As shown in FIGS. 1 and 2, the circuit board 1
The suction mechanism in which a concave groove is formed on a frame-like frame on the lower surface of the flexible deformable sheet material 3 arranged on the upper surfaces of the plurality of semiconductor elements 2 mounted by flip-chip mounting 4 and an elevating mechanism 5 for moving the sheet material 3 to the vicinity of the back surface of the semiconductor element 2. The elevating mechanism 5 is composed of an elastic body such as a spring. Above the sheet material 3, an integrated structure S in which the heat source 7 is built in the upper chamber 6 is arranged, and a pressurizing port 8 is formed in a part of the upper chamber 6. 1 and 2, it is assumed that the sealing resin 11 is arranged in the gap between the circuit board 1 and each semiconductor element 2. The sealing resin 11 may be in a paste form or a sheet form.

【００５１】このように構成された半導体実装体の製造
装置において、一体構造体Ｓをシート材３の方へ下降さ
せ上チャンバー６を吸着機構４に載せると、上チャンバ
ー６の重さにより昇降機構５によって吸着機構４が下降
し、シート材３の周辺が固定されるとともに、シート材
３が各半導体素子２の上面に配置される。次に、加圧口
８から、空気もしくは圧縮ガスを上チャンバー６内に供
給することで、図２に示すように、空気圧はシート材３
に伝達され、半導体素子２は均一な圧力で押圧される。In the semiconductor package manufacturing apparatus having the above structure, when the integrated structure S is lowered toward the sheet material 3 and the upper chamber 6 is placed on the suction mechanism 4, the lifting mechanism is moved by the weight of the upper chamber 6. The suction mechanism 4 is lowered by 5 and the periphery of the sheet material 3 is fixed, and the sheet material 3 is arranged on the upper surface of each semiconductor element 2. Next, by supplying air or compressed gas into the upper chamber 6 through the pressurizing port 8, the air pressure is increased as shown in FIG.
And the semiconductor element 2 is pressed with a uniform pressure.

【００５２】そして熱源７をシート材３に近づけること
により、熱源７の輻射熱がシート材３を介して、封止樹
脂１１に伝達されるため、厚みおよび形状が異なった多
数個の半導体素子２を実質上均一に加圧することができ
る。その結果、短時間に一括で加圧加熱処理を実現する
ことができる。When the heat source 7 is brought close to the sheet material 3, the radiant heat of the heat source 7 is transferred to the sealing resin 11 via the sheet material 3, so that a large number of semiconductor elements 2 having different thicknesses and shapes are formed. The pressure can be applied substantially uniformly. As a result, the pressure and heat treatment can be realized collectively in a short time.

【００５３】なお、図１３に示すように、シート材３に
空気圧を供給した際、シート材３の硬度が極めて低くそ
の厚みも極薄形状である場合、必然的に引張り弾性係数
も低くなる。すると、半導体素子２の裏面に充填された
封止樹脂１１は、シート材３で密閉された状態となり、
その内部応力の影響でａ部に示すように封止樹脂１１が
半導体素子２の上面に這い上がる現象が生じ、半導体素
子２の外観を損ない品質が低下する。そして、マザー基
板にＣＳＰ（チップサイズパッケージ）実装を行う際、
半導体素子２の表面に封止樹脂１１が付着していると、
実装機の吸着エラーが発生し、実装を行う上で大きな問
題となる。As shown in FIG. 13, when air pressure is supplied to the sheet material 3, if the hardness of the sheet material 3 is extremely low and the thickness thereof is extremely thin, the tensile elastic coefficient is inevitably low. Then, the sealing resin 11 with which the back surface of the semiconductor element 2 is filled is sealed with the sheet material 3,
Due to the influence of the internal stress, a phenomenon in which the sealing resin 11 crawls on the upper surface of the semiconductor element 2 occurs as shown in part a, and the appearance of the semiconductor element 2 is impaired and the quality is deteriorated. When the CSP (chip size package) is mounted on the mother board,
If the sealing resin 11 is attached to the surface of the semiconductor element 2,
A pick-up error of the mounting machine occurs, which is a big problem in mounting.

【００５４】また、図１４に示すように、隣接した半導
体素子２の距離Ｌが長いと、さらにシート材３が回路基
板１の面に密着される。このため、上述と同様の現象が
生じてしまう。Further, as shown in FIG. 14, when the distance L between the adjacent semiconductor elements 2 is long, the sheet material 3 is further adhered to the surface of the circuit board 1. Therefore, the same phenomenon as described above occurs.

【００５５】そこで、このような現象の発生を抑制する
ため、図１５に示すように、シート材３が回路基板１の
面と接しないような硬度と厚みと引張弾性係数とを有
し、かつ半導体素子２間の距離Ｌがあまり大きくならな
いようにする。すると、シート材３と回路基板１との間
に発生したギャップｄの影響によりＡおよびＢ方向にリ
ークパスができて、シート材３はその一部が回路基板１
に接しなくなる。このため、半導体素子２の表面に付着
した封止樹脂１１の影響を最小限に抑制することがで
き、品質向上を図ることができる。Therefore, in order to suppress the occurrence of such a phenomenon, as shown in FIG. 15, the sheet material 3 has such hardness, thickness and tensile elastic coefficient that the sheet material 3 does not come into contact with the surface of the circuit board 1. The distance L between the semiconductor elements 2 is prevented from becoming too large. Then, due to the influence of the gap d generated between the sheet material 3 and the circuit board 1, a leak path is created in the A and B directions, and a part of the sheet material 3 is part of the circuit board 1.
No longer touches. Therefore, the influence of the sealing resin 11 attached to the surface of the semiconductor element 2 can be suppressed to the minimum, and the quality can be improved.

【００５６】もちろん、シート材３は、図１６に示され
ているように、一部が回路基板１に接していても、一部
（もちろん、半導体素子２に触れない部分の内の一部）
が回路基板１に接していなければよい。Of course, as shown in FIG. 16, even if a part of the sheet material 3 is in contact with the circuit board 1, part (of course, part of the part which does not touch the semiconductor element 2) is used.
Need not be in contact with the circuit board 1.

【００５７】なお、空気圧を供給するタイミングを調節
して、加圧が行われる少なくとも直前には、シート材３
が半導体素子２および／または封止樹脂１１に接しない
ようにすることもできる。The sheet material 3 is adjusted at least immediately before the pressurization is performed by adjusting the timing of supplying the air pressure.
It is also possible not to contact the semiconductor element 2 and / or the sealing resin 11.

【００５８】また、下チャンバー９に構成された熱源１
０は回路基板１の予備加熱と封止樹脂１１の注入性を高
めるための加熱を行うものであり、排気口Ａはシート材
３を吸着させるものであり、排気口Ｂはシート材３の上
方と下方に差圧を生じさせるためのものであり、シール
用弾性体１２はシート材３の上方と下方とでのリークを
防ぐシール材である。断熱板１３は熱遮蔽するため断熱
材であり、高さ規制用ネジ１４は熱源７と半導体素子２
との高さを調整するものである。The heat source 1 constructed in the lower chamber 9
Reference numeral 0 denotes preheating of the circuit board 1 and heating for enhancing the injection property of the sealing resin 11, the exhaust port A is for adsorbing the sheet material 3, and the exhaust port B is above the sheet material 3. And a sealing elastic body 12 is a sealing material that prevents leakage above and below the sheet material 3. The heat insulating plate 13 is a heat insulating material for heat shielding, and the height regulating screw 14 is used for the heat source 7 and the semiconductor element 2.
The height of and is adjusted.

【００５９】また、シート材３は、例えば、０．０１ｍ
ｍ〜３ｍｍの厚みで構成されるシリコン、ブナーＳなど
のゴムシート材や、０．０１ｍｍ〜１ｍｍの厚みで構成
されるポリイミド、フッ素樹脂、ポリフェニレンサルフ
ァイド、ポリプロピレン、ポリエーテル、ポリカーボネ
ート、クロルスルホン化ポリエチレンなどの樹脂シート
材や、０．０１ｍｍ〜０．５ｍｍの厚みで構成される、
アルミニウム、銅、ステンレスなどの金属シート材であ
る。また、そのシート材３は輻射熱の吸収性の良い材料
を用いてもよい。The sheet material 3 is, for example, 0.01 m.
Silicone having a thickness of m to 3 mm, rubber sheet material such as Bunner S, polyimide having a thickness of 0.01 mm to 1 mm, fluororesin, polyphenylene sulfide, polypropylene, polyether, polycarbonate, chlorosulfonated polyethylene Such as a resin sheet material or a thickness of 0.01 mm to 0.5 mm,
It is a metal sheet material such as aluminum, copper, and stainless steel. Further, the sheet material 3 may use a material having a good absorption of radiant heat.

【００６０】また、シート材３は、上述したシリコン、
ブナーＳなどのゴムシート材や、ポリイミド、フッ素樹
脂、ポリフェニレンサルファイド、ポリプロピレン、ポ
リエーテル、ポリカーボネート、クロルスルホン化ポリ
エチレンなどの樹脂シート材や、アルミニウム、銅、ス
テンレスなどの金属シート材の複合材で構成されたシー
トであってもよい。The sheet material 3 is made of the above-mentioned silicon,
Consists of rubber sheet materials such as Bunner S, resin sheet materials such as polyimide, fluororesin, polyphenylene sulfide, polypropylene, polyether, polycarbonate, chlorosulfonated polyethylene, and metal sheet materials such as aluminum, copper and stainless steel It may be a prepared sheet.

【００６１】また、シート材３の半導体素子２と接する
側の面に離型処理を施すことにより、封止樹脂１１の付
着が抑制でき、たとえ封止樹脂１１が付着してもその洗
浄が簡略化されるため、作業効率が改善される。Further, by applying a mold release treatment to the surface of the sheet material 3 which is in contact with the semiconductor element 2, the adhesion of the sealing resin 11 can be suppressed, and even if the sealing resin 11 adheres, the cleaning thereof is simplified. Therefore, work efficiency is improved.

【００６２】また、シート材３の半導体素子２と接しな
い側に熱吸収を高めるための着色処理を施すことによ
り、早い熱吸収性が得られ、封止樹脂１１の短時間熱硬
化ができる。Further, by applying a coloring treatment for enhancing heat absorption to the side of the sheet material 3 which is not in contact with the semiconductor element 2, fast heat absorption can be obtained and the sealing resin 11 can be thermoset in a short time.

【００６３】また、シート材３に着色添加物を加えてお
くことにより、上述と同様の効果が得られる。By adding a coloring additive to the sheet material 3, the same effect as described above can be obtained.

【００６４】また、ゴムシート材、樹脂シート材、金属
シート材等で構成された複合体（例えば、シリコンゴム
シート材と金属シート材の組み合わせ）に上述した離型
処理と着色処理を施すことにより、弾性体のシリコンゴ
ムでシート材３の半導体素子２との接触によるダメージ
の抑制と封止樹脂１１のシート材３への付着防止を行
い、熱伝達に優れた金属シート材でシート材３の熱吸収
性を向上させることができる。Further, by subjecting a composite composed of a rubber sheet material, a resin sheet material, a metal sheet material and the like (for example, a combination of a silicon rubber sheet material and a metal sheet material) to the above-mentioned releasing treatment and coloring treatment. The elastic silicon rubber suppresses damage due to the contact of the sheet material 3 with the semiconductor element 2 and prevents the sealing resin 11 from adhering to the sheet material 3, and the sheet material 3 is made of a metal sheet material excellent in heat transfer. The heat absorption can be improved.

【００６５】また、複数個の凹形状の溝を構成した吸着
機構を用いて、シート材３の外側から順次シート材３を
半導体素子２に吸着させることにより、シート材３のた
るみが矯正され、安定した架張を得ることができる。Also, the slack of the sheet material 3 is corrected by sequentially adsorbing the sheet material 3 to the semiconductor element 2 from the outside of the sheet material 3 using an adsorption mechanism having a plurality of concave grooves. A stable suspension can be obtained.

【００６６】より具体的には、図１７に示されているよ
うに、（１）はじめに吸着機構４′における外側に形成
された溝４ａを利用してシート材３を吸着し、（２）つ
ぎに吸着機構４′における内側に形成された溝４ｂを利
用してシート材３を吸着することで、シート材３の外側
から内側の順にシート材３の周辺を固定するとともに、
張力を発生させてシート材３の弛みをとってもよい。な
お、溝４ａ〜４ｂの四隅が角丸に形成されていることに
より、シート材３の吸着が不要な皺の発生をともなうこ
となく行われる。More specifically, as shown in FIG. 17, (1) first, the sheet material 3 is sucked by utilizing the groove 4a formed on the outer side of the suction mechanism 4 ', and (2) By adsorbing the sheet material 3 using the groove 4b formed inside the adsorption mechanism 4 ', the periphery of the sheet material 3 is fixed in order from the outer side to the inner side of the sheet material 3, and
The sheet material 3 may be loosened by generating tension. In addition, since the four corners of the grooves 4a to 4b are formed into rounded corners, the suction of the sheet material 3 is performed without generating wrinkles that are unnecessary.

【００６７】さらに、前述のシート材３の架張は、真空
吸着以外の手法で行ってもよい。例えば、シート材３を
矢印Ｘの方向に供給する供給リール３ａとそれを巻き取
る巻き取りリール３ｂとをモーター駆動し、ある一定の
架張で制御しても構わない。さらに、供給リール３ａ側
と巻き取りリール３ｂ側の周辺にテンションゲージなど
を設け、その出力値を読み取り制御することにより、シ
ート材３に対して安定した架張を与えることも可能であ
る。Further, the stretching of the above-mentioned sheet material 3 may be performed by a method other than vacuum suction. For example, the supply reel 3a that supplies the sheet material 3 in the direction of the arrow X and the take-up reel 3b that winds the supply material may be driven by a motor and controlled by a certain tension. Further, a tension gauge or the like is provided around the supply reel 3a side and the take-up reel 3b side, and by reading and controlling the output value thereof, it is possible to give a stable stretch to the sheet material 3.

【００６８】また、排気口Ｂを介して下チャンバー９を
減圧状態にすることにより、下チャンバー９の上面に配
置したシート材３が吸着される。この時、回路基板１に
搭載された半導体素子２の裏面もシート材３の吸着効果
により押圧が作用するため、前述の空気圧による加圧方
式に対して負圧方式でも同じように加圧加熱硬化するこ
とができる。Further, by depressurizing the lower chamber 9 through the exhaust port B, the sheet material 3 arranged on the upper surface of the lower chamber 9 is adsorbed. At this time, the back surface of the semiconductor element 2 mounted on the circuit board 1 is also pressed by the suction effect of the sheet material 3, so that the negative pressure method is similarly applied to the negative pressure method instead of the air pressure method described above. can do.

【００６９】また、シート材３を基準に例えば、シート
材３の上面側に１気圧の空気圧を、下面側に減圧による
マイナス１気圧の負圧を供給させることにより、半導体
素子２の裏面はプラス１気圧とマイナス１気圧でトータ
ル２気圧の相乗効果を得ることができるため、半導体素
子２への押圧力が、空気圧だけでは不足する場合に有効
な手段である。Further, with the sheet material 3 as a reference, for example, by supplying air pressure of 1 atmosphere to the upper surface side of the sheet material 3 and supplying negative pressure of minus 1 atmosphere to the lower surface side, the back surface of the semiconductor element 2 is positive. Since it is possible to obtain a synergistic effect of a total of 2 atm with 1 atm and -1 atm, it is an effective means when the pressing force on the semiconductor element 2 is insufficient with only the air pressure.

【００７０】なお、上述した実施の形態では、本発明の
半導体実装体の製造装置の、配置手段の一例として吸着
機構４、昇降機構５及び上チャンバー６を、加圧手段の
一例として加圧口８（気体供給手段の一例）及び排気口
Ｂ（気体排除手段の一例）を、固定手段の一例として吸
着機構４及び上チャンバー６を、加熱手段の一例として
熱源７を、それぞれ用いた。In the above-described embodiment, the suction mechanism 4, the elevating mechanism 5 and the upper chamber 6 are used as an example of the arranging means and the pressure port is used as an example of the pressurizing means in the apparatus for manufacturing a semiconductor package of the present invention. 8 (an example of a gas supply unit) and an exhaust port B (an example of a gas removal unit), the adsorption mechanism 4 and the upper chamber 6 as an example of a fixing unit, and the heat source 7 as an example of a heating unit.

【００７１】また、弛み除去手段の一例として吸着機構
４（吸着機構４′）を用いた。The suction mechanism 4 (suction mechanism 4 ') is used as an example of the slack removing means.

【００７２】また、上述した実施の形態における熱源７
としては、カートリッジヒーター、セラミックヒータ
ー、シーズヒーター、ハロゲンランプ、赤外線若しくは
高周波を用いたヒーターの何れを用いることもできる。Further, the heat source 7 in the above-mentioned embodiment
Any of a cartridge heater, a ceramic heater, a sheath heater, a halogen lamp, and a heater using infrared rays or high frequency can be used.

【００７３】（第２の実施の形態）次に、本第２の実施
の形態における半導体実装体の製造装置の構成について
図面を参照して説明する。なお、第２の実施の形態と第
１の実施の形態の半導体実装体の製造装置は共通点が多
いので、第２の実施の形態では、相違点のみを説明す
る。(Second Embodiment) Next, the structure of a semiconductor package manufacturing apparatus according to the second embodiment will be described with reference to the drawings. Since the semiconductor mounting body manufacturing apparatuses of the second embodiment and the first embodiment have many common points, only the differences will be described in the second embodiment.

【００７４】図３は、シート材３を半導体素子２の上面
に配置する前に、半導体素子２の近傍に配置される支持
枠Ａの全体構成を示す斜視図であって、その支持枠Ａは
シート材３を支持するためのものである。図４は、支持
枠Ａが半導体素子２の近傍に配置された後に各半導体素
子２の上面にシート材３を配置し、そのシート材３で各
半導体素子２を加圧する状態を示す図である。FIG. 3 is a perspective view showing the overall structure of a support frame A arranged near the semiconductor element 2 before the sheet material 3 is arranged on the upper surface of the semiconductor element 2. It is for supporting the sheet material 3. FIG. 4 is a diagram showing a state where the sheet material 3 is arranged on the upper surface of each semiconductor element 2 after the support frame A is arranged in the vicinity of the semiconductor element 2, and each semiconductor element 2 is pressed by the sheet material 3. .

【００７５】図３および図４に示すように、回路基板１
に配置された支持枠Ａの各開口部は、対応する各半導体
素子２より大きく、かつ半導体素子２の高さと実質上同
等となるように、支持枠Ａの厚み調整が施されている。As shown in FIGS. 3 and 4, the circuit board 1
The thickness of the support frame A is adjusted so that the openings of the support frame A arranged at are larger than the corresponding semiconductor elements 2 and are substantially equal to the height of the semiconductor element 2.

【００７６】このように形成された支持枠Ａを、その支
持枠Ａの各開口部が対応する半導体素子２を囲むように
回路基板１上に配置した上で、シート材３をかぶせて加
圧すると、例えば、支持枠Ａが存在しない場合は、図４
の点線部ａに示すように、シート材３は半導体素子２を
押さえ込もうとする力が作用するため、無理なテンショ
ンが半導体素子２に伝わりダメージを与えたり、シート
材３を破損する危険性があるが、これに対して、支持枠
Ａを取り付けた場合は、半導体素子２に集中した応力が
作用するため、より安定した加圧加熱が維持され半導体
素子２の接続信頼性を向上することが可能となる。The supporting frame A thus formed is arranged on the circuit board 1 so that each opening of the supporting frame A surrounds the corresponding semiconductor element 2, and then the sheet material 3 is covered and pressed. Then, for example, when the support frame A does not exist, as shown in FIG.
As indicated by the dotted line portion a, the sheet material 3 exerts a force to press down the semiconductor element 2. Therefore, there is a risk that excessive tension is transmitted to the semiconductor element 2 to cause damage or damage the sheet material 3. However, when the support frame A is attached, stress concentrated on the semiconductor element 2 acts, so that more stable pressurization and heating is maintained and the connection reliability of the semiconductor element 2 is improved. Is possible.

【００７７】また、図１２に示すような、実装された多
数個の半導体素子２の全体領域より、大きな開口部を有
する支持枠Ｂを、図５に示すように、その開口部が全部
の半導体素子２を囲むように回路基板１上に配置した場
合においても、シート材３のテンションは、支持枠Ｂで
緩衝されるため、半導体素子２へのダメージを最小限に
抑えた状態で加圧加熱することができる。Further, as shown in FIG. 5, a support frame B having an opening larger than the entire area of the mounted semiconductor elements 2 as shown in FIG. Even when the sheet 2 is arranged on the circuit board 1 so as to surround the element 2, the tension of the sheet material 3 is buffered by the support frame B, so that the semiconductor element 2 is pressurized and heated with a minimum damage. can do.

【００７８】（第３の実施の形態）次に、本第３の実施
の形態における半導体実装体の製造装置の加熱構成とそ
の動作について図面を参照して説明する。なお、第３の
実施の形態と第１の実施の形態の半導体実装体の製造装
置は共通点が多いので、第３の実施の形態では、相違点
のみを説明する。(Third Embodiment) Next, the heating configuration and operation of the semiconductor package manufacturing apparatus according to the third embodiment will be described with reference to the drawings. Since the semiconductor mounting body manufacturing apparatuses of the third embodiment and the first embodiment have many common points, only the differences will be described in the third embodiment.

【００７９】図６は、熱源７の設定温度と封止樹脂１１
の昇温速度の相対関係を示した温度プロファイルであ
る。FIG. 6 shows the set temperature of the heat source 7 and the sealing resin 11.
3 is a temperature profile showing the relative relationship of the heating rate of.

【００８０】本加熱硬化方式は、輻射熱を用いているた
め、熱源７自体の設定温度と昇温速度は必然的に相対関
係を有している。例えば、図６に示すように、横軸に封
止樹脂１１の昇温速度の時間を、縦軸に封止樹脂１１の
温度を表すと、熱源７の設定温度が１７０度である場
合、所望の目標到達温度（１５０度〜１６０度）に到達
するまでの所要時間は約１２０秒である。なお、熱源７
とシート材３との距離を１．０ｍｍとした。Since the present heat curing method uses radiant heat, the set temperature of the heat source 7 itself and the rate of temperature rise necessarily have a relative relationship. For example, as shown in FIG. 6, when the temperature of the sealing resin 11 is plotted on the abscissa and the temperature of the sealing resin 11 is plotted on the ordinate, when the set temperature of the heat source 7 is 170 degrees, The time required to reach the target attainment temperature (150 to 160 degrees Celsius) is about 120 seconds. The heat source 7
The distance between the sheet material 3 and the sheet material 3 was 1.0 mm.

【００８１】これに対して、熱源７の設定温度が２６０
度である場合は、所望の目標到達温度（１５０度〜１６
０度）に約２０秒程度で到達する。尚、条件としては、
半導体素子２と熱源７との距離は一定でシート材３を介
した封止樹脂１１の温度測定である。On the other hand, the set temperature of the heat source 7 is 260
If the temperature is in degrees, the desired target temperature (150 degrees to 16 degrees
It reaches 0 degree in about 20 seconds. The conditions are as follows:
The distance between the semiconductor element 2 and the heat source 7 is constant, and the temperature of the sealing resin 11 is measured via the sheet material 3.

【００８２】このことから、熱源７自体の設定温度を高
温（例えば２６０度）に設定してシート材３に近接さ
せ、封止樹脂１１が所望の目標到達温度（１５０度〜１
６０度）に到達した後、熱源７の設定温度を保ったまま
シート材３と熱源７との空間距離を広げ、封止樹脂１１
が所望の設定温度を維持するような温度プロファイル制
御をすることにより、短時間で封止樹脂１１を昇温させ
ることができるとともに、短時間で封止樹脂１１を硬化
させることができ、熱硬化時間を大幅に短縮することが
できる。From this, the set temperature of the heat source 7 itself is set to a high temperature (for example, 260 ° C.) so as to be close to the sheet material 3, and the sealing resin 11 reaches the desired target temperature (150 ° C. to 1 ° C.).
(60 degrees), the spatial distance between the sheet material 3 and the heat source 7 is increased while maintaining the set temperature of the heat source 7, and the sealing resin 11
By controlling the temperature profile so that the desired set temperature is maintained, the temperature of the sealing resin 11 can be raised in a short time, and the sealing resin 11 can be cured in a short time. The time can be greatly reduced.

【００８３】本実施の形態では、熱源７に昇降自在なエ
アーシリンダー（図示せず）が設けられており、そのシ
ャフトの先端には、ある一定量の傾斜を付けたカムが設
けられていて、エアーシリンダーの流量切り換えによ
り、任意の位置に簡単にカムを動作させることができ、
それによりシート材３に対する熱源７の高さを容易に変
更することができる構成になっている。In the present embodiment, the heat source 7 is provided with an air cylinder (not shown) which can be raised and lowered, and a cam having a certain amount of inclination is provided at the tip of its shaft. By switching the flow rate of the air cylinder, you can easily operate the cam at any position,
Thereby, the height of the heat source 7 with respect to the sheet material 3 can be easily changed.

【００８４】また、上述の熱源７を昇降させるために、
電気的制御を有するステッピングモーターやパルスモー
ターなどを用いても構わない。In order to move the heat source 7 up and down,
A stepping motor or a pulse motor having electrical control may be used.

【００８５】なお、上記の熱源７を昇降するための手段
は、本発明の半導体実装体の製造装置の距離調節手段に
該当し、その距離調節手段の一例として図２に示す高さ
規制用ネジ１４も該当する。The means for raising and lowering the heat source 7 corresponds to the distance adjusting means of the semiconductor package manufacturing apparatus of the present invention, and the height adjusting screw shown in FIG. 2 is an example of the distance adjusting means. 14 is also applicable.

【００８６】（第４の実施の形態）次に、本第４の実施
の形態における半導体実装体の製造方法について図面を
参照して説明する。尚、本第４の実施の形態は第１の実
施の形態に用いた図面を参考に説明する。(Fourth Embodiment) Next, a method for manufacturing a semiconductor package according to the fourth embodiment will be described with reference to the drawings. The fourth embodiment will be described with reference to the drawings used in the first embodiment.

【００８７】図１は、半導体実装体の製造方法の全体構
成を説明するための断面図であり、図２は、その詳細図
である。FIG. 1 is a sectional view for explaining the overall structure of the method for manufacturing a semiconductor package, and FIG. 2 is a detailed view thereof.

【００８８】図１および図２に示すように、回路基板１
上にフリップチップ実装にて搭載された複数個の半導体
素子２を有する実装体を熱源１０上に配置し、回路基板
１と半導体素子２との隙間に封止樹脂１１を配置してお
く。そして、図１および図２に示すように、枠状のフレ
ームに凹形状の溝加工が施された吸着機構４にフレキシ
ブルに変形するシート材３を載置した後、排気口Ａを真
空に引くことにより、シート材３が半導体素子２に吸着
し一定圧に架張を維持することができる。さらに吸着機
構４には、複数個の凹形状の溝が設けられているため、
シート材３を外側から順次吸着させることにより、シー
ト材３のたるみが矯正され、より安定した架張を得るこ
とができる。As shown in FIGS. 1 and 2, the circuit board 1
A mounting body having a plurality of semiconductor elements 2 mounted thereon by flip-chip mounting is arranged on the heat source 10, and a sealing resin 11 is arranged in a gap between the circuit board 1 and the semiconductor element 2. Then, as shown in FIGS. 1 and 2, after the flexible deformable sheet material 3 is placed on the suction mechanism 4 in which the concave groove is formed in the frame-shaped frame, the exhaust port A is evacuated. As a result, the sheet material 3 is adsorbed to the semiconductor element 2 and the stretching can be maintained at a constant pressure. Furthermore, since the suction mechanism 4 is provided with a plurality of concave grooves,
By sequentially adsorbing the sheet material 3 from the outside, the slack of the sheet material 3 is corrected, and more stable tension can be obtained.

【００８９】さらに、吸着機構４の下側には、半導体素
子２全体より離れた位置にシート材３が架張されるよう
に圧縮バネを内蔵した昇降自在な機能を有する昇降機構
５が設けられているため、作業者がシート材３を取り付
ける際における、封止樹脂１１の付着やなんらかの半導
体素子２に対する不具合を解消することができる。Further, below the suction mechanism 4, there is provided an elevating mechanism 5 having a function of freely elevating and lowering, which has a built-in compression spring so that the sheet material 3 is stretched at a position apart from the entire semiconductor element 2. Therefore, when the worker attaches the sheet material 3, the adhesion of the sealing resin 11 and some troubles to the semiconductor element 2 can be eliminated.

【００９０】次に、熱源７を内蔵し一体構造を有した上
チャンバー６を下降すると上チャンバー６の自重によ
り、昇降機構５にも追従した動作が伝わるため、吸着機
構４に吸着したシート材３は半導体素子２の裏面近傍ま
で移動される。Next, when the upper chamber 6 having a built-in heat source 7 and having an integrated structure is lowered, the following motion is transmitted to the elevating mechanism 5 due to the weight of the upper chamber 6, so that the sheet material 3 adsorbed by the adsorption mechanism 4 is conveyed. Are moved to the vicinity of the back surface of the semiconductor element 2.

【００９１】この後、上チャンバー６の一部に設けられ
た加圧口８から、空気もしくは圧縮ガスを上チャンバー
６内に供給し、圧力をシート材３に加えることにより、
図２に示すように、空気圧はシート材３を介して、半導
体素子２に伝達されるため、異なった厚みや形状を有す
る多数個の半導体素子２を均一な圧力で押圧することが
できる。After that, air or compressed gas is supplied into the upper chamber 6 from the pressurizing port 8 provided in a part of the upper chamber 6, and pressure is applied to the sheet material 3,
As shown in FIG. 2, since the air pressure is transmitted to the semiconductor element 2 via the sheet material 3, a large number of semiconductor elements 2 having different thicknesses and shapes can be pressed with a uniform pressure.

【００９２】次に、チャンバー６に内蔵された熱源７を
シート材３に近づけると、熱源７の輻射熱は、前述と同
様にシート材３を介して、半導体素子２に介在させた封
止樹脂１１にも伝達されるため、封止樹脂１１を加熱硬
化することができる。Next, when the heat source 7 contained in the chamber 6 is brought close to the sheet material 3, the radiant heat of the heat source 7 is the sealing resin 11 interposed in the semiconductor element 2 via the sheet material 3 as described above. Therefore, the sealing resin 11 can be cured by heating.

【００９３】このように、半導体素子２に均一な押圧を
維持させた状態で、かつ熱源７とシート材３とを非接触
にして輻射熱で封止樹脂１１の加圧加熱硬化工程を一括
に処理することが実現できるため、生産性および接続信
頼性を大幅に向上させることが可能となる。As described above, while the semiconductor element 2 is kept uniformly pressed, the heat source 7 and the sheet material 3 are not in contact with each other, and the pressure heat curing step of the sealing resin 11 is collectively performed by radiant heat. Therefore, it is possible to significantly improve productivity and connection reliability.

【００９４】また、熱源７と半導体素子２の隙間は、輻
射熱との温度依存性に左右されるため、熱源７に設けた
高さ規制用ネジ１４の微調整により、輻射熱の空間ギャ
ップ調整を簡単に得ることができる。Since the gap between the heat source 7 and the semiconductor element 2 depends on the temperature dependence of the radiant heat, the space gap of the radiant heat can be easily adjusted by finely adjusting the height regulating screw 14 provided on the heat source 7. Can be obtained.

【００９５】また、半導体素子２に一定の加圧を与えた
状態で封止樹脂１１を加熱硬化させるために用いるシー
ト材３は、例えば、０．０１ｍｍ〜３ｍｍの厚みで構成
されるシリコン、ブナーＳなどのゴムシート材や、０．
０１ｍｍ〜１ｍｍの厚みで構成されるポリイミド、フッ
素樹脂、ポリフェニレンサルファイド、ポリプロピレ
ン、ポリエーテル、ポリカーボネート、クロルスルホン
化ポリエチレンなどの樹脂シート材や、０．０１ｍｍ〜
０．５ｍｍの厚みで構成される、アルミニウム、銅、ス
テンレスなどの金属シート材を有するシートである。The sheet material 3 used to heat and cure the encapsulating resin 11 in a state where a constant pressure is applied to the semiconductor element 2 is, for example, silicon or bunner having a thickness of 0.01 mm to 3 mm. Rubber sheet material such as S or 0.
Resin sheet materials such as polyimide, fluororesin, polyphenylene sulfide, polypropylene, polyether, polycarbonate, and chlorosulfonated polyethylene having a thickness of 01 mm to 1 mm, and 0.01 mm to
It is a sheet having a metal sheet material such as aluminum, copper, and stainless having a thickness of 0.5 mm.

【００９６】また、シート材３の半導体素子２と接する
側の面に離型処理を施しておくことにより、封止樹脂１
１の付着が抑制でき、たとえ封止樹脂１１が付着しても
その洗浄が簡略化されるため、作業効率が改善される。Further, the surface of the sheet material 3 in contact with the semiconductor element 2 is subjected to a mold release treatment, so that the sealing resin 1
1 can be suppressed from adhering, and even if the sealing resin 11 adheres, the cleaning thereof is simplified, so that the work efficiency is improved.

【００９７】また、シート材３の半導体素子２と接しな
い側の面に熱吸収を高めるための着色処理を施すことに
より、早い熱吸収性が得られ、封止樹脂１１の短時間熱
硬化ができる。Further, by applying a coloring treatment for enhancing heat absorption to the surface of the sheet material 3 which is not in contact with the semiconductor element 2, fast heat absorption can be obtained, and the sealing resin 11 can be thermally cured for a short time. it can.

【００９８】また、シート材３に着色添加物を加え場合
においても、上述と同様の効果が得られる。Also, when the coloring additive is added to the sheet material 3, the same effect as described above can be obtained.

【００９９】また、シート材３は、ゴムシート材、樹脂
シート材、金属シート材等の複合体に上述した離型処理
と着色処理を施すことにより後述のような効果が得られ
る。例えば、シリコンゴムシート材と金属シート材を組
み合わせることにより、弾性体のシリコンゴムで半導体
素子２と接触する際のダメージが抑制され、かつ封止樹
脂１１の付着防止を行うことができる。さらに、弾性体
の半導体素子２と接しない側の面に高剛性で熱伝達に優
れた金属シート材を形成しておくと、早く熱を吸収する
ことができる。さらに、金属シート材に押圧を加えた場
合、半導体素子２の形状が球状であれば特に問題はない
が、正方形もしくは長方形を有しているとコーナーのエ
ッジ部の応力によって、シート材に痕跡が生じるが、シ
ート材３を金属シート材とシリコンゴムの複合体で構成
しておくと、シリコンゴムによって痕跡が吸収されるた
め、シート自体のリサイクルが可能となり、材料コスト
を大幅に削減することができる。As the sheet material 3, the following effects can be obtained by subjecting a composite of a rubber sheet material, a resin sheet material, a metal sheet material and the like to the above-mentioned releasing treatment and coloring treatment. For example, by combining a silicone rubber sheet material and a metal sheet material, damage when the silicon rubber as an elastic body comes into contact with the semiconductor element 2 is suppressed, and adhesion of the sealing resin 11 can be prevented. Further, if a metal sheet material having high rigidity and excellent heat transfer is formed on the surface of the elastic body that is not in contact with the semiconductor element 2, heat can be absorbed quickly. Furthermore, when a pressure is applied to the metal sheet material, there is no particular problem as long as the semiconductor element 2 has a spherical shape. However, if the sheet material 3 is made of a composite of a metal sheet material and silicone rubber, the traces are absorbed by the silicone rubber, so that the sheet itself can be recycled and the material cost can be significantly reduced. it can.

【０１００】また、図４に示すように、回路基板１に搭
載された複数個の各半導体素子２に対応する複数個の開
口部を有し、かつ半導体素子２の高さと実質上同等の厚
み調整が施された支持枠Ａを、その支持枠Ａの各開口部
が対応する半導体素子２を囲むように配置すると、シー
ト材３を押さえ込もうとする応力が減少し、無理なテン
ションが半導体素子２に作用しないため、安定した接続
信頼性を得ることができる。Further, as shown in FIG. 4, the semiconductor device has a plurality of openings corresponding to the plurality of semiconductor elements 2 mounted on the circuit board 1 and has a thickness substantially equivalent to the height of the semiconductor element 2. When the adjusted supporting frame A is arranged so that each opening of the supporting frame A surrounds the corresponding semiconductor element 2, the stress for pressing the sheet material 3 is reduced, and the excessive tension is applied to the semiconductor. Since it does not act on the element 2, stable connection reliability can be obtained.

【０１０１】また、図１２に示すような、実装された多
数個の半導体素子２の全体領域より、大きな開口部を有
する支持枠Ｂを、図５に示すように、その開口部が全部
の半導体素子２を囲むように回路基板１上に配置した場
合においても、シート材３のテンションは、支持枠Ｂで
緩衝されるため、半導体素子２へのダメージを最小限に
抑えることができる。Further, as shown in FIG. 5, a support frame B having an opening larger than the entire area of the mounted large number of semiconductor elements 2 as shown in FIG. Even when it is arranged on the circuit board 1 so as to surround the element 2, the tension of the sheet material 3 is buffered by the support frame B, so that damage to the semiconductor element 2 can be minimized.

【０１０２】また、回路基板１に搭載された複数個の半
導体素子２は、少なくとも２種類以上の形状または厚み
を有するマルチチップモジュールであっても、等圧の押
圧を与えた状態で封止樹脂１１を一括で加圧加熱硬化さ
せることが可能である。Further, even if the plurality of semiconductor elements 2 mounted on the circuit board 1 are multi-chip modules having at least two types or shapes or thicknesses, the sealing resin is applied under a constant pressure. It is possible to press and heat 11 together.

【０１０３】また、回路基板１上に半導体素子２以外の
電子部品が混載している場合においても、上述と同じ効
果を得ることができる。Even when electronic components other than the semiconductor element 2 are mixedly mounted on the circuit board 1, the same effect as described above can be obtained.

【０１０４】（第５の実施の形態）次に、本第５の実施
の形態における半導体実装体の製造方法について図面を
参照して説明する。(Fifth Embodiment) Next, a method of manufacturing a semiconductor package according to the fifth embodiment will be described with reference to the drawings.

【０１０５】図７は、半導体実装体の製造方法がＳＢＢ
方式（スタッドバンプボンディング）である場合におけ
る工程を示す断面図であり、図８は、ペースト状もしく
はシート状の封止材を用いて半導体実装体を製造する製
造工程を示す断面図であり、図９は、電極パッドにハン
ダもしくは金メッキのバンプが形成された半導体素子を
用いた半導体実装体の製造方法を示す断面図である。FIG. 7 shows a method of manufacturing a semiconductor package according to SBB.
FIG. 9 is a cross-sectional view showing a process in the case of the method (stud bump bonding), and FIG. 8 is a cross-sectional view showing a manufacturing process for manufacturing a semiconductor package using a paste-like or sheet-like sealing material. FIG. 9 is a cross-sectional view showing a method for manufacturing a semiconductor package using a semiconductor element having solder bumps or gold-plated bumps formed on electrode pads.

【０１０６】図７に示すように、半導体素子２の電極パ
ッド１５にバンプ１６を形成する工程と、バンプ１６に
導電性接着剤１７を転写する工程と、半導体素子２を回
路基板１の端子電極１８にフリップチップ実装する工程
と、導電性接着剤１７を乾燥する工程と、半導体素子２
と回路基板１との隙間に封止樹脂１１を充填する工程を
有するＳＢＢ実装方式に対しても、上述したように半導
体素子２の上面に、フレキシブルに変形するシート材３
を配置し、半導体素子２の裏面を加圧しながら封止樹脂
１１を一括に加熱硬化処理することが可能である。As shown in FIG. 7, a step of forming bumps 16 on the electrode pads 15 of the semiconductor element 2, a step of transferring the conductive adhesive 17 to the bumps 16, and a step of connecting the semiconductor element 2 to the terminal electrodes of the circuit board 1. A step of flip-chip mounting on the semiconductor chip 18, a step of drying the conductive adhesive 17, and a semiconductor element 2
Also for the SBB mounting method including a step of filling the gap between the circuit board 1 and the circuit board 1, the sheet material 3 which is flexibly deformed on the upper surface of the semiconductor element 2 as described above.
And the sealing resin 11 can be collectively heat-cured while pressing the back surface of the semiconductor element 2.

【０１０７】また、シート材３を介した加圧効果によ
り、バンプ１６と端子電極１８は確実に接合されるた
め、２段突起形状を有するバンプ１６全体に導電接着剤
１７を均一に管理された量を転写する必要性が解消さ
れ、転写量の工程管理が省略できるとともに、導電性接
着剤１７の量を抑制することができ、隣接したバンプ１
６への導電性接着剤１７の付着が抑えられるため、８０
μｍ以下を有する狭ピッチな半導体素子２に対しても、
第１の実施の形態等で説明した半導体実装体の製造方法
を有効に用いることができる。Further, since the bumps 16 and the terminal electrodes 18 are reliably joined by the pressing effect via the sheet material 3, the conductive adhesive 17 is uniformly controlled over the entire bumps 16 having the two-step protrusion shape. The need to transfer the amount is eliminated, the process control of the transfer amount can be omitted, and the amount of the conductive adhesive 17 can be suppressed.
Since the adhesion of the conductive adhesive 17 to 6 is suppressed, 80
Even for a narrow pitch semiconductor element 2 having a size of μm or less,
The method for manufacturing a semiconductor package described in the first embodiment and the like can be effectively used.

【０１０８】また、図８に示すように、電極パッド１５
にバンプを形成する工程と、回路基板１上にペースト状
１９の封止材を塗布するかもしくはシート状の封止材を
貼り付ける工程を有する半導体実装体の製造方法に対し
ても、半導体素子２を実装時に封止材を加圧加熱状態で
仮硬化させた後、フレキシブルに変形するシート材３で
複数数個の半導体素子２の裏面を加圧させながら、封止
材を一括で加熱本硬化処理することができるため、実装
時間が短縮でき、生産性を向上することができる。Further, as shown in FIG.
Also for the method for manufacturing a semiconductor package having a step of forming bumps on the substrate and a step of applying a paste-like sealing material on the circuit board 1 or adhering a sheet-like sealing material to the semiconductor element, 2 is mounted, the encapsulant is temporarily cured under pressure and heating, and then the encapsulant is collectively heated while pressing the back surfaces of the plurality of semiconductor elements 2 with the sheet material 3 that is deformed flexibly. Since it can be cured, the mounting time can be shortened and the productivity can be improved.

【０１０９】また、図９に示すように、半導体素子２の
電極パッド１５にハンダバンプ２０を形成した工程の後
に、シート材３を用いて半導体素子２の裏面を加圧し、
ハンダバンプ２０を溶融させることにより、前述と同様
の一括処理が可能である。Further, as shown in FIG. 9, after the step of forming the solder bumps 20 on the electrode pads 15 of the semiconductor element 2, the back surface of the semiconductor element 2 is pressed by using the sheet material 3,
By melting the solder bumps 20, the same batch processing as described above can be performed.

【０１１０】また、半導体素子２の電極パッド１５に金
メッキバンプを形成した工程の後に、シート材３を用い
て半導体素子２の裏面を加圧し、前記バンプを熱圧着す
ることにより、前述と同様の効果を得ることができる。After the step of forming the gold-plated bumps on the electrode pads 15 of the semiconductor element 2, the back surface of the semiconductor element 2 is pressed by using the sheet material 3 and the bumps are thermocompression-bonded. The effect can be obtained.

【０１１１】[0111]

【発明の効果】以上説明したところから明らかなよう
に、本発明は、異なった厚みおよび形状を有する複数の
半導体素子を回路基板上に実装する際、それら複数の半
導体素子を実質上均一に加圧し半導体実装体を製造する
ことができる半導体実装体の製造方法及び製造装置を提
供することができる。As is apparent from the above description, according to the present invention, when a plurality of semiconductor elements having different thicknesses and shapes are mounted on a circuit board, the plurality of semiconductor elements are applied substantially uniformly. It is possible to provide a manufacturing method and a manufacturing apparatus for a semiconductor package that can manufacture a semiconductor package by pressing.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の第１及び第４の実施の形態の半導体実
装体の製造装置の断面図FIG. 1 is a cross-sectional view of a semiconductor package manufacturing apparatus according to first and fourth embodiments of the present invention.

【図２】本発明の第１及び第４の実施の形態の半導体実
装体の製造方法を説明するための図FIG. 2 is a diagram for explaining a method for manufacturing a semiconductor package according to the first and fourth embodiments of the present invention.

【図３】本発明の第２及び第４の実施の形態の支持枠の
斜視図FIG. 3 is a perspective view of a support frame according to second and fourth embodiments of the present invention.

【図４】本発明の第２及び第４の実施の形態の半導体実
装体の製造方法を説明するための図FIG. 4 is a diagram for explaining a method for manufacturing a semiconductor package according to second and fourth embodiments of the present invention.

【図５】本発明の第２及び第４の実施の形態の半導体実
装体の製造方法を説明するための図FIG. 5 is a diagram for explaining a method for manufacturing a semiconductor package according to second and fourth embodiments of the present invention.

【図６】本発明の第３の実施の形態の半導体実装体の製
造装置の熱源の設定温度と昇温速度の相対関係を示した
温度プロファイルを示す図FIG. 6 is a diagram showing a temperature profile showing a relative relationship between a set temperature of a heat source and a heating rate of a semiconductor package manufacturing apparatus according to a third embodiment of the present invention.

【図７】本発明の第５の実施の形態の、ＳＢＢ方式にお
ける半導体実装体の製造方法を説明するための図FIG. 7 is a view for explaining the method of manufacturing a semiconductor package according to the SBB method of the fifth embodiment of the present invention.

【図８】本発明の第５の実施の形態の、ペースト状もし
くはシート状の封止材を用いた場合における半導体実装
体の製造方法を説明するための図FIG. 8 is a diagram for explaining a method of manufacturing a semiconductor package according to a fifth embodiment of the present invention when a paste-like or sheet-like sealing material is used.

【図９】本発明の第５の実施の形態の、半導体素子の電
極パッドにハンダもしくは金メッキのバンプを形成した
場合における半導体実装体の製造方法を説明するための
図FIG. 9 is a diagram for explaining a method for manufacturing a semiconductor package according to the fifth embodiment of the present invention when solder or gold-plated bumps are formed on electrode pads of a semiconductor element.

【図１０】従来の半導体実装体の製造装置を用いて、半
導体素子を回路基板上にフリップチップ実装した構造体
の構成とその製造手順を説明するための図FIG. 10 is a view for explaining the structure of a structure in which a semiconductor element is flip-chip mounted on a circuit board and a manufacturing procedure thereof, using a conventional apparatus for manufacturing a semiconductor mounted body.

【図１１】従来の半導体実装体の製造装置で半導体実装
体を製造する際、弾性体を用いて半導体素子を回路基板
上にフリップチップ実装する状態を示す図FIG. 11 is a diagram showing a state in which a semiconductor element is flip-chip mounted on a circuit board using an elastic body when a semiconductor package is manufactured by a conventional semiconductor package manufacturing apparatus.

【図１２】本発明の第２及び第４の実施の形態の支持枠
の斜視図FIG. 12 is a perspective view of a support frame according to second and fourth embodiments of the present invention.

【図１３】本発明の第１の実施の形態の封止樹脂１１の
這い上がり現象の説明図（その１）FIG. 13 is an explanatory diagram (1) of the creeping phenomenon of the sealing resin 11 according to the first embodiment of the present invention.

【図１４】本発明の第１の実施の形態の封止樹脂１１の
這い上がり現象の説明図（その２）FIG. 14 is an explanatory view (No. 2) of the creeping phenomenon of the sealing resin 11 according to the first embodiment of the present invention.

【図１５】本発明の第１の実施の形態のシート材３が回
路基板１に接しない状態の説明図（その１）FIG. 15 is an explanatory view (part 1) of a state in which the sheet material 3 of the first embodiment of the present invention does not contact the circuit board 1.

【図１６】本発明の第１の実施の形態のシート材３が回
路基板１に接しない状態の説明図（その２）FIG. 16 is an explanatory diagram of a state where the sheet material 3 according to the first embodiment of the present invention does not contact the circuit board 1 (Part 2).

【図１７】本発明の第１の実施の形態の溝４ａ〜４ｂを
有する吸着機構４′の説明図FIG. 17 is an explanatory diagram of a suction mechanism 4 ′ having the grooves 4a and 4b according to the first embodiment of this invention.

【図１８】本発明の第１の実施の形態の供給リール３
ａ、巻き取りリール３ｂの説明図FIG. 18 is a supply reel 3 according to the first embodiment of this invention.
a, an explanatory view of the take-up reel 3b

【符号の説明】[Explanation of symbols]

１ 回路基板 ２ 半導体素子 ３ シート材 ４ 吸着機構 ５ 昇降機構 ６ 上チャンバー ７、１０ 熱源 ８ 加圧口 ９ 下チャンバー １１ 封止樹脂 １２ シール用弾性体 １３ 断熱板 1 circuit board 2 Semiconductor element 3 sheet materials 4 Adsorption mechanism 5 Lifting mechanism 6 Upper chamber 7, 10 heat source 8 pressurizing port 9 Lower chamber 11 Sealing resin 12 Elastic body for sealing 13 Insulation board

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小山 雅義 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 戸村 善広 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 小島 俊之 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 柴田 修 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 斎藤 龍一 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5F044 KK02 LL11 RR19    ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masayoshi Koyama             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Yoshihiro Tomura             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Toshiyuki Kojima             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Osamu Shibata             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. (72) Inventor Ryuichi Saito             1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric             Sangyo Co., Ltd. F-term (reference) 5F044 KK02 LL11 RR19

Claims (32)

【特許請求の範囲】[Claims] 【請求項１】 回路基板上に１個又は複数個の半導体素
子が実装され、前記回路基板と前記半導体素子との隙間
に封止樹脂が配置された半導体実装体の製造方法であっ
て、 前記半導体素子の前記回路基板と対向しない方の面に、
形状がフレキシブルに変形するシートを配置する第１工
程と、 その第１工程の後に、前記シートを基準にして、前記半
導体素子が存在しない側の気圧が、前記半導体素子が存
在する側の気圧より高くなるように、前記半導体素子が
存在しない側と前記半導体素子が存在する側とに気圧差
を設け、前記シートで前記半導体素子を加圧する第２工
程とを備えた半導体実装体の製造方法。1. A method of manufacturing a semiconductor mounting body, wherein one or a plurality of semiconductor elements are mounted on a circuit board, and a sealing resin is arranged in a gap between the circuit board and the semiconductor element. On the surface of the semiconductor element that does not face the circuit board,
A first step of arranging a sheet whose shape is flexibly deformed; A method of manufacturing a semiconductor package, comprising: a second step of increasing a pressure difference between a side where the semiconductor element does not exist and a side where the semiconductor element exists so that the sheet is pressed with the sheet. 【請求項２】 前記第２工程において、前記シートは少
なくとも一部が前記回路基板に接しない請求項１に記載
の半導体実装体の製造方法。2. The method for manufacturing a semiconductor package according to claim 1, wherein at least a part of the sheet is not in contact with the circuit board in the second step. 【請求項３】 前記第２工程は、前記シートの前記半導
体素子が存在しない側の面に所定の気体を供給するとと
もに、前記半導体素子が存在する側の気体を排除するこ
とによって行う請求項１又は２に記載の半導体実装体の
製造方法。3. The second step is performed by supplying a predetermined gas to a surface of the sheet on the side where the semiconductor element does not exist and removing the gas on the side where the semiconductor element exists. Alternatively, the method for manufacturing a semiconductor package according to Item 2. 【請求項４】 前記第２工程において、前記シートは前
記加圧が行われる少なくとも直前には前記半導体素子お
よび／または前記封止樹脂に接しない請求項１又は２に
記載の半導体実装体の製造方法。4. The method for manufacturing a semiconductor package according to claim 1, wherein in the second step, the sheet does not come into contact with the semiconductor element and / or the sealing resin at least immediately before the pressure is applied. Method. 【請求項５】 前記シートを加圧する少なくとも直前
に、前記半導体素子に配置された前記シートの周辺を固
定する第３工程を備えた請求項１又は２に記載の半導体
実装体の製造方法。5. The method for manufacturing a semiconductor package according to claim 1, further comprising a third step of fixing the periphery of the sheet arranged on the semiconductor element at least immediately before pressing the sheet. 【請求項６】 前記シートを加圧する前に、前記シート
の弛みをとる請求項５に記載の半導体実装体の製造方
法。6. The method for manufacturing a semiconductor package according to claim 5, wherein the slack of the sheet is removed before the sheet is pressed. 【請求項７】 前記シートの弛みをとるとは、前記シー
トの外側から内側の順に前記シートの周辺を固定するこ
とである請求項６に記載の半導体実装体の製造方法。7. The method for manufacturing a semiconductor package according to claim 6, wherein the loosening of the sheet is fixing the periphery of the sheet in order from the outer side to the inner side of the sheet. 【請求項８】 前記シートを加圧する際、前記半導体素
子が存在しない側から前記シートをヒータで加熱する第
４工程を備えた請求項１又は２に記載の半導体実装体の
製造方法。8. The method for manufacturing a semiconductor package according to claim 1, further comprising a fourth step of heating the sheet with a heater from a side where the semiconductor element does not exist when pressing the sheet. 【請求項９】 前記配置されたシートと前記ヒータとの
間の距離を調節する請求項８に記載の半導体実装体の製
造方法。9. The method for manufacturing a semiconductor package according to claim 8, wherein a distance between the arranged sheet and the heater is adjusted. 【請求項１０】 前記シートは、シリコン又はブナーＳ
で形成され、０．０１ｍｍ〜３ｍｍの厚みを有するゴム
シートである請求項１又は２に記載の半導体実装体の製
造方法。10. The sheet is silicon or Bunner S.
The method for manufacturing a semiconductor package according to claim 1 or 2, which is a rubber sheet having a thickness of 0.01 mm to 3 mm. 【請求項１１】 前記シートは、ポリイミド、フッ素樹
脂、ポリフェニレンサルファイド、ポリプロピレン、ポ
リエーテル、ポリカーボネート、若しくはクロルスルホ
ン化ポリエチレン、又はそれらの複合体で形成され、
０．０１ｍｍ〜１ｍｍの厚みを有する樹脂シートである
請求項１又は２に記載の半導体実装体の製造方法。11. The sheet is formed of polyimide, fluororesin, polyphenylene sulfide, polypropylene, polyether, polycarbonate, chlorosulfonated polyethylene, or a composite thereof.
The method for manufacturing a semiconductor package according to claim 1, which is a resin sheet having a thickness of 0.01 mm to 1 mm. 【請求項１２】 前記シートは、アルミニウム、銅、又
はステンレスで形成され、０．０１ｍｍ〜０．５ｍｍの
厚みを有する金属シートである請求項１又は２に記載の
半導体実装体の製造方法。12. The method for manufacturing a semiconductor package according to claim 1, wherein the sheet is a metal sheet made of aluminum, copper, or stainless steel and having a thickness of 0.01 mm to 0.5 mm. 【請求項１３】 前記シートの前記半導体素子と接する
側の面には、離型処理が施されている請求項１又は２に
記載の半導体実装体の製造方法。13. The method for manufacturing a semiconductor package according to claim 1, wherein the surface of the sheet on the side in contact with the semiconductor element is subjected to a mold release treatment. 【請求項１４】 前記シートの前記半導体素子と接しな
い方の面には、熱吸収を高めるための着色処理が施され
ている請求項１又は２に記載の半導体実装体の製造方
法。14. The method for manufacturing a semiconductor package according to claim 1, wherein a surface of the sheet which is not in contact with the semiconductor element is subjected to a coloring treatment for enhancing heat absorption. 【請求項１５】 前記シートには、熱吸収を高めるため
の着色添加物が含まれている請求項１又は２に記載の半
導体実装体の製造方法。15. The method for manufacturing a semiconductor package according to claim 1, wherein the sheet contains a coloring additive for increasing heat absorption. 【請求項１６】 前記シートを配置する前に、前記半導
体素子の近傍に前記シートを支持するための支持枠を配
置する第５工程を備えた請求項１又は２に記載の半導体
実装体の製造方法。16. The method for manufacturing a semiconductor package according to claim 1, further comprising a fifth step of disposing a support frame for supporting the sheet in the vicinity of the semiconductor element before disposing the sheet. Method. 【請求項１７】 回路基板上に１個又は複数個の半導体
素子が実装され、前記回路基板と前記半導体素子との隙
間に封止樹脂が配置された半導体実装体の製造装置であ
って、 前記半導体素子の前記回路基板と対向しない方の面に、
形状がフレキシブルに変形するシートを配置する配置手
段と、前記配置されたシートを基準にして、前記半導体
素子が存在しない側の気圧が、前記半導体素子が存在す
る側の気圧より高くなるように、前記半導体素子が存在
しない側と前記半導体素子が存在する側とに気圧差を設
け、前記シートで前記半導体素子を加圧する加圧手段と
を備えた半導体実装体の製造装置。17. A manufacturing apparatus of a semiconductor mounting body, wherein one or a plurality of semiconductor elements are mounted on a circuit board, and a sealing resin is disposed in a gap between the circuit board and the semiconductor element, On the surface of the semiconductor element that does not face the circuit board,
Arrangement means for arranging a sheet whose shape is flexibly deformed, with reference to the arranged sheet, the atmospheric pressure on the side where the semiconductor element does not exist is higher than the atmospheric pressure on the side where the semiconductor element exists, An apparatus for manufacturing a semiconductor package, comprising: a pressure unit that applies a pressure difference between a side where the semiconductor element does not exist and a side where the semiconductor element exists and presses the semiconductor element with the sheet. 【請求項１８】 前記加圧が行われる際、前記シートは
少なくとも一部が前記回路基板に接しない請求項１７に
記載の半導体実装体の製造装置。18. The apparatus for manufacturing a semiconductor package according to claim 17, wherein at least a part of the sheet does not contact the circuit board when the pressing is performed. 【請求項１９】 前記加圧手段は、前記シートの前記半
導体素子が存在しない側の面に所定の気体を供給すると
ともに、前記半導体素子が存在する側の気体を排除する
ことによって前記加圧を行う請求項１７又は１８に記載
の半導体実装体の製造装置。19. The pressurizing means supplies a predetermined gas to the surface of the sheet on the side where the semiconductor element does not exist, and eliminates the gas on the side where the semiconductor element exists to apply the pressure. The apparatus for manufacturing a semiconductor package according to claim 17, which is performed. 【請求項２０】 前記加圧が行われる際、前記シートは
前記加圧が行われる少なくとも直前には前記半導体素子
および／または前記封止樹脂に接しない請求項１７又は
１８に記載の半導体実装体の製造装置。20. The semiconductor package according to claim 17, wherein when the pressure is applied, the sheet does not come into contact with the semiconductor element and / or the sealing resin at least immediately before the pressure is applied. Manufacturing equipment. 【請求項２１】 前記シートが加圧される少なくとも直
前に、前記半導体素子に配置された前記シートの周辺を
固定する固定手段を備えた請求項１７又は１８に記載の
半導体実装体の製造装置。21. The apparatus for manufacturing a semiconductor package according to claim 17, further comprising fixing means for fixing the periphery of the sheet arranged on the semiconductor element at least immediately before the sheet is pressed. 【請求項２２】 前記シートを加圧する前に、前記シー
トの弛みをとる弛み除去手段を備えた請求項２１に記載
の半導体実装体の製造装置。22. The apparatus for manufacturing a semiconductor package according to claim 21, further comprising slack removing means for slackening the sheet before pressing the sheet. 【請求項２３】 前記シートの弛みをとるとは、前記シ
ートの外側から内側の順に前記シートの周辺を固定する
ことである請求項２２に記載の半導体実装体の製造装
置。23. The apparatus for manufacturing a semiconductor package according to claim 22, wherein the loosening of the sheet means fixing the periphery of the sheet in order from the outer side to the inner side of the sheet. 【請求項２４】 前記シートが加圧される際、前記半導
体素子が存在しない側から前記シートを加熱する加熱手
段を備えた請求項１７又は１８に記載の半導体実装体の
製造装置。24. The apparatus for manufacturing a semiconductor package according to claim 17, further comprising heating means for heating the sheet from the side where the semiconductor element does not exist when the sheet is pressed. 【請求項２５】 前記配置されたシートと前記加熱手段
との間の距離を調節する距離調節手段を備えた請求項２
４に記載の半導体実装体の製造装置。25. A distance adjusting means for adjusting a distance between the arranged sheet and the heating means.
4. The semiconductor package manufacturing apparatus according to item 4. 【請求項２６】 前記シートは、シリコン又はブナーＳ
で形成され、０．０１ｍｍ〜３ｍｍの厚みを有するゴム
シートである請求項１７又は１８に記載の半導体実装体
の製造装置。26. The sheet is made of silicon or Bunner S.
The apparatus for manufacturing a semiconductor package according to claim 17 or 18, which is a rubber sheet having a thickness of 0.01 mm to 3 mm and formed by. 【請求項２７】 前記シートは、ポリイミド、フッ素樹
脂、ポリフェニレンサルファイド、ポリプロピレン、ポ
リエーテル、ポリカーボネート、若しくはクロルスルホ
ン化ポリエチレン、又はそれらの複合体で形成され、
０．０１ｍｍ〜１ｍｍの厚みを有する樹脂シートである
請求項１７又は１８に記載の半導体実装体の製造装置。27. The sheet is formed of polyimide, fluororesin, polyphenylene sulfide, polypropylene, polyether, polycarbonate, chlorosulfonated polyethylene, or a composite thereof,
The apparatus for manufacturing a semiconductor package according to claim 17, which is a resin sheet having a thickness of 0.01 mm to 1 mm. 【請求項２８】 前記シートは、アルミニウム、銅、又
はステンレスで形成され、０．０１ｍｍ〜０．５ｍｍの
厚みを有する金属シートである請求項１７又は１８に記
載の半導体実装体の製造装置。28. The apparatus for manufacturing a semiconductor package according to claim 17, wherein the sheet is a metal sheet formed of aluminum, copper, or stainless steel and having a thickness of 0.01 mm to 0.5 mm. 【請求項２９】 前記シートの前記半導体素子と接する
側の面には、離型処理が施されている請求項１７又は１
８に記載の半導体実装体の製造装置。29. The mold release treatment is applied to the surface of the sheet on the side in contact with the semiconductor element.
8. The manufacturing apparatus for a semiconductor package according to item 8. 【請求項３０】 前記シートの前記半導体素子と接しな
い方の面には、熱吸収を高めるための着色処理が施され
ている請求項１７又は１８に記載の半導体実装体の製造
装置。30. The apparatus for manufacturing a semiconductor package according to claim 17, wherein a surface of the sheet that is not in contact with the semiconductor element is subjected to a coloring treatment for enhancing heat absorption. 【請求項３１】 前記シートには、熱吸収を高めるため
の着色添加物が含まれている請求項１７又は１８に記載
の半導体実装体の製造装置。31. The apparatus for manufacturing a semiconductor package according to claim 17, wherein the sheet contains a coloring additive for enhancing heat absorption. 【請求項３２】 前記シートが配置される前に、前記半
導体素子の近傍に前記シートを支持するために配置され
るべき支持枠を備えた請求項１７又は１８に記載の半導
体実装体の製造装置。32. The apparatus for manufacturing a semiconductor package according to claim 17, further comprising a support frame arranged to support the sheet in the vicinity of the semiconductor element before the sheet is arranged. .
JP2002086616A 2001-08-03 2002-03-26 Semiconductor mounting body manufacturing method and semiconductor mounting body manufacturing apparatus Expired - Fee Related JP3896017B2 (en)

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