JP2003114796A - Computer control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a program developed for an asynchronous type memory be usable for a synchronous type memory without being corrected. SOLUTION: This computer control circuit is provided with a selector 41 to select one of an output of a latch 50 holding an output instruction code, an instruction code outputted from the synchronous type memory, a Nop instruction code, and an instruction code generated at a breakpoint, and a register 55 to control selecting action of the selector 41. The selector 41 selects the Nop instruction code to be outputted when the instruction code outputted from the synchronous type memory is a jump instruction, selects the output of the latch to be outputted when it is a wait instruction, and selects the instruction code at the break point to be outputted when break point conditions are satisfied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer control circuit operated by a program such as microcode,
In particular, the present invention relates to a computer control circuit that allows a program developed for an asynchronous memory to be used as it is without changing when the asynchronous memory is changed to a synchronous memory.

[0002]

2. Description of the Related Art [First Prior Art] FIG. 7 shows the configuration of a conventional computer control circuit using an asynchronous memory. Reference numeral 11 is an asynchronous memory, and when an address is input, data is output after the access time. A program is stored in the asynchronous memory 11. Reference numeral 21 is a data register, 22 is an address register, and 23 is an address switching selector. When the asynchronous memory 11 is a RAM, when the program is downloaded from the control circuit 20 to the asynchronous memory 11, the address switching selector 23 is switched to the address register 22 side and the address register 22 stores the address of the asynchronous memory 11. Is set, the program data of the address is set in the data register 21, and the asynchronous memory 1 is set from the control circuit 20.
A write signal is input to 1 to write a program. If the asynchronous memory 11 is a ROM, the data register 21, the address register 22, and the selector 23 are unnecessary.

Reference numeral 25 is a start control register. When the program stored in the asynchronous memory 11 is executed, the control circuit 20 writes "1" (ST = 1) to start the program.

Reference numeral 26 is a breakpoint register group for executing an instruction code different from the instruction code written in the asynchronous memory 11 at a specific address during execution of a program stored in the asynchronous memory 11. Then, the specific address and instruction code are set from the control circuit 20. The breakpoint register group 26 is mainly used during program debugging.

A program counter 30 is used to generate an address of the asynchronous memory 11.
Reference numeral 32 denotes an address selector of the asynchronous memory 11, and the selection conditions of the selector 32 and its output are shown in FIG. 33 is a selector for the program counter 30. In FIG. 9, the value of the start control register 25 is S
When T = 0, the value PC of the program counter 30 is set to "000", and the address addr (RAM) of the asynchronous memory 11 is set to "000". Further, when the value of the start register 25 is ST = 1, the program control instructions non, wait, and jump which will be described later are given.
The address addr (RAM) of the asynchronous memory 11 and the program counter 30 according to p, push, and pop.
The value PC of is set.

28 is a stack instruction register group,
When the instruction code of the program is the Push instruction, the value PC of the program counter 30 is saved. When the instruction code is the Pop instruction, the value STK1 of the STK1 register is output to the address of the asynchronous memory 11 via the selector 32, and the adder 39 is also used. Then, 1 is added to the value of the STK1 register, and the value is set in the program counter 30 via the selector 33.
The stack instruction register group 28 is prepared for the depth of the program stack. FIG. 4 shows the instruction code and the operation when the stack has 6 stages.

Reference numeral 40 is an instruction code register, 42 is an instruction code register selector, and 45 is a comparator for detecting a match between the addresses BP1 to BP6 of the break pointer register group 26 and the value PC of the program counter 30.

Reference numeral 46 is a combinational circuit, which decodes the instruction code IR set in the instruction code register 40 to perform arithmetic processing such as ALU and to generate a program control instruction for controlling the order of the next program. .

This program control instruction includes a non instruction, a push instruction, a pop instruction, a jump instruction, and a wai.
There are t commands and the like. The non instruction is the program counter 30.
Is an instruction to sequentially execute the program by incrementing the value PC of. The push instruction is an instruction that causes the stack group 28 to save the value PC of the program counter 30 currently being executed, such as a subroutine instruction, and execute an instruction at another address. The pop instruction is an instruction that restores the value PC of the program counter 30 saved in the stack group 28 by a return instruction or the like and returns from the subroutine. The jump instruction is an instruction to jump to the address written in the instruction code register 40 when the jump condition is satisfied by a jump instruction or the like. The wait is an instruction to execute the program of the same address until a certain condition such as the Wait instruction is satisfied.

The combination circuit 48 establishes a program control instruction of the combination circuit 46 and a breakpoint (PC).
= BP1, BP2, BP3, BP4, BP5, or BP
6) At the time, it is a circuit that generates the selection condition of the instruction code register selector 42, and FIG. 8 shows the relationship between the selection condition of the selector 42 and the output. Depending on the selection result of the selector 42, a new instruction code I is stored in the instruction code register 40.
R is set. In FIG. 8, when the value of the start control register 25 is ST = 0, the Nop instruction is selected. When ST = 1, depending on the output of the combination circuit 46 and the output of the comparator 45, one of IR, BP1 to BP6, RAM or the like is selected. IR is the value of the instruction code register 40, BP1 to BP6 are specific outputs of the breakpoint register group 26, and RAM is the output of the asynchronous memory 11.

FIG. 12 shows an example of a program written in the asynchronous memory 11, and FIGS. 10 and 11 are timing charts when the program of FIG. 12 is executed in the computer control circuit using the asynchronous memory 11. is there. At this timing, the right end of FIG. 10 and the left end of FIG. 11 continue.

In FIGS. 10 and 11, CLK is a clock, ST is the value of the start control register 25, PC is the value of the program counter 30, and addr is the asynchronous memory 1.
1 address, do is output of asynchronous memory 11, IR
Is a value of the instruction code register 40, Decode is a program control instruction generated from the combination circuit 46, STKl
Is the value of the STK1 register of the stack group 28, and BPn is the value of the break point.

Here, ST, PC, IR and STK1 operate in synchronization with the rising edge of the clock CLK.
dr, do, and Decode operate asynchronously with the clock CLK.

Now, when ST = 1 is set in the start control register 25 from the control circuit 20, the asynchronous memory 1
The program stored in 1 starts from '000' (71 in FIG. 10). After that, the program control instruction De
If the code is a non instruction, the program counter 3
The value PC of 0 is sequentially incremented and input to the address of the asynchronous memory 11, a new instruction code is output from the asynchronous memory 11, and the instruction code register 4
Set to 0 as IR. When a new instruction code is set in the instruction code register 40, the combination circuit 46
A new program control instruction is determined according to the processing result of. IR0-Pop (IR8 in FIGS. 10 and 11)
As shown in FIG. 12, 1) indicates an instruction code written in each address of the asynchronous memory 11.

In FIGS. 10 and 11, 72 JMP0
Indicates the case where the condition is not satisfied in the conditional jump. At this time, the program control instruction becomes a non instruction, and the value PC of the program counter 30 is incremented by +1.

JMP1 at 73 is a conditional jump and indicates a case where the condition is satisfied. At this time, the program control instruction becomes a jump instruction, the address set in the instruction code register 40 is input to the address of the asynchronous memory 11 via the selector 32, and the output of the asynchronous memory 11 is output via the selector 42. , The jump destination instruction is set in the instruction code register 40.

Wait 1 of 74 is a Wait instruction, which is W
The case where the ait condition is satisfied is shown. At this time, the program control instruction is a wait instruction, and neither PC nor IR changes.

Wait0 of 75 is a Wait instruction and is W
The case where the ait condition is not satisfied is shown. At this time, the program control instruction becomes a non instruction, and the value PC of the program counter 30 is incremented by +1.

Push of 76 is a subroutine instruction,
The value PC of the program counter 30 is set in the STK1 register, the new jump destination address set in the instruction code register 40 is input to the address of the asynchronous memory 11 via the selector 32, and the output of the asynchronous memory 11 is output. Output via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

The Pop of 77 is a return instruction, and STK
The value PC of the program counter 30 saved in the 1 register is input to the address of the asynchronous memory 11 via the selector 32, the output of the asynchronous memory 11 is output via the selector 42, and the instruction of the return destination is It is set in the instruction code register 40.

BP1 at 78 indicates the operation when the break point is established. At this time, the instruction code BP1 set in the breakpoint register group 26 is
It is replaced with IR17 and set in the instruction code register 40. The program control instruction at this time is a nop instruction.

BP2 79 indicates the operation when the break point is established. At this time, the instruction code BP2 set in the break point register group 26 is
It is replaced with the IR 20 and set in the instruction code register 40. If the program control instruction at this time is a jump instruction, the address of the new jump destination set in the instruction code register 40 is input to the address of the asynchronous memory 11 via the selector 32, The output is output via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

As described above, in the computer control circuit using the asynchronous memory 11, after the instruction code is set in the instruction code register 40, the combination circuit 46 decodes the instruction code to generate the program control instruction, and the asynchronous memory The address of 11 is fixed, the instruction code corresponding to the address is output, and the instruction code register 40 is again output.
It is performed in 1 clock until it is set to. Therefore, the delay time by the combination circuit 46, the asynchronous memory 1
1 delay time, selector 32, 33, 42 delay time,
The total setup time and delay time of the instruction code register 40 must be within one clock cycle. Therefore, in the computer control circuit using the asynchronous memory 11, the operation speed is limited by the delay time of the circuit.

[Second Prior Art] FIG. 13 shows the configuration of a conventional synchronous access type computer control circuit. The same parts as those shown in FIG. 7 are designated by the same reference numerals. Three
Reference numerals 4 and 35 are selectors for the program counter 30. The selection conditions of the selector 34 and their outputs are shown in FIG. When ST = 0, the output nextP of the selector 34
C is '000', and when ST = 1, program control instructions push and po output from the combinational circuit 46 are output.
The operation corresponding to p, jump, wait, and non is performed.
For example, when the program control instruction is a non instruction, the adder 39 increments it by +1 (PC +
1).

The stack instruction register group 28 saves the value PC of the program counter 30 when the instruction code of the program is the Push instruction and S when it is the pop instruction.
The value STK1 of the TK1 register is incremented by +1 by the adder 39 and set in the program counter 30. Similar to the computer control circuit of FIG. 7, the stack register group 28 is prepared by the depth of the program stack.

The structure of the computer control circuit of the synchronous access system shown in FIG. 13 is different from the structure of the computer control circuit of the asynchronous memory explained in FIG. 7, except that the address of the asynchronous memory 11 is transferred to the program counter via the selector 23. Since it is directly connected to 30, it does not change in the middle of the clock, that is, it synchronizes with the clock.

FIG. 17 shows an example of a program when the synchronous access method is used, and FIGS. 15 and 16 show a computer control circuit which uses the synchronous access method.
It is a timing diagram when the program of is executed. At this timing, the right end of FIG. 15 continues to the left end of FIG.

In FIGS. 15 and 16, CLK is a clock, ST is the value of the start control register 25, and nextP.
C is the output of the selector 34, PC is the program counter 3
The value of 0, do is the output of the asynchronous memory 11, IR is the value of the instruction code register 40, and Decode is the combinational circuit 4
6, STK1 is the value of the STK1 register of the stack group 28, and BPn is the value of the breakpoint.

Here, ST, PC, IR and STK1 operate in synchronization with the rising edge of the clock CLK, but ne
xtPC, do, and Decode operate asynchronously with the clock CLK.

When ST = 1 is set in the start control register 25 from the control circuit 20, the asynchronous memory 1
The program stored in 1 starts from '000' (81 in FIG. 15). After that, the program control instruction is n
In the case of an on instruction, the value PC of the program counter 30 is sequentially incremented and input to the address of the asynchronous memory 11, a new instruction code is output from the asynchronous memory 11, and set in the instruction code register 40.
When a new instruction code is set in the instruction code register 40, the combination circuit 46 determines a new program control instruction. Here, IR0 to IR81 (Po
p) corresponds to the instruction code described in FIG.

JMP0 of 82 indicates the case where the condition is not satisfied in the conditional jump. At this time, the program control instruction becomes a non instruction, and the value PC of the program counter 30
Is incremented by +1.

JMPl of 83 indicates the case where the condition is satisfied by the conditional jump. At this time, the program control instruction becomes a jump instruction, and the address set in the instruction code register 40 is set in the program counter 30. At the next clock, the value PC of the program counter 30 is input to the address of the asynchronous memory 11, the output of the asynchronous memory 11 is output via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

Wait 1 at 84 is a Wait instruction
The case where the ait condition is satisfied is shown. At this time, the program control instruction is a wait instruction, and neither PC nor IR changes.

Wait 0 of 85 is a Wait instruction,
The case where the ait condition is not satisfied is shown. At this time, the program control instruction becomes a non instruction, and the value PC of the program counter 30 is incremented by +1.

Push of 86 is a subroutine instruction,
The value PC of the program counter 30 is set in the STK1 register, and the new jump destination address set in the instruction code register 40 is set in the program counter 30. At the next clock, the value PC of the program counter 30 is input to the address of the asynchronous memory 11, the output of the asynchronous memory 11 is output via the selector 42, and the instruction of the jump destination is the instruction code register 40.
Is set to.

Pop of 87 is a return instruction and STK
The value PC of the program counter 30 saved in the 1 register is incremented by +1 in the adder 39 and set in the program counter 30. At the next clock, the value of the program counter 30 is input to the address of the asynchronous memory 11, the output of the asynchronous memory 11 is output via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

BPl of 88 indicates the operation when the break point is established. At this time, the instruction code BP1 set in the breakpoint register group 26 is
It is replaced with IR17 and set in the instruction code register 40. The program control instruction at this time is a nop instruction.

BP2 at 89 indicates the operation when the break point is established. At this time, the instruction code BP2 set in the break point register is IR2.
It is replaced with 0 and set in the instruction code register 40. If the program control instruction at this time is a jump instruction, the address of the new jump destination set in the instruction code register 40 is set in the program counter 30. At the next clock, the value of the program counter 30 is input to the address of the asynchronous memory 11, the output of the asynchronous memory 11 is output via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

Here, the program control instruction is a jump instruction, a subroutine instruction, a return instruction, or the like.
In the case of the instruction, push instruction, and pop instruction, two clocks are required until the instruction of the jump destination is executed, so the instruction next to the jump instruction is executed before the instruction of the jump destination is executed. Therefore, in order to realize the same operation as the program of FIG. 12, as shown in FIG. 17, JMP, Pu
It is necessary to add the Nop instruction after the sh and Pop instructions.

As described above, in the computer control circuit using the synchronous access method, the program counter 30
The value PC of is set and input to the address of the asynchronous memory 11, and it takes one clock for the output of the asynchronous memory 11 to be set in the instruction code register 40. Also, it is set to 1 from the time it is set in the instruction code register 40 until it is decoded in the combination circuit 46 to generate the program control instruction and set in the program counter 30.
It takes a clock.

Therefore, in the computer control circuit using the synchronous access method, the address of the asynchronous memory 11 is set in the program counter 30, and the instruction code is output after the access time of the asynchronous memory 11,
Of the first delay time until the instruction code register 40 is set and the second delay time until the combination circuit 46 performs decoding after the instruction code register 40 is set and the program counter 30 is set. The clock cycle is determined by the delay time of the later one.

In the computer control circuit using the asynchronous memory described with reference to FIG. 7, since the clock cycle is determined by the sum of the first delay time and the second delay time, the synchronous access of FIG. The method can be operated with a faster clock, which facilitates timing design.

On the other hand, in the case of the synchronous access method, the timing of executing the instruction on the program counter 30 is 1
Clock slows down. If it is a continuous instruction, the execution of the instruction will be entirely delayed from the instruction of the program counter 30.

When a command such as a jump command or a subroutine command in which the value PC of the program counter 30 changes (jump command or the like) is executed, a new jump destination is set in the program counter 30. During execution of this jump instruction, the next instruction address is set in the program counter 30, the instruction next to the jump instruction is executed at the next clock, and the instruction at the jump destination is executed at the next clock. It will be.

Therefore, in order to use the program developed for the computer control circuit using the asynchronous memory shown in FIG. 7 in the computer control circuit using the synchronous memory shown in FIG. It is necessary to modify the program for the synchronous memory by inserting the Nop instruction or changing to the instruction that is not affected by the jump in consideration of the context.

[Third Conventional Example] FIG. 18 shows the configuration of a synchronous memory type computer control circuit. Reference numeral 10 is a synchronous memory, which is an asynchronous memory 11, an input data register 12, an address register 13, and an output data register 1.
5, the input and output are accessed in synchronization with the clock. The same parts as those in FIG. 13 are denoted by the same reference numerals.

The configuration of the synchronous memory type computer control circuit of FIG. 18 differs from that of the synchronous access type computer control circuit of FIG. 13 in that the asynchronous memory 11 of FIG. 18, the value addr of the address register 13 and the value P of the program counter 30 in the synchronous memory 10 of FIG.
Program counter 3 is configured so that C is the same.
The value set to 0 (PC-1) is the actual address ad
This is a point where the output by the address addr is delayed by one clock due to the output register 15.

FIG. 19 shows an example of a program of a computer control circuit using the synchronous memory 10, and FIGS. 20, 21 and 22 show the program of FIG. 19 in the computer control circuit using the synchronous memory 10. It is a timing diagram at the time of performing. This timing is shown in FIG.
21 is continuous with the left end of FIG. 21, and the right end of FIG.
Continue to the left edge of.

In FIGS. 20, 21, and 22, CLK
Is the clock, ST is the value of the start control register 25, n
extPC is the output of the selector 34, PC is the value of the program counter 30, DO is the output of the synchronous memory 10, IR
Is the value of the instruction code register 40, Decode is a program control instruction generated by the combination circuit 46, ST
K1 is the value of the STK1 register of the stack group 28, BPn
Is the value of the breakpoint.

Here, ST, PC, DO, IR, STK
1 operates in synchronization with the rising edge of the clock CLK, while nextPC and Decode operate asynchronously with the clock CLK.

Now, when ST = 1 is set in the start control register 25 from the control circuit 20, the synchronous memory 10
The program stored in is started from '000' (91 in FIG. 20). After that, the program control instruction is no
In the case of an n instruction, the value PC of the program counter 30 is sequentially incremented, but the value "PC-
1 ”is input to the address register 13 of the synchronous memory 10, a new instruction code is set in the output data register 15, and is set in the instruction code register 40 via the selector 42 at the next clock. When a new instruction code is set in the instruction code register 40, a new program control instruction is decided according to the processing result of the combination circuit 46. Here, IR0 to IR81 (Pop)
Corresponds to the instruction code shown in FIG.

JMP0 of 92 indicates the case where the condition is not satisfied in the conditional jump. At this time, the program control instruction becomes a non instruction, and the value PC of the program counter 30
Is incremented by +1.

JMP1 of 93 shows the case where the condition is satisfied by the conditional jump. At this time, the program control instruction becomes a jump instruction, and the address set in the instruction code register 40 is transferred through the selector 34 to the address register 13 of the synchronous memory 10 and the program counter 30.
Is set to. The instruction code is output from the synchronous memory 10 at the next clock, the output of the synchronous memory 10 is output at the next clock via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

Wait 1 at 94 is a Wait instruction
The case where the ait condition is satisfied is shown. At this time, the program control instruction becomes a wait instruction, and neither PC nor IR changes.

95, Wait 0, is a Wait instruction
The case where the ait condition is not satisfied is shown. At this time, the program control instruction becomes a non instruction, and the value PC of the program counter 30 is incremented by +1.

Push of 96 is a subroutine instruction and sets the value PC of the program counter 30 to the STK1 register, and the new jump destination address set to the instruction code register 40 is the address register 13 of the synchronous memory 10. And program counter 30
Is set to. The instruction code is output from the synchronous memory 10 at the next clock, the output of the synchronous memory 10 is output at the next clock via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

Pop of 97 is a return instruction and S
Program counter 3 saved in the TK1 register
The value of 0 is incremented by 1 in the adder 39 and set in the address register 13 and the program counter 30 of the synchronous memory 10. The instruction code is output from the synchronous memory 10 at the next clock, the output of the synchronous memory 10 is output at the next clock via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

BPl of 98 indicates the operation when the break point is established. At this time, the instruction code BPl set in the breakpoint register is IR1.
It is replaced with 7 and set in the instruction code register 40. The program control instruction at this time is a nop instruction. Here, it is necessary to set the value of the address +1 of the instruction to be replaced to the address of the breakpoint register.

BP2 of 99 indicates the operation when the break point is established. At this time, the instruction code BP2 set in the break point register is IR2.
It is replaced with 0 and set in the instruction code register 40. If the program control instruction at this time is a jump instruction, the new jump destination address set in the instruction code register 40 is set in the address register 13 and the program counter 30 of the synchronous memory 10. The instruction code is output from the synchronous memory 10 at the next clock, the output of the synchronous memory 10 is output at the next clock via the selector 42, and the instruction of the jump destination is set in the instruction code register 40.

Here, the program control instruction is ju due to a jump instruction, a subroutine instruction, a return instruction, or the like.
In the case of mp instruction, push instruction, and pop instruction, it takes 3 clocks until the instruction of the jump destination is executed.
The instruction next to the jump instruction is executed before the instruction at the jump destination is executed. Therefore, in order to realize the same operation as the program of FIG. 12, as shown in FIG.
It is necessary to add two Nop instructions after the P, Push, Pop, and Wait instructions.

As described above, in the computer control circuit using the synchronous memory 10, since the output of the synchronous memory 10 is synchronized with the clock, considering the operation including the Wait instruction, the breakpoint and other conditions. , FIG. 18
Since it is necessary to connect it to the instruction code register 40 via the selector 42 as shown in FIG. 1, after the address is set in the address address register 13 than in the synchronous access method computer control circuit shown in FIG.
It takes one clock to set the instruction code in the instruction code register 40.

Therefore, in the case of the computer control circuit using the synchronous memory 10, the timing of executing the instruction on the program counter 30 is delayed by 2 clocks. If it is a continuous instruction, the execution of the instruction will be entirely delayed from the instruction of the program counter 30.

When a command such as a jump or a subroutine command in which the value of the program counter changes (jump command, etc.) is executed, a new jump destination is set in the program counter. During execution of this jump command, The next instruction address is set in the program counter, the instruction after the jump instruction is executed at the next clock, and the instruction at the jump destination is executed at the next clock. Therefore, in order to use a program developed for a computer control circuit that uses the asynchronous memory 11 in a computer control circuit that uses the synchronous memory 10, considering the context of the jump instruction, N
It is necessary to modify the program for the synchronous memory 10 by inserting two op instructions or changing to instructions that are not affected by jumps.

[0064]

Today, process technology is evolving and miniaturized. Here, when a computer control circuit is once developed and then redeveloped in a more miniaturized process, when an asynchronous memory is used, a timing problem is likely to occur at the location of the asynchronous memory.
Therefore, since the timing problem is less likely to occur when the synchronous memory is used, the synchronous memory is often used. Furthermore, as a process maker, there are increasing cases where an asynchronous memory is not prepared.

However, when the asynchronous memory is changed to the synchronous memory, as described above, there is a delay of 1 clock from the input of the address to the program memory until the output of data. Therefore, the timing of executing the instruction on the program counter is delayed by one clock. If the instructions are continuous, the execution of the instructions will be entirely behind the instruction of the program counter.

When an instruction (jump instruction or the like) whose value of the program counter changes, such as a jump or a subroutine instruction, a new jump destination is set in the program counter. During execution of this jump instruction, Since the next instruction address is set in the program counter, the instruction after the jump instruction is executed at the next clock, and the instruction at the jump destination is executed at the next clock, so it is necessary for the asynchronous memory. In order to use the developed program in the synchronous memory, consider the context of jump instructions, insert Nop instructions,
There is a problem that the program needs to be modified for the synchronous memory by changing to an instruction that is not affected by the jump.

An object of the present invention is to solve the above problems and to realize a computer control circuit using a synchronous memory, which allows a program developed for an asynchronous memory to be used as it is without modification. Is.

[0068]

The invention according to claim 1 is
In a computer control circuit using a synchronous memory, one of an output of a latch holding an output instruction code, an instruction code output from the synchronous memory, a Nop instruction code, and an instruction code generated at a breakpoint is set. A selector for selecting and a register for controlling a selecting operation of the selector are provided. The selector selects the Nop instruction code by the register when the instruction code output from the synchronous memory is a jump instruction. Computer control characterized in that it is controlled so that the output of the latch is selected and outputted in the case of a Wait instruction and the instruction code of the breakpoint is selected and outputted when a breakpoint condition is satisfied. It was a circuit.

The invention according to claim 2 is the computer control circuit according to the invention according to claim 1, characterized in that the register holds the selection state of the selector for one clock period.

The invention according to claim 3 is the invention according to claim 1 or 2, characterized in that the program counter is controlled so as to have the same value as the address register built in the synchronous memory. It was a computer control circuit.

[0071]

BEST MODE FOR CARRYING OUT THE INVENTION In a computer control circuit using a synchronous memory of the present invention, an instruction code selection selector is used, and this selector is controlled by an instruction code selection register. As a result, the output of the latch holding the instruction code, the instruction code output from the synchronous memory, Nop
Select one of the instruction codes generated at the instruction code, the break point, etc. with the instruction code selection selector. If the instruction code is a jump instruction, insert a Nop instruction, and
In the case of the ait instruction, the same instruction code is output from the latch that latches the instruction, and when the breakpoint condition is satisfied, that instruction code is output.

With this configuration, since the instruction code selection register is used to select the instruction code, the selected instruction code does not change during the clock. That is, the instruction code is synchronized with the clock. Therefore, the output of the selector can be used in the same manner as the output of the instruction code register.

FIG. 1 shows the configuration of a computer control circuit according to one embodiment of the present invention. Reference numeral 10 is a synchronous memory, which includes an asynchronous memory 11, an input data register 12, an address register 13, and an output data register 15, and its input and output are accessed in synchronization with a clock. 21
Is a data register, 22 is an address register, and 23 is an address switching selector. These are synchronous memory 1
When 0 is a RAM, it is used when the program is downloaded from the control circuit 20 to the asynchronous memory 11, but it is not necessary when the synchronous memory 10 is a ROM.

Reference numeral 25 is a start control register, and the program is started by writing ST = 1 from the control circuit 20. Reference numeral 26 is a breakpoint register group, which is mainly used during program debugging.

A program counter 30 has the same value as that of the address register 13 in the synchronous memory 10. Reference numeral 31 is a selector for the address of the synchronous memory 10 and for the program counter 30, and its selection condition and output nextPC are shown in FIG. In FIG. 3, in the selector 31, the value of the start control register 25 is ST = 0.
'000' is selected in the case of, and program control instructions push, pop, jump, wait, are selected in the case of ST = 1.
PC + 1, PC, IR, STK1 or the like is selected according to non. For example, when the program control instruction is a non instruction, the value PC of the program counter 30 is the adder 39.
Is incremented by 1 to become PC + 1.

28 is a stack instruction register group,
When the instruction code of the program is the Push instruction, the value PC of the program counter 30 is saved, and when it is the Pop instruction, the value of the STK1 register is set to the address of the synchronous memory 10 and the program counter 30 via the selector 31. The stack register group 28 is prepared by the depth of the stack of the program. FIG. 4 shows the instruction code and the operation when the stack has 6 stages.

Reference numeral 41 is an instruction code selection selector, and 45 is an address BP1 to BP1 of the break pointer register group 26.
It is a comparator that detects the coincidence between BP6 and the value PC of the program counter 30.

Reference numeral 46 denotes a combinational circuit, which decodes the instruction code output from the instruction code selection selector 41 to perform arithmetic processing such as ALU, and at the same time, program control instructions push and po that control the order of the next program.
p, jump, wait, non are generated.

47 is also a combinational circuit, and a combinational circuit 46
The program control instruction generated in step 3, the output of the comparator 45, and the output of the start control register 25 are input, and the selection condition of the instruction code selection selector 41 is generated. An instruction code selection register 55 sets the selection condition of the selector 41 according to the processing result of the combination circuit 47.

FIG. 2 shows the relationship between the selection condition of the selector 41 and its output. In FIG. 2, when ST = 0 and the program control instruction is jump, push, or pop, the Nop instruction is selected, and when ST = 1 and the program control instruction is non, RAM (output of the synchronous memory 10).
Is selected, ST = 1 and the program control instruction is wai
Latch 50 for latching the output of the selector 41 at t
Output R1 is selected, ST = 1 and PC = BP1, B
B when P2, BP3, BP4, BP5, or BP6
One of the corresponding P1 to BP6 is selected.

5 and 6 are timing diagrams of the computer control circuit according to the embodiment of the present invention. This timing chart is a timing chart when the program (FIG. 12) for the computer control circuit using the asynchronous memory shown in FIG. 7 is executed. At this timing, the right end of FIG. 5 continues to the left end of FIG.

In FIGS. 5 and 6, CLK is a clock,
ST is the value of the start control register 25, nextPC is the output of the selector 31, PC is the value of the program counter 30, DO is the output of the synchronous memory 10, R1 is the value of the latch 50 holding the instruction code, and Sel is the instruction code selection. The value of the register 55, IR is the instruction code selection selector 41
, Decode is a program control instruction generated by the combination circuit 46, STK1 is the value of the STK1 register of the stack group 28, and BPn is the value of the break point.

Here, ST, PC, DO, R1, Se
l and STK1 operate in synchronization with the rising edge of the clock CLK. IR is delayed by the operation time of the selector 41 with respect to the rising edge of the clock. Also, nextPC,
Decode operates asynchronously with clock CLK.

Here, the value addr of the address register 13 inside the synchronous memory 10 and the program counter 3 are used.
The value PC of 0 becomes the same, the value (PC-1) set in the program counter 30 becomes the actual address addr, and the output by the address addr is delayed by one clock by the output register 15.

Now, when ST = 1 is set in the start control register 25 from the control circuit 20, the synchronous memory 10
The program stored in is started from '000' (61 in FIG. 5). After that, the program control instruction is non
In the case of an instruction, the value PC of the program counter 30 is sequentially incremented, but one value before that, "PC-
1 ”is input to the address register 13 of the synchronous memory 10, a new instruction code is set in the output data register 15, and its output becomes a new instruction code via the selector 41. Then, a new program control instruction is determined according to the processing result of the combination circuit 46. here,
IR0 to IR81 (Pop) correspond to the instruction code in FIG.

JMP0 of 62 indicates the case where the condition is not satisfied in the conditional jump. At this time, the program control instruction becomes a non instruction, and the value P of the program counter 30
C is incremented by +1.

JMPl of 63 indicates the case where the condition is satisfied in the conditional jump. At this time, the program control instruction becomes a jump instruction, and the address on the instruction code IR output by the selector 41 is set in the address register 13 and the program counter 30 of the synchronous memory 10 via the selector 31. In the case of the jump instruction, the combination circuit 47 selects the Nop instruction as the next output of the selector 41, the instruction code selection register 55 is set for the selection of Nop at the next clock, and the selector 41 outputs the instruction code as the instruction code. The Nop command is output. At the next clock, the instruction code at the jump destination is output from the synchronous memory 10. At this time, since the program control instruction is a non instruction, the instruction code selection register 55 is set for selecting the output of the synchronous memory 10,
The output of the synchronous memory 10 is output via the selector 41 and becomes the instruction code of the jump destination. In this way, the Nop instruction is automatically inserted between the jump instruction and the jump destination instruction.

Wait 1 of 64 is a Wait instruction
The case where the ait condition is satisfied is shown. At this time, the program control instruction becomes a wait instruction, and the synchronous memory 10
The values of the address register 13 and the program counter 30 do not change. In addition, the combination circuit 47 allows the selector 4
R1 of the latch 50 is selected as the output next to 1, the instruction code selection register 55 is set for the selection of R1 of the latch 50 at the next clock, and the same instruction code as the one currently being executed is output from the selector 41.

Wait0 of 65 is a Wait instruction, and
The case where the ait condition is not satisfied is shown. At this time, the program control instruction becomes a non instruction, and the value PC of the program counter 30 is incremented by +1. At this time, since the program control instruction is the non instruction, the instruction code selection register 55 is set to select the output of the synchronous memory 10, the output of the synchronous memory 10 is output via the selector 41, and the next instruction It becomes a code.

Push of 66 is a subroutine instruction,
The value PC of the program counter 30 is set in the STK1 register. At this time, the program control instruction is pus
This is the h instruction, and the address on the instruction code IR output by the selector 41 is set in the address register 13 and the program counter 30 of the synchronous memory 10. In the case of the push instruction, the combination circuit 47 selects the Nop instruction as the output of the next selector 41, the instruction code selection register 55 is set for the Nop selection at the next clock, and the selector 41 outputs the instruction code IR. The Nop command is output as. At the next clock, the instruction code at the jump destination is output from the synchronous memory 10. At this time, since the program control instruction is a non instruction, the instruction code selection register 55 is set for selection of the output of the synchronous memory 10, the output of the synchronous memory 10 is output via the selector 41, and the jump destination It becomes an instruction code. In this way, the Nop instruction is automatically inserted between the Push instruction and the instruction at the jump destination.

Pop of 67 is a return instruction, the program control instruction becomes a pop instruction, and the value PC of the program counter 30 saved in the STK1 register is set in the address register 13 and the program counter 30 of the synchronous memory 10. It In the case of a pop instruction, the combination circuit 47 outputs the output IR of the next selector 41.
Nop instruction is selected as, and the instruction code selection register 55 is set for Nop selection at the next clock,
As a result, the selector 41 outputs the instruction code IR
p command is output. At the next clock, the instruction code of the save destination is output from the synchronous memory 10. At this time, since the program control instruction is the non instruction, the instruction code selection register 55 is set for selecting the output of the synchronous memory 10, and the output of the synchronous memory 10 is changed to the selector 4
It is output via 1 and becomes the instruction code of the save destination. In this way, the Nop instruction is automatically inserted between the pop instruction and the save destination instruction.

BP1 at 68 indicates the operation when the break point is established. At this time, the combination circuit 47 selects BP1 as the output of the next selector 41,
At the next clock, the instruction code selection register 55 is set for the selection of BP1, so that the instruction code BP1 set in the breakpoint register group 26 becomes IR.
It is replaced with 17 and output as a new instruction code IR via the selector 41.

BP2 at 69 indicates the operation when the break point is established. At this time, BP2 is selected as the output of the next selector 41 by the combination circuit 47, and the instruction code selection register 55 is set to BP2 at the next clock.
The instruction code B set for the selection of 2 and set in the break point register group 26 from the selector 41.
P2 is replaced with IR20 and output as a new instruction code via the selector 41. If the program control instruction at this time is a jump instruction, the selector 4
The address on the instruction code IR output by 1 is set in the address register 13 and the program counter 30 of the synchronous memory 10. In the case of the jump instruction, the combination circuit 47 selects the Nop instruction as the output of the next selector 41, the instruction code selection register 55 is set for the Nop selection at the next clock, and the selector 41 outputs the instruction code IR. The Nop command is output as. At the next clock, the instruction code at the jump destination is output from the synchronous memory 10. At this time, since the program control instruction is the non instruction, the instruction code selection register 55 is set for selecting the output of the synchronous memory 10, the output of the synchronous memory 10 is output via the selector 41, and the instruction of the jump destination is set. It becomes a code. In this way, the Nop instruction is automatically inserted between the jump instruction and the jump destination instruction.

As described above, in the present embodiment, when the asynchronous memory is changed to the synchronous memory, when the program developed for the asynchronous memory is executed, the Nop instruction is automatically executed by the jump or the subroutine instruction. Since, is inserted, a program developed for asynchronous memory can be used as it is without modification.

Further, since the instruction code selection register 55 is used, it is equivalent to the instruction code register 40 used in the computer control circuits of FIGS. 7, 13 and 18.
The instruction code synchronized with the clock can be obtained.

[0096]

As described above, according to the present invention, when the asynchronous memory is changed to the synchronous memory, the program developed for the asynchronous memory can be used without being changed. No development cost is required.

Normally, when the asynchronous memory is changed to the synchronous memory, the capacity of the program increases because the instruction such as Nop is added for the timing adjustment. However, since the program capacity does not change in the present invention, the memory increases. There is no increase in chip cost.

Further, the use of the synchronous memory simplifies the timing constraint, and when the process is miniaturized,
Since the process can be easily changed, the chip cost can be reduced by reducing the chip area in the same circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a computer control circuit using a synchronous memory according to an embodiment of the present invention.

FIG. 2 is a selector 41 for selecting an instruction code in the circuit of FIG.
3 is an explanatory diagram of a table of FIG.

FIG. 3 is an explanatory diagram of a table of a program counter selector 31 of the circuit of FIG.

4 is an explanatory diagram of a stack state transition table of a stack register group 28 in FIG.

5 is a timing diagram of the operation of the circuit of FIG.

6 is a timing diagram of the operation of the circuit of FIG.

FIG. 7 is a circuit diagram of a computer control circuit using a conventional asynchronous memory.

8 is an explanatory diagram of a table of an instruction code register selector of the circuit of FIG.

9 is an explanatory diagram of a table of address selectors of the circuit of FIG.

10 is a timing diagram of the operation of the circuit of FIG.

11 is a timing diagram of the operation of the circuit of FIG.

12 is an explanatory diagram of a program for the circuit of FIG.

FIG. 13 is a circuit diagram of a conventional synchronous access type computer control circuit.

14 is an explanatory diagram of a table of a program count selector of the circuit of FIG.

FIG. 15 is a timing diagram of the operation of the circuit of FIG.

16 is a timing diagram of the operation of the circuit of FIG.

17 is an explanatory diagram of a program for the circuit of FIG.

FIG. 18 is a circuit diagram of a computer control circuit using a conventional synchronous memory.

19 is an explanatory diagram of a program for the circuit in FIG.

20 is a timing diagram of the operation of the circuit of FIG.

21 is a timing diagram of the operation of the circuit of FIG.

22 is a timing diagram of the operation of the circuit of FIG.

[Explanation of symbols]

10: Synchronous memory, 11: Asynchronous memory, 12: Input data register, 13: Address register, 15: Output data register, 20: Control circuit, 21: Data register, 22: Address register, 23: Address switching selector, 25: Start control register, 26: Breakpoint register group, 28: Stack instruction register group, 30: Program counter, 31: Synchronous memory address and program counter selector, 3
2: address selector, 33: program counter selector, 34, 35: program counter selector, 39: adder, 40: instruction code register, 41:
Instruction code selection selector, 42: instruction code register selector, 45: comparator, 46, 47, 48: combinational circuit, 50: latch, 55: instruction code selection register.

Claims (3)

[Claims] 1. A computer control circuit using a synchronous memory, comprising: an output of a latch holding an output instruction code; an instruction code output from the synchronous memory; a Nop instruction code; and an instruction code generated at a breakpoint. A selector for selecting one of the selectors, and a register for controlling a selecting operation of the selector. The selector selects the Nop instruction when the instruction code output from the synchronous memory is a jump instruction. It is controlled so that the code is selected and output, the output of the latch is selected and output in the case of the Wait instruction, and the instruction code of the breakpoint is selected and output when the breakpoint condition is satisfied. Characterized computer control circuit. 2. The computer control circuit according to claim 1, wherein the register holds the selection state of the selector for one clock period. 3. The computer control circuit according to claim 1, further comprising a program counter controlled to have the same value as an address register built in the synchronous memory.