JP2003110414A - Power-on reset circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably reset a circuit even in the event of chattering or short-time interruption or slow switching on-off of a power source. SOLUTION: The power-on reset circuit having a signal inversion circuit controlled by a terminal voltage of a capacitor chargeable by a power source resets a circuit upon the output of the signal inversion circuit, as the power source is switched on and off. It comprises a discharge circuit for removing charges stored in the capacitor when the power source goes down from a high level to a low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-on reset circuit which is mounted on an LSI such as a CMOS circuit and outputs a reset signal when the power is turned on to reset the internal circuit of the LSI.

[0002]

2. Description of the Related Art FIG. 10 shows a configuration example of a conventional power-on reset circuit. Conventional power-on reset circuit 10
Is a charging circuit 1 formed by connecting a series circuit of a P-type MOS transistor P00 having a gate connected to GND and a capacitor C0 between a power supply VDD and a ground GND, and a series connection of a P-type MOS transistor P01 and an N-type MOS transistor N01. The circuit is connected between VDD and GND, and the signal inversion circuit 2 is formed by connecting the gates of these transistors P01 and N01 to the connection point of the P-type MOS transistor P00 and the capacitor C0.

At this time, the input voltage of the signal inverting circuit 2 is set to rs.
t0 (terminal voltage of capacitor C0), output RESET
When set to 0, RESET0 is supplied to the internal circuit (not shown) of the LSI as a reset signal or a reset release signal. However, the P-type MOS transistor P00 is used as a resistor and may be composed of a resistance element.

The operation of the power-on reset circuit 10 shown in FIG. 10 will be briefly described with reference to FIG.
As shown in FIG. 11A, the power-on reset circuit 1
0 when the power VDD is supplied at time t0, the capacitor C
The terminal voltage rst0 of 0 rises and is charged according to the time constant CR. As shown in FIG. 11B, the signal inverting circuit 2 outputs a reset signal (RESET0 is at a high level) until rst0 exceeds the threshold voltage Vthc of the signal inverting circuit 2 to initialize the internal circuit of the LSI. To do. After the rst0 voltage exceeds Vthc, the signal inversion circuit 2 outputs the reset release signal (RESET0 is low level).
Is output to cancel the initialization of the internal circuit.

[0005]

[Problems to be Solved by the Invention]
As shown in the period B of (a), when the supply of the power supply VDD is stopped (VDD becomes the ground voltage GND level) and the process of supplying the power again sharply switches, the reset operation can be performed again. Sometimes there is not.

That is, even if the supply of the power supply VDD is stopped once the capacitor C0 is sufficiently charged, the electric charge of the capacitor C0 is not fully discharged and the power supply VDD is
When the supply stop period is short, the rst0 voltage is the threshold voltage Vthc of the signal inverting circuit 2 as shown in FIG.
Does not fall below.

Therefore, the power-on reset circuit 10 cannot reset the internal circuit because the RESET0 signal does not go high as shown in FIG. 11 (b). Therefore, when the stop period of the power supply VDD is short as described above, The circuit will not be reset again.

FIG. 12 shows an example of a case where the power supply voltage VDD supplied to the power-on reset circuit rises and falls slowly. Also in this case, as shown in FIG. 12A, when the power is first turned on, as shown in FIG. 12B, RESET0 becomes high level to reset the internal circuit, and then the rst0 voltage becomes the signal. When the threshold voltage Vthc of the inverting circuit 2 is exceeded, the reset signal (RESET0 is at high level) that was initially issued is released. After that, when the power supply voltage VDD is slowly turned on and off,
The rst0 voltage is the threshold value voltage Vthc for the same reason as above.
Since the following does not occur, the RESET0 signal does not go high, and the internal circuit of the LSI is not reset.

Therefore, in the conventional power-on reset circuit 10, in order to reset the internal circuit of the LSI again, the stop period of the power supply VDD needs to be long to some extent. Therefore, there is a problem that the internal circuit cannot be reset and the internal circuit cannot be initialized at the time of chattering of the power source VDD or switching on / off of the power source for a short time.

The present invention has been made in order to solve the above-mentioned conventional problems, and its object is to provide a circuit even when the power supply chatters or shuts off for a short time or when the power supply is slowly turned on or off. It is to provide a power-on reset circuit capable of surely resetting.

[0011]

In order to achieve the above object, a first means for solving the problem has a signal inverting circuit controlled by a terminal voltage of a first capacitor charged by a power source, In a power-on reset circuit that resets the circuit by the output of the signal inverting circuit when the power supply is turned on and off, when the power supply drops from a high level to a low level and falls below a predetermined voltage, the charge stored in the capacitor is extracted to the power supply side. A discharge circuit is provided.

The second means has a signal inverting circuit controlled by the terminal voltage of the first capacitor charged by the power supply, and resets the circuit by the output of the signal inverting circuit when the power supply is turned on and off. In the on-reset circuit, a series circuit of a diode, a first transistor, and a second transistor is connected between a power line and a ground line, and the gates of the first and second transistors are commonly used. A second capacitor connected between a connection point between the diode and the first transistor and a ground line, and a gate connected to a connection point between the first transistor and the second transistor. 3 transistor is connected between the power supply side terminal of the first capacitor and the ground line,
The polarity of the first transistor is different from the polarities of the second and third transistors.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration according to the first embodiment of the power-on reset circuit of the present invention. However, the same parts as those of the conventional example will be described with the same reference numerals.

The power-on reset circuit of this example comprises a power-on reset circuit section 20 and a discharge circuit section 30. The power-on reset circuit section 20 has a gate
A charging circuit 1 in which a P-type MOS transistor P00 connected to ND and a capacitor C0 are connected in series between a power supply VDD and a ground GND, a P-type MOS transistor P01 and N.
Type MOS transistor N01 is connected in series between power supply VDD and GND, and the gates of these transistors P01 and N01 are connected to P type MOS transistor P00 and capacitor C0.
Signal inversion circuit (inverter) 2 connected to the connection point of
Composed of.

With this configuration, the input voltage of the signal inverting circuit 2 is rst1 (terminal voltage of the capacitor C0), and the output is RES.
ET1 is supplied to an internal circuit (not shown) of the LSI as a reset signal or a reset release signal. However, the P-type MOS transistor P00 is used as a resistor and may be composed of a resistance element.

The discharge circuit section 30 includes diodes D11 and P.
Type MOS transistor P11 and N type MOS transistor N11 are connected in series between the power supply VDD and the ground GND, and the capacitor C1 is connected to the diode D11 and the P type MOS.
It is configured by being connected between the connection point of the transistor P11 and GND, and further includes a P-type MOS transistor P11 and an N-type MO.
An N-type MOS transistor N12 in which a gate is connected to a connection point of the S transistor N11, a source is connected to GND, and a drain is connected to a connection point between the P-type MOS transistor P00 and the capacitor C0 in the power-on reset circuit section 20.
have.

Next, the operation of this embodiment will be described.
First, in the power-on reset circuit of this example, the power supply voltage VDD
2A, the power supply VDD rises at time t0 in FIG. 2A, so that the gates of the P-type and N-type MOS transistors P11 and N11 of the discharge circuit unit 30 become high level.
The P-type MOS transistor P11 is off and the N-type MOS transistor N11 is on. As a result, the capacitor C1 is charged with electric charge via the diode D11.
At this time, the terminal voltage VDDP1 of the capacitor C1 is equal to the power source V
DD and VF (the forward threshold voltage of the PN junction of the diode D11, which is about 0.5 in the standard CMOS process).
[V]. Between).

At this time, as described above, the N-type MOS
The transistor N11 is on, and INVOUT1 is at the ground voltage GND, that is, low level. As a result, the gate voltage of the N-type MOS transistor N12 is at low level, and this transistor N12 is in the off state.

On the other hand, when the power VDD is turned on, there is no accumulated charge in the capacitor C0 of the power-on reset circuit section 20, so the terminal voltage rst1 of the capacitor C0 is at a low level and the threshold value Vthc of the signal inverting circuit 2 is sufficient. It is below the limit. As a result, similarly to the conventional case, the output RESET1 of the signal inverting circuit 2 becomes high level as shown in FIG. 2A, and the reset signal is output to the internal circuit (not shown) of the LSI.

After that, as shown in FIG. 2B, the terminal voltage rst1 of the capacitor C0 changes to the threshold value V of the signal inverting circuit 2.
If it exceeds thc, the output of the signal inversion circuit 2 RESET1
Becomes low level as shown in FIG. 2A, the reset release signal is output to the internal circuit, and the initialization is completed.

Next, as shown in FIG. 2A, the power supply VDD
When the signal becomes GND for the period B, the gates of the P-type MOS transistor P11 and the N-type MOS transistor N11 become low level, the P-type MOS transistor P11 turns on, and the N-type MOS transistor N11 turns off. Therefore, the charge accumulated in the capacitor C1 is applied to the gate of the N-type MOS transistor N12, and VDDP1 = INVOU
Since it becomes T1, this N-type MOS transistor N12 is turned on. When the N-type MOS transistor N12 is turned on, the charge accumulated in the capacitor C0 of the charging circuit 1 becomes N.
It is discharged to the GND side through the MOS transistor N12.

As a result, the P-type MOS of the signal inverting circuit 2 is
The common gate voltage rst1 of the transistor P01 and the N-type MOS transistor N01 is as shown in FIG.
It rapidly goes to the low level, and the threshold value Vth of the signal inversion circuit 2
less than c. Therefore, the P-type MOS transistor P01 is turned on, the N-type MOS transistor N01 is turned off, the output of the signal inversion circuit 2 is inverted, and its output RESET1.
Becomes high level as shown in FIG. 2B, and the reset signal is output to the internal circuit.

After that, when the power supply voltage lowered to GND in the period B rises again to the original power supply voltage value, the P-type MOS is
Since the transistor P11 is turned off and the N-type MOS transistor N12 is turned on, INVOUT1 becomes low level and the N-type MOS transistor N12 is turned off. At the same time, the capacitor C0 is rapidly charged through the P-type MOS transistor P00 and rst1 becomes high level, so that the P-type MOS transistor P01 is turned off and the N-type MOS transistor N01 is turned on, and the output of the signal inversion circuit 2 is output. Is inverted and its output RESET1 is shown in FIG.
As shown in (b), it goes low and the reset release signal is output to the internal circuit.

FIG. 2C shows the terminal voltage VDDP1 of the capacitor C1 and the N-type M of the discharge circuit section 30 during the above operation.
FIG. 9 is a waveform diagram showing a change over time in the gate voltage INVOUT1 of the OS transistor N12. At power on, power VD
When D rises, since the P-type MOS transistor P11 is off and the N-type MOS transistor N11 is on, INVOUT1 is low level (GND level), and the terminal voltage VDDP1 of the capacitor C1 is the capacitor C1 passing through the diode D11. Rises with the charging to and saturates at a voltage of approximately VDD-VF.

Next, when the power supply VDD drops during the period B, P
Since the type MOS transistor P11 is turned on and the N type MOS transistor N11 is turned off, INVOUT1 which is the gate voltage of the N type MOS transistor N12 becomes the terminal voltage of the capacitor C1 and sharply rises to VDDP1. At this time, as described above, the N-type MOS transistor N
12 is turned on, and the electric charge of the capacitor C0 of the charging circuit 1 is extracted.

After that, when the power supply VDD rises, the P-type M
The OS transistor P11 is off, the N-type MOS transistor N11 is on, and the INVOUT1 returns to the low level (GND level).

Even if the charge stored in the capacitor C0 is applied to the gate of the N-type MOS transistor N12 during the period B, its terminal voltage is VDDP1 because it has sufficient capacity.
Hardly changes.

FIG. 3 is a waveform diagram for explaining the operation of the power-on reset circuit of this example when the power supply VDD slowly turns on and off. When the power is turned on, as shown in FIG.
When the power supply VDD slowly rises, at this time, since there is no charge accumulated in the capacitor C0, the terminal voltage rst1 of the capacitor C0 is initially at the low level, which is sufficiently lower than the threshold value Vthc of the signal inverting circuit 2. . As a result, the P-type MOS transistor P01 is turned on and the N-type MOS transistor N01 is turned off, and the output of the signal inverting circuit 2 is RESET1 as shown in FIG.
, And a triangular reset signal is output to the internal circuit.

After that, when the power supply VDD further rises, the terminal voltage of the capacitor C0 becomes rs as shown in FIG. 3 (b).
Since t1 exceeds the threshold voltage Vthc of the signal inverting circuit 2, the output RESET1 of the signal inverting circuit 2 is inverted and becomes low level, and the reset release signal is output to the internal circuit.

After that, as shown in FIG.
When the power supply VDD drops to some extent when DD is slowly turned off and on, the P-type MOS transistor P11 of the discharge circuit unit 20 is turned on and the N-type MOS transistor N11 is turned off. Is applied to the gate of the N-type MOS transistor N12 to turn on the N-type MOS transistor N12. Therefore, the charge charged in the capacitor C0 is the N-type MOS transistor N12.
Is rapidly discharged to GND, and then decreases, as shown in FIG. 3 (b).
As shown in, the terminal voltage rst1 of the capacitor C0 falls below the threshold voltage Vthc of the signal inverting circuit 2.

As a result, as shown in FIG. 3B, the output RESET1 of the signal inverting circuit 2 is inverted to a high level, and the reset signal is output to the internal circuit as the power supply VDD rises. When the rise of the power supply VDD is further increased, the terminal voltage of the capacitor C0 exceeds the threshold voltage Vthc of the signal inverting circuit 2 by rst1, the output RESET1 is inverted and becomes low level, and the reset release signal is output to the internal circuit. .

FIG. 3C shows the terminal voltage VDDP1 of the capacitor C1 and the N-type M of the discharge circuit section 30 during the above operation.
FIG. 9 is a waveform diagram showing a change over time in the gate voltage INVOUT1 of the OS transistor N12. At power on, power VD
When D rises, since the P-type MOS transistor P11 is off and the N-type MOS transistor N11 is on, INVOUT1 is low level (GND level), and the terminal voltage VDDP1 of the capacitor C1 is the capacitor C1 passing through the diode D11. However, the way of the rise is slower than that shown in FIG. 2 (c).

As the power supply VDD drops during the period B, the P-type M
Since the OS transistor P11 is on and the N-type MOS transistor N11 is off, the N-type MOS transistor N
INVOUT1 which is the gate voltage of 12 sharply rises to VDDP1. At this time, as described above, the N-type MOS
The transistor N12 is turned on, the charge of the capacitor C0 of the charging circuit 1 is extracted, the output of the signal inverting circuit 2 is inverted, RESET1 becomes high level, and the reset signal is output to the internal circuit.

After that, when the power supply VDD rises again, P
The type MOS transistor P11 is turned off, the N type MOS transistor N11 is turned on, and the INVOUT1 returns to the low level (GND level).

In the period B, even if the charge stored in the capacitor C0 is applied to the gate of the N-type MOS transistor N12 for a relatively long period of time, there is sufficient capacitance, so that the terminal voltage V
DDP1 is only slightly lowered.

According to the present embodiment, by providing the discharging circuit section 30 which draws out the charge charged in the capacitor C0 of the power-on reset circuit section 20 when the power supply VDD is lowered, the power supply VDD is changed from the stable supply state to the GND. Even when the process of returning to the original state after being lowered to the vicinity is switched abruptly or slowly, it is possible to reliably output the reset signal having a pulse width sufficient to initialize the internal circuit of the LSI. , The internal circuit can be initialized even when the power supply process is repeatedly switched in a short time (chattering etc.),
It is possible to ensure stable operation.

Further, since the additional portion from the conventional example is small, it is possible to prevent the pattern area of the power-on reset circuit from increasing. Furthermore, since the N-type MOS transistor N12 is turned off when the power is turned on,
Even if the discharge circuit unit 30 is provided, the power-on reset circuit unit 2
0 has no adverse effect, the same characteristics as the conventional one can be obtained, and the operation at a low power supply voltage is possible.

FIG. 4 is a block diagram showing the configuration of the power-on reset circuit according to the second embodiment of the present invention. However, the same parts as those of the first embodiment shown in FIG. The power-on reset circuit of this example is different from the first embodiment in that the diode D11 used in the first embodiment of the discharge circuit unit 30 is replaced with an N-type MOS transistor N21, and other configurations are exactly the same. Is.

As a result, the voltage of the terminal voltage VDDP1 of the capacitor C1 at the time of charging becomes VDD-VthN, and a lower voltage operation is possible than in the first embodiment. The circuit operation is the same as that of the first embodiment and has the same effect as that of the first embodiment. Particularly, in this example, since the diode is not used, it can be manufactured by a standard CMOS process.

FIG. 5 is a block diagram showing the configuration of the power-on reset circuit according to the third embodiment of the present invention. However, the same parts as those of the first embodiment shown in FIG.

In the power-on reset circuit of this example, the diode D11 used in the first embodiment of the discharge circuit section 30 is replaced with a P-type MOS transistor P31 (hereinafter referred to as P31), which is a P-type MOS transistor. P31
The gate, the drain, and the bulk are connected.

As a result, the voltage of the terminal voltage VDDP1 of the capacitor C1 at the time of charging becomes VDD-VF. VF
Is the forward threshold voltage of the parasitic diode generated between the source and the bulk of P31 or the lower voltage of the threshold voltage of the P-type MOS transistor P31, which is lower than that of the first embodiment. is there. The circuit operation is the same as that of the first embodiment and has the same effect as that of the first embodiment. Particularly, in this example, since the diode is not used, it can be manufactured by a standard CMOS process.

FIG. 6 is a block diagram showing the configuration of the power-on reset circuit according to the fourth embodiment of the present invention. However, the same parts as those of the first embodiment shown in FIG. The power-on reset circuit of the present invention is composed of the power-on reset circuit section 20 and the discharge circuit section 30, and has substantially the same configuration as that of the first embodiment. The difference is that the discharge circuit unit 30
N-type MOS transistor N12 is inserted between the connection point of the P-type MOS transistor P00 of the power-on reset circuit unit 20 and the capacitor C0 and the power supply VDD line, and the gate thereof is the capacitor C1 and the diode D1.
1 is connected to the connection point.

Next, the operation of this embodiment will be described.
In the power-on reset circuit of the present invention, when the power VDD is supplied (time t0) as shown in FIG. 7A, the capacitor C1 is charged through the diode D11, and its terminal voltage VDDP1 is VDD− It rises to the voltage of VF. When this power is turned on, the terminal voltage VD of the capacitor C1
Since DP1 is at the low level, there is a voltage difference between the gate of the N-type MOS transistor N12 and the power supply VDD line, and the N-type MOS transistor N12 is momentarily turned on. As a result, the capacitor C0 of the charging circuit 1 is charged with electric charges via the N-type MOS transistor N12.

After that, the terminal voltage VDD of the capacitor C1
When P1 rises, there is no voltage difference between the gate of the N-type MOS transistor N12 and the power VDD line,
The N-type MOS transistor N12 is turned off, and the capacitor C0 has a P-type MOS transistor P00.
The electric charge is charged via.

The subsequent operation of the power-on reset circuit section 20 is the same as that of the first embodiment. As shown in FIG. 7B, when the power is turned on, RESET1 is at the high level,
The reset signal is output to the internal circuit of the LSI. After that, when the terminal voltage rst1 of the capacitor C0 exceeds the threshold value of the signal inverting circuit 2, RESET1 becomes low level, and the reset release signal is output to the internal circuit.

Next, as shown in FIG. 7A, when the power supply VDD drops at the beginning of the period B, the terminal voltage VDDP1 of the capacitor C1 is at the high level and the power supply VDD line is at the low level. A voltage difference occurs between the gate of the MOS transistor N12 and the power supply VDD line. As a result, the N-type MOS transistor N12 is turned on, and the charge stored in the capacitor C0 of the charging circuit 1 is discharged to the power supply VDD line via the N-type MOS transistor N12.

As a result, as shown in FIG. 7B, the terminal voltage rst1 of the capacitor C0 falls below the threshold value of the inverting circuit 2, so that the output of the inverting circuit 2 is inverted and RESET1 is set.
Goes high, and a reset signal is output to the internal circuit of the LSI. After that, when the power supply VDD rises from the GND level, as shown in FIG. 7B, the capacitor C0
Terminal voltage rst1 of the inverting circuit 2 exceeds the threshold of the inverting circuit 2
ET1 goes low, and the signal inversion circuit 2 outputs a reset release signal to the internal circuit.

FIG. 7C is a waveform diagram showing the change over time of the terminal voltage VDDP1 of the capacitor C1 of the discharge circuit section 30 during the above operation. When the power supply VDD rises when the power is turned on, initially the terminal voltage VDDT1 of the capacitor C1
Is a low level (GND level), but the P-type MOS transistor P11 is off and the N-type MOS transistor N is
11 is on, the terminal voltage VD of the capacitor C1
DP1 rises as the capacitor C1 is charged through the diode D11 and saturates at a voltage of approximately VDD-VF.

Similarly, as shown in FIG. 8A, even when the falling edge and the rising edge of the power source are slow, as shown in FIG.
As shown in (b), it is possible to output a reset signal having a sufficient pulse width and a subsequent reset release signal, and it is possible to initialize the internal circuit. Also, FIG.
As shown in (c), the terminal voltage VDDP of the capacitor C1
No. 1 rises slowly when the power is turned on, and thereafter maintains a substantially constant voltage.

According to the present embodiment, the diode D11 and the N-type MOS transistor N12 are turned on even when the power supply chatters, the power is turned on or off for a short time, or the power is turned on or off when the power supply falls or the rising edge is slow. It is possible to operate with a possible low power supply voltage VF + VthN (VthN is the threshold voltage of the N-type MOS transistor N12).
The same effect as the above embodiment is obtained. In particular, since the electric charge of the capacitor C0 can be discharged to the power supply side as in this example,
This is effective when other circuits are affected by draining the charges to the ground side systematically.

FIG. 9 is a block diagram showing the configuration of the power-on reset circuit according to the fifth embodiment of the present invention. However, the same parts as those of the fourth embodiment shown in FIG. The difference between this example and the fourth embodiment is that the diode D11 used in the fourth embodiment of the discharge circuit unit 30 is replaced with a P-type MOS transistor P31. The drain and the bulk are connected. At this time, the voltage of the terminal voltage VDDP1 of the capacitor C1 is V
It becomes DD-VF and can be operated at a lower power supply voltage than the fourth embodiment. The other circuit configuration is the same as that of the fourth embodiment, and similar effects can be obtained. Especially, in this example, since a diode is not used, a standard CM is used.
It can be manufactured by the OS process.

The same effect can be obtained even if the diode D11 is replaced with an N-type MOS transistor.

Further, the present invention is not limited to the above-mentioned embodiments, and can be carried out in various other modes in specific configurations, functions, actions and effects without departing from the scope of the invention. .

[0055]

As described in detail above, according to the present invention, when the power source is lowered from the high level to the low level,
By providing the discharging circuit for extracting the charged electric charge of the capacitor, the circuit can be surely reset even when the power supply chatters, the power is cut off for a short time, or the power is slowly turned on and off.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration according to a first embodiment of a power-on reset circuit of the present invention.

FIG. 2 is a waveform diagram for explaining a reset operation when the power supply of the circuit shown in FIG. 1 is sharply turned on / off.

FIG. 3 is a waveform diagram for explaining a reset operation when slowly turning on / off the power supply of the circuit shown in FIG.

FIG. 4 is a block diagram showing a configuration of a power-on reset circuit according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a power-on reset circuit according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing a configuration according to a fourth exemplary embodiment of a power-on reset circuit of the present invention.

7 is a waveform diagram for explaining a reset operation when the power supply of the circuit shown in FIG. 6 is turned on and off abruptly.

FIG. 8 is a waveform diagram for explaining a reset operation when the power supply of the circuit shown in FIG. 6 is slowly turned on / off.

FIG. 9 is a block diagram showing a configuration of a power-on reset circuit according to a fifth embodiment of the present invention.

FIG. 10 is a diagram showing a configuration example of a conventional power-on reset circuit.

FIG. 11 is a waveform diagram illustrating a reset operation when the power supply of the conventional circuit shown in FIG. 10 is turned on and off abruptly.

FIG. 12 is a waveform diagram for explaining a reset operation when slowly turning on / off the power supply of the conventional circuit shown in FIG.

[Explanation of symbols]

1 Charge Circuit 2 Signal Inversion Circuit 20 Power-on Reset Circuit Section 30 Discharge Circuit Section C0, C1 Capacitor D11 Diodes N01, N11, N12, N21 N-type MOS Transistors P00, P01, P11, P31 P-type MOS Transistor

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masatomo Tanaka             25-1 Honmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa             Toshiba Microelectronics Co., Ltd. (72) Inventor Hiroyuki Suwabe             25-1 Honmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa             Toshiba Microelectronics Co., Ltd. F term (reference) 5B054 BB01 DD03                 5J032 AA05 AB02 AC14                 5J055 AX57 AX66 BX16 BX42 CX23                       DX22 DX56 DX72 DX83 EX07                       EX21 EY10 EY12 EY21 EZ00                       EZ07 FX12 FX17 FX35 GX02                       GX04

Claims (5)

[Claims] 1. A power-on reset circuit having a signal inverting circuit controlled by the terminal voltage of a first capacitor charged by a power supply, and resetting the circuit by the output of the signal inverting circuit when the power supply is turned on and off. A power-on reset circuit comprising: a discharge circuit that draws out the charge stored in the capacitor to the power supply side when the power supply drops from a high level to a low level and falls below a predetermined voltage. 2. The discharge circuit connects a series circuit of a diode, a first transistor, and a second transistor between a power supply line and a ground line, and connects the gates of the first and second transistors to each other. Commonly connected to a power supply line, a second capacitor connected between a connection point of the diode and the first transistor and a ground line, and a gate connected to a connection point of the diode and the first transistor. 3rd connected
2. The transistor according to claim 1 is connected between a power supply side terminal of the first capacitor and a power supply line, and the polarity of the first transistor is different from the polarities of the second and third transistors. The power-on reset circuit described in. 3. A power-on reset circuit having a signal inverting circuit controlled by the terminal voltage of a first capacitor charged by a power source, and resetting the circuit by the output of the signal inverting circuit when the power source is turned on and off. Connecting a series circuit of a diode, a first transistor and a second transistor between a power supply line and a ground line, and connecting the gates of the first and second transistors in common to the power supply line, A second transistor is connected between a connection point between the diode and the first transistor and a ground line, and a third transistor whose gate is connected to a connection point between the first transistor and the second transistor. The first
The power-on reset circuit is connected between the power supply side terminal of the capacitor and the ground line, and the polarity of the first transistor is different from the polarities of the second and third transistors. 4. The power-on reset circuit according to claim 2, wherein a fourth transistor having the same polarity as the first transistor is used instead of the diode. 5. The power-on reset circuit according to claim 2, wherein a fifth transistor having the same polarity as the second transistor is used instead of the diode.