JP2003110019A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device of the structure where signal wires are allocated in the horizontal and vertical directions to improve reliability thereof. SOLUTION: The horizontal signal lines 3 and the vertical signal lines 5 are formed on the first inter-layer insulation film 1. At the crossing areas of both signal lines 3, 5, one signal line is patterned not to be in contact with the other signal line. The second inter-layer insulation film 7 having the via hole 9 is formed on the first inter-layer insulation film 1 corresponding to the end portions of the signal lines 3, 5 at the crossing areas. An upper wiring layer 11 is formed on the second inter-layer insulation film 7 and within the via hole 9 in order to electrically connect the signal line 3 or 5 which is intermittently formed at the crossing areas. Since both signal lines 3, 5 are formed on the first inter-layer insulation film 1 having less stepped areas, it is possible to make it difficult to generate disconnection and fluctuation in the final process. Therefore, stable signal line may be provided and reliability of signal line can also be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a semiconductor device having a structure in which signal lines are arranged vertically and horizontally. In this specification, a signal line refers to a wiring layer that intersects vertically and horizontally, such as a data line, a scanning line, or a capacitor line.

[0002]

2. Description of the Related Art In a semiconductor device having a structure in which wiring layers for signal lines are regularly arranged vertically and horizontally, as represented by a large sensor or a liquid crystal device, for example, in order to specify the position of a sensor or a pixel, For example, the signal line is divided into an upper layer and a lower layer in the horizontal direction (X direction) and the vertical direction (Y direction) (for example, see Japanese Patent Laid-Open No. 2000-81636).

FIG. 5 is a diagram showing a wiring layer structure of a conventional large-sized sensor. (A) is a plan view and (B) is A of (A).
FIG. 6C is a cross-sectional view taken along the line -A ', and FIG. 6C is a cross-sectional view taken along the line BB' in FIG. In FIG. 5, the structure is simplified and a detailed illustration of the light receiving element region including the control transistor is omitted, and only one signal line in each of the horizontal direction and the vertical direction is shown with respect to the light receiving element region.

A first interlayer insulating film 31 made of a silicon oxide film is formed on a silicon substrate (not shown).
A plurality of horizontal signal lines 33 are formed on the first interlayer insulating film 31 in parallel with each other in the X direction (lateral direction). A second interlayer insulating film 35 is formed on the first interlayer insulating film 31 and the horizontal signal line 33. A plurality of vertical signal lines 37 are formed on the second interlayer insulating film 35 in parallel with each other and in the Y direction (vertical direction) orthogonal to the horizontal signal lines 33. The vertical signal lines 37 are formed over the plurality of horizontal signal lines 33. A light receiving element (not shown) and a control transistor (not shown) are formed in a light receiving element region surrounded by the horizontal signal line 33 and the vertical signal line 37.

[0005]

The surface of the first interlayer insulating film 31 on which the lower horizontal signal line 33 is formed has relatively few steps, and the horizontal signal line 33 may have a disconnection due to the step. There are few concerns about narrow line width. However, the second interlayer insulating film 3 on which the vertical signal line 37 is formed
On the surface of 5, there is a step portion on the horizontal signal line 35 due to the horizontal signal line 35. Since the vertical signal line 37 formed on the surface of the second interlayer insulating film 35 is arranged so as to cross over the horizontal signal line 33, it is greatly affected by the step portion. Therefore, with respect to the vertical signal line 37, there is a concern about a change in shape such as a thin line width in the step portion or a disconnection, which lowers reliability.

[0006] Therefore, an object of the present invention is to provide a semiconductor device having a structure in which signal lines are arranged vertically and horizontally, which can improve the reliability of the signal lines.

[0007]

A semiconductor device according to the present invention is a semiconductor device having a structure in which signal lines are arranged vertically and horizontally, and the signal lines are formed in the same layer except the intersecting portions where they intersect with each other. It is formed by an existing wiring layer, and in the intersecting portion, one of the signal lines in the vertical direction or the horizontal direction is formed by the wiring layer existing in the same layer, and the other signal line is formed as a connection hole and It is electrically connected through another wiring layer formed in another layer.

With respect to the vertical and horizontal signal lines intersecting with each other, by forming the portions other than the intersecting portions by the wiring layers existing in the same layer, it becomes possible to form the signal lines in a lower layer, and it becomes difficult to be influenced by the step difference in the base. . Further, regarding the signal line, the portion affected by the base step is only in the vicinity of the intersecting portion, and compared to the case where the vertical signal line and the horizontal signal line are formed by separate wiring layers as in the conventional technique, The effect of reducing the overall step can be obtained. Therefore, it is possible to prevent the occurrence of defects such as disconnection and finish variation in the signal line, and it is possible to supply a stable signal line,
The reliability of the signal line can be improved.

In a semiconductor device having a long signal line such as a large sensor, when the vertical signal line and the horizontal signal line are formed by separate wiring layers as in the prior art, Since the parasitic capacitance values in the wiring layers of different layers are different, there is a problem in that there is a large difference in signal propagation delay time between the vertical signal line and the horizontal signal line. In the semiconductor device of the present invention, the vertical and horizontal signal lines are formed by the wiring layers existing in the same layer except the intersecting portion, so that the vertical and horizontal signal lines have substantially the same parasitic capacitance value. Therefore, it is possible to realize the simplification of the design for the estimation of the signal propagation delay time.

In addition, avoiding the formation of signal lines in the lowermost metal wiring layer, for example, the second metal wiring layer from the bottom is used to form a portion other than the intersection portion of the signal lines, and the intersection portion is connected more than that. By using the uppermost metal wiring layer, for example, the third metal wiring layer from the bottom, a certain distance can be secured between the signal line and the semiconductor substrate, and the parasitic capacitance in the signal line can be reduced.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, it is preferable that the another wiring layer is formed above a portion other than the intersection of the signal lines. As a result, most of the signal line can be formed in a lower layer, the influence of the step difference in the base can be reduced, and the reliability of the signal line can be improved.

In the present invention, it is preferable that the portion other than the intersecting portion of the signal lines is formed by the lowermost metal wiring layer. As a result, most of the signal line can be formed in a lower layer, the influence of the step difference in the base can be reduced, and the reliability of the signal line can be improved. However, the metal wiring layer in which a portion other than the crossing portion of the signal line is formed is not limited to the lowermost metal wiring layer, and the crossing portion of the signal line is formed by the second or more metal wiring layers from the bottom. Other parts may be formed. In this case, if there is no step on the surface of the base film in a region where a portion other than the intersection of the signal lines is formed, or if the step on the surface of the base film is small, it is difficult to cause problems such as disconnection and finish variation of the signal line. Therefore, a stable signal line can be supplied, and the reliability of the signal line can be improved.

In the present invention, it is preferable that the portion of the signal line electrically connected through the another wiring layer in which the connection hole exists has a wide line width. When forming the other wiring layer above the portion other than the crossing portion of the signal line, by forming the line width of the signal line in the portion where the connection hole exists, the insulating film formed in the upper layer It is possible to reduce the step difference at the intersecting portion, which in turn can reduce the step difference of another wiring layer formed in the upper layer.
This makes it possible to stabilize the connection between the signal line and another wiring layer.

In one aspect of the present invention, the signal line electrically connected through the another wiring layer is only the signal line in either the vertical direction or the horizontal direction. As a result, the circuit design is facilitated and the design efficiency can be improved.

In another aspect of the present invention, in the plurality of intersections existing in a matrix, vertical signal lines and horizontal signal lines are alternately electrically connected via the other wiring layers. ing. As a result, there is no long signal line, and it is possible to prevent formation defects such as thin line width and disconnection in the manufacturing process, especially for relatively thin signal lines, and to stabilize the manufacturing process and improve yield. it can.

[0016]

EXAMPLE FIG. 1 is a diagram showing a wiring layer structure of a large-sized sensor as one example, (A) is a plan view, (B) is a sectional view taken along the line AA ′ of (A), C) is B of (A)
It is a sectional view in the -B 'position. In FIG. 1, the structure is shown in a simplified manner, the detailed illustration of the light receiving element region including the control transistor is omitted, and only one signal line in each of the horizontal direction and the vertical direction is shown with respect to the light receiving element region.

A first interlayer insulating film 1 made of, for example, a silicon oxide film is formed on a silicon substrate (not shown). A plurality of horizontal signal lines 3 are formed in parallel with each other in the X direction (lateral direction) on the first interlayer insulating film 1, and a plurality of vertical signal lines 5 are parallel to each other and orthogonal to the horizontal signal lines 3. Is formed in the Y direction (vertical direction). At the intersection of the horizontal signal lines 3 and the vertical signal lines 5, one signal line is patterned so as not to contact the other signal line. Horizontal signal line 3 and vertical signal line 5
Are formed by the lowermost metal wiring layer. The region where the lowermost metal wiring layer is formed is on the same step of the first interlayer insulating film 1 or the region where the underlying step of the first interlayer insulating film 1 is small, and the film thickness and line width are uniform. The horizontal signal line 3 and the vertical signal line 5 are formed.

The horizontal signal line 3 is a crossing portion intersecting with the vertical signal line 5, and a portion formed intermittently with the vertical signal line 5 interposed therebetween and a portion formed continuously. With. The vertical signal line 5 has a portion that is intermittently formed and a portion that is continuously formed in the intersecting portion that intersects with the horizontal signal line 3 with the horizontal signal line 3 interposed therebetween. In the intersecting portions existing in a matrix, the intersecting portions in which the horizontal signal lines 3 are continuously formed and the intersecting portions in which the vertical signal lines 5 are continuously formed are alternately formed.

A second interlayer insulating film 7 made of, for example, a silicon oxide film is formed on the first interlayer insulating film 1, the horizontal signal line 3 and the vertical signal line 5. Via holes (connection holes) 9 are formed in the second interlayer insulating film 7 corresponding to the tips of the horizontal signal lines 3 and the vertical signal lines 5 which are intermittently formed at the intersection.

An upper wiring layer (another wiring layer) 11 is formed on the second interlayer insulating film 7 and in the via hole 9. The upper wiring layer 11 is electrically independently formed at each intersection, and electrically connects the horizontal signal line 3 or the vertical signal line 5 which is intermittently formed. A light receiving element region 13 is formed in a region surrounded by the horizontal signal lines 3 and the vertical signal lines 5.

In this embodiment, the horizontal signal lines 3 and the vertical signal lines 5 intersecting with each other are formed by the lowermost metal wiring layer so that the influence of the step difference of the underlying layer is suppressed. Further, the portion affected by the underlying step is only the upper wiring layer 11 at the intersecting portion, which is different from the case where the signal lines in the X direction and the signal lines in the Y direction are formed by different wiring layers as in the prior art. Thus, the effect of reducing the overall step difference can be obtained. Therefore, the horizontal signal line 3, the vertical signal line 5, and the upper wiring layer 11 can be prevented from having troubles such as disconnection and finish variation, and a stable signal line can be supplied, and the reliability of the signal line can be improved. Can be improved.

Further, since the horizontal signal line 3 and the vertical signal line 5 are formed by the wiring layers existing in the same layer, the parasitic capacitance value of both the horizontal signal line 3 and the vertical signal line 5 is formed. Can be made almost the same, which is effective for the signal propagation delay time. Further, since the horizontal signal line 3 and the vertical signal line 5 are formed by the lowermost metal wiring layer, the parasitic capacitance can be reduced,
It is effective for the signal propagation delay time.

Further, in a plurality of intersecting portions existing in a matrix, the horizontal signal lines 3 and the vertical signal lines 5 are electrically connected alternately via the upper wiring layer 11, so that they are biased in one direction. There is no need to run long signal lines. This makes it possible to prevent formation defects such as thin line widths and disconnections in the manufacturing process, especially for relatively thin signal lines, and to form the signal lines 3 and 5 in both directions with high accuracy, thus stabilizing the manufacturing process and reducing the number of steps. It is possible to improve the stay.

2A and 2B are views showing a wiring layer structure of a large-sized sensor as another embodiment. FIG. 2A is a plan view, FIG. 2B is a sectional view taken along the line AA 'in FIG. C) is B of (A)
It is a sectional view in the -B 'position. In FIG. 2, the structure is simplified and the detailed illustration of the light receiving element region including the control transistor is omitted. Only one signal line in each of the horizontal direction and the vertical direction is shown with respect to the light receiving element region. The same reference numerals are given to the parts that perform the same functions as in FIG.

A first interlayer insulating film 1 is formed on a silicon substrate (not shown). On the first interlayer insulating film 1, a plurality of horizontal signal lines 3 are formed in parallel with each other in the X direction, and a plurality of vertical signal lines 5 are formed in parallel with each other in the Y direction. At the intersection where the horizontal signal lines 3 and the vertical signal lines 5 intersect, the horizontal signal lines 3 are continuously formed and the vertical signal lines 5 are intermittently formed.

A second interlayer insulating film 7 is formed on the first interlayer insulating film 1, the horizontal signal line 3 and the vertical signal line 5. In the second interlayer insulating film 7, corresponding to the tip portion of the vertical signal line 5 which is intermittently formed at the intersection,
The via hole 9 is formed.

An upper wiring layer 11 is formed on the second interlayer insulating film 7 and in the via hole 9. The upper wiring layer 11 is electrically formed independently for each intersection, and electrically connects the vertical signal lines 5 that are intermittently formed. A light receiving element region 13 is formed in a region surrounded by the horizontal signal lines 3 and the vertical signal lines 5.

In this embodiment, at all intersections,
Since only the vertical signal lines 5 are electrically connected through the upper wiring layer 11, the circuit design is facilitated and the design efficiency can be improved. In this embodiment, only the vertical signal lines are electrically connected through the upper wiring layer, but the present invention is not limited to this, and only the horizontal signal lines are provided in another wiring layer, for example, You may make it electrically connected through an upper wiring layer. Even with such a configuration, the same effects as those of the embodiment shown in FIG. 2 can be obtained, the circuit design can be facilitated, and the design efficiency can be improved.

As in the embodiment shown in FIGS. 1 and 2, the signal lines intermittently formed at the intersection are electrically connected by another wiring layer above the portion other than the intersection of the signal lines. In this case, the shape of the signal line in the portion where the connection hole exists may have the same shape as that of the signal line. However, by forming the line width wide in that portion, the crossing of the insulating film formed in the upper layer thereof may occur. It is possible to reduce the level difference in the part,
As a result, it is possible to reduce the step difference of another wiring layer formed in the upper layer. An example thereof is shown in FIG.

FIG. 3 is a diagram showing an example of an intersecting portion of horizontal signal lines and vertical signal lines, (A) being a plan view,
(B) shows a sectional view taken along the line AA ′ in (A). Figure 1
The same reference numerals are given to the parts that perform the same functions as in FIG.

At the intersection shown in FIG. 3, the horizontal signal line 3
Are electrically connected via the upper wiring layer 11, and the vertical signal lines 5 are continuously formed. Horizontal signal line 3
The portion corresponding to the via hole 9 has a wide line width. Along with this, the step difference of the second interlayer insulating film 7 in the region where the upper wiring layer 11 is formed is reduced ((B)).
reference). As a result, the step difference of the upper wiring layer 11 is realized.

By forming the line width of the portion corresponding to the via hole 9 of the horizontal signal line 3 wide, the horizontal signal line 3 and the upper wiring layer 11 can be connected more reliably. Furthermore, by reducing the level difference in the upper wiring layer 11, stable connection can be achieved at the intersection.

In the embodiment shown in FIG. 3, the size of the portion where the horizontal signal line 3 is formed to have a large width is, for example, the positioning accuracy (alignment margin) when the horizontal signal line 3 and the upper wiring layer 11 are formed. ) Is taken into consideration, and the offset amount (see dimensions a and b in FIG. 3) is secured more than that, it is possible to keep the underlying state (surface shape of the second interlayer insulating film 7) uniform and stable. It is possible to form the connected connection.

FIG. 4 shows an example of the light receiving element region of a large-sized sensor to which the present invention is applied. (A) is a plan view, (B) is a sectional view taken along line BB ′ of (A), and (C) is A of (A).
A sectional view in the -A 'position is shown. The same reference numerals are given to the parts having the same functions as those in FIGS. Control transistors 17, 19 and a light receiving element 21 are formed in the light receiving element region 13 of the silicon substrate 15. Here, the light receiving element 21 is illustrated in a simplified manner. Control transistor 17,1
9 and the surface of the silicon substrate 15 in the region other than the light receiving element 21 is covered with a field oxide film 23 for element isolation.

The control transistor 17 is formed in a well 17w (not shown in (A)) formed in the silicon substrate 15, and has a source 17s and a drain 17d formed at intervals in the well 17w. In addition, the gate electrode 17g made of polysilicon is formed on the well 17w via a silicon oxide film (not shown). The control transistor 19 is formed in a well (not shown) formed in the silicon substrate 15 in a region different from the well 17w, and the source 19s and the drain 1 are formed in the well at intervals.
9d and silicon oxide film on the well (not shown)
Gate electrode 1 made of polysilicon formed through
It is composed of 9 g.

A first interlayer insulating film 1 is formed on the control transistors 17 and 19, the light receiving element 21 and the field oxide film 23. In the first interlayer insulating film 1, the contact hole 2 is formed on the gate electrode 17g of the control transistor 17.
5a, a contact hole 25b is formed on the drain 17d, a contact hole 25c is formed on the source 17s, a contact hole 25d is formed on the gate electrode 19g of the control transistor 19, a contact hole 25e is formed on the drain 19d, and a contact hole 25f is formed on the source 19s. And a contact hole 25g is formed on the light receiving element 21.

A first horizontal signal line 3a is formed on the first interlayer insulating film 1 and in the contact hole 25a.
On the first interlayer insulating film 1 and in the contact hole 25b,
A second horizontal signal line 3b is formed in parallel with the first horizontal signal line 3a. The vertical signal line 5 is formed in a direction orthogonal to the first horizontal signal line 3a and the second horizontal signal line 3b. The first horizontal signal line 3a and the second
At the intersection where the horizontal signal line 3b and the vertical signal line 5 intersect, the first horizontal signal line 3a and the second horizontal signal line 3b are formed intermittently.

A metal wiring 27a is formed on the first interlayer insulating film 1 and in the contact holes 25c and 25e. The metal wiring 27a electrically connects the source 17s of the control transistor 17 and the drain 19d of the control transistor 19. A metal wiring 27b is formed on the first interlayer insulating film 1 and in the contact hole 25f. The metal wiring 27b is electrically connected to the vertical signal line 5. A metal wiring 27c is formed on the first interlayer insulating film 1 and in the contact holes 25d and 25g. The metal wiring 27c electrically connects the gate electrode 19d of the control transistor 19 and the light receiving element 21.

On the first interlayer insulating film 1, the first horizontal signal line 3a, the second horizontal signal line 3b, and the vertical signal line 5
A second interlayer insulating film 7 is formed on the top and the metal wirings 27a, 27b, 27c. In the second interlayer insulating film 7, the first horizontal signal line 3 intermittently formed at the intersecting portion is formed.
A via hole 9a is formed corresponding to the tip portion of a, and a via hole 9b is formed corresponding to the tip portion of the second horizontal signal line 3b.

On the second interlayer insulating film 7 and via hole 9a
An upper wiring layer 11a is formed inside, and an upper wiring layer 11b is formed on the second interlayer insulating film 7 and inside the via hole 9b. The upper wiring layer 11a electrically connects the first horizontal signal line 3a which is intermittently formed, and the upper wiring layer 11b.
Electrically connects the second horizontal signal line 3b which is intermittently formed.

When the light receiving element region 13 shown in FIG. 4 is selected, for example, a predetermined voltage is applied to the first horizontal signal line 3a and the control transistor 1 is applied via the gate electrode 17g.
7 is turned on, and a predetermined voltage is applied to the second horizontal signal line 3b. When electric charge is accumulated in the light receiving element 21, the electric charge causes the metal wiring 27c and the gate electrode 1
The control transistor 19 is turned on via 9g, and the voltage applied to the second horizontal signal line 3b is applied to the vertical signal line 5 via the control transistor 17, the metal wiring 27a, the control transistor 19 and the metal wiring 27b. Be transmitted to.

When the charge is not accumulated in the light receiving element 21, the control transistor 19 is not turned on. Therefore, the voltage applied to the second horizontal signal line 3b is applied to the vertical signal line 5b.
Is not transmitted to. By detecting the voltage change of the vertical signal line 5, it is detected whether charge is accumulated in the light receiving element 21.

The large sensor shown in FIG. 4 is provided with two signal lines in the horizontal direction and one signal line in the vertical direction with respect to the light receiving element region 13, but the present invention is not limited to this. However, the present invention can be applied to any semiconductor device having a structure in which signal lines are arranged vertically and horizontally regardless of the number of signal lines for the light receiving element region. Further, the semiconductor device to which the present invention is applied is not limited to a large sensor, and the present invention can be applied to any semiconductor device having a structure in which signal lines are arranged vertically and horizontally, such as a liquid crystal device. . Although the embodiment of the present invention has been described above, the present invention is not limited to this, and various modifications can be made within the scope of the present invention described in the claims.

[0044]

According to the semiconductor device of the first aspect, in a semiconductor device having a structure in which signal lines are arranged vertically and horizontally,
The signal line is formed by a wiring layer in which portions other than the intersecting portions that intersect with each other are present in the same layer, and in the intersecting portion, one of the signal lines in the vertical direction or the horizontal direction is present in the same layer. Since the signal line is formed by the wiring layer and the other signal line is electrically connected through the connection hole and another wiring layer formed in another layer, the signal line is caused by the underlying step portion. It is possible to prevent problems such as wire breakage and finish variation from occurring easily, it is possible to supply a stable signal line, and it is possible to improve the reliability of the signal line. Furthermore, the parasitic capacitance values of the vertical and horizontal signal lines can be made substantially the same, and the design can be facilitated for the estimation of the signal propagation delay time. Further, by avoiding the formation of the signal line in the lowermost metal wiring layer and forming the signal line in the upper metal wiring layer than the lowermost metal wiring layer, the distance between the signal line and the semiconductor substrate can be increased. Can be secured to some extent, and the parasitic capacitance in the signal line can be reduced.

According to another aspect of the semiconductor device of the present invention, since the other wiring layer is formed in a layer above a portion other than the intersection of the signal lines, most of the signal lines are formed in a lower layer. It is possible to reduce the influence of the step difference of the underlying layer and improve the reliability of the signal line.

In the semiconductor device according to the third aspect of the present invention, the portion other than the intersection of the signal lines is formed by the lowermost metal wiring layer, so most of the signal lines are formed in the lower layer. It is possible to reduce the influence of the step difference of the base,
The reliability of the signal line can be improved.

In the semiconductor device according to the fourth aspect, the portion of the signal line electrically connected through the another wiring layer in which the connection hole is present has a wide line width. When the above-mentioned another wiring layer is formed above the portion other than the intersection of the signal lines, it is possible to reduce the step difference of the other wiring layer formed above, and to connect the signal line and the other wiring layer. Can be stabilized.

In the semiconductor device according to the fifth aspect, the signal line electrically connected through the another wiring layer is only the signal line in either the vertical direction or the horizontal direction. The circuit design is facilitated and the design efficiency can be improved.

According to a sixth aspect of the present invention, in the plurality of intersections existing in a matrix, vertical signal lines and horizontal signal lines are alternately electrically connected via the different wiring layers. Since they are connected, there is no long signal line, and it is possible to prevent formation defects such as thin line width and disconnection in the manufacturing process especially for relatively thin signal lines,
It is possible to stabilize the manufacturing process and improve the yield.

[Brief description of drawings]

FIG. 1 is a diagram showing a wiring layer structure of a large-sized sensor as one example, (A) is a plan view, and (B) is A- of (A).
Sectional drawing in a A'position, (C) is sectional drawing in a BB 'position of (A).

2A and 2B are diagrams showing a wiring layer structure of a large-sized sensor as another embodiment, in which FIG. 2A is a plan view and FIG. 2B is A in FIG.
FIG. 6C is a cross-sectional view taken along the line -A ', and FIG. 6C is a cross-sectional view taken along the line BB' in FIG.

3A and 3B are diagrams showing an example of an intersection of a horizontal signal line and a vertical signal line, FIG. 3A is a plan view, and FIG. 3B is a sectional view taken along the line AA ′ in FIG. .

FIG. 4 is a diagram showing an example of a light receiving element region of a large-sized sensor to which the present invention is applied, (A) is a plan view, (B) is a cross-sectional view taken along line BB ′ of (A), C) is A of (A)
A sectional view in the -A 'position is shown.

5A and 5B are views showing a wiring layer structure of a conventional large-sized sensor, in which FIG. 5A is a plan view, FIG. 5B is a cross-sectional view taken along the line AA ′ in FIG. 5A, and FIG. 3 is a cross-sectional view taken along line BB ′ of FIG.

[Explanation of symbols]

1 First interlayer insulating film 3 horizontal signal lines 5 Vertical signal line 7 Second interlayer insulating film 9 Via Hall 11 Upper wiring layer 13 Light receiving element area

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2H092 GA24 GA25 GA29 GA30 GA33                       GA34 GA37 GA38 GA39 GA42                       GA43 GA44 GA59 GA60 JB21                       JB22 JB23 JB24 JB31 JB32                       JB33 JB61 JB64 JB66 JB73                       NA11 NA13 NA15 NA16 NA23                       NA24 NA29                 5F033 HH07 JJ07 KK01 KK04 LL04                       QQ09 QQ37 RR04 UU04 XX24                       XX27                 5F049 MA01 NA15 NB05 QA20 SS03

Claims (6)

[Claims] 1. A semiconductor device having a structure in which signal lines are arranged vertically and horizontally, wherein the signal lines are formed by a wiring layer in which portions other than the intersecting portions that intersect each other are present in the same layer. , One of the signal lines in the vertical direction or the horizontal direction is formed by the wiring layer existing in the same layer, and the other signal line is formed through the connection hole and another wiring layer formed in another layer. A semiconductor device, which is electrically connected. 2. The semiconductor device according to claim 1, wherein the another wiring layer is formed above a portion other than the intersecting portion of the signal line. 3. A portion of the signal line other than the intersecting portion is formed by a lowermost metal wiring layer.
The semiconductor device according to. 4. The line width is formed wide in a portion of the signal line electrically connected through the another wiring layer where the connection hole exists. Semiconductor device. 5. The semiconductor according to claim 1, wherein the signal line electrically connected through the another wiring layer is only the signal line in either the vertical direction or the horizontal direction. apparatus. 6. The plurality of intersecting portions existing in a matrix, wherein vertical signal lines and horizontal signal lines are electrically connected alternately through the different wiring layers. 4. The semiconductor device according to any one of 4 above.