CN111554730A - Display panel and display device - Google Patents
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- CN111554730A CN111554730A CN202010520074.3A CN202010520074A CN111554730A CN 111554730 A CN111554730 A CN 111554730A CN 202010520074 A CN202010520074 A CN 202010520074A CN 111554730 A CN111554730 A CN 111554730A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
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Abstract
The invention discloses a display panel and a display device. The display panel includes a driving unit and a light emitting unit which are stacked, and includes: the display device comprises a first display area, a second display area, a first wire, a second wire and a plurality of light emitting units, wherein the first display area and the second display area are arranged in the same plane; for any first wire, the first wire comprises a plurality of first sub-wires, a gap is formed between any two adjacent first sub-wires and the first sub-wires are connected through a first auxiliary connecting wire, the first sub-wires and the first auxiliary connecting wire are located on different layers and are connected through via holes, and the lengths of the first sub-wires are the same. The display panel can ensure uniform change of characteristics of the thin film transistor device and improve the problem of uneven display of the periphery of a punching area of the display panel.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel and a display device.
Background
With the development of display technologies, users have higher and higher requirements on screen occupation ratios of display screens of electronic devices, so that comprehensive screen display of electronic devices is receiving more and more attention in the industry.
In the existing electronic devices (such as mobile phones and tablet computers), holes are usually formed in a display screen to place photosensitive elements such as a front camera and a receiver, so that the lengths of gate-source-drain lines of Thin Film Transistors (TFTs) around a punching area are not uniform, and the charge accumulation effects of the lines in the process of manufacturing process are different, thereby affecting the characteristics of the TFT devices, and finally showing the problem of uneven display around the punching area, i.e., abnormal display or Mura (which means the phenomenon of various traces due to uneven brightness of a display).
Disclosure of Invention
The invention provides a display panel and a display device, which can ensure uniform change of characteristics of a thin film transistor device and solve the problem of uneven display at the periphery of a punching area of the display panel.
In a first aspect, an embodiment of the present invention provides a display panel, including a driving unit and a light emitting unit, which are stacked, including:
the display device comprises a first display area, a second display area, a first wire, a second wire and a plurality of light emitting units, wherein the first display area and the second display area are arranged in the same plane; wherein the content of the first and second substances,
for any first wire, the first wire comprises a plurality of first sub-wires, a gap is formed between any two adjacent first sub-wires and the first sub-wires are connected through a first auxiliary connecting wire, the first sub-wires and the first auxiliary connecting wire are located on different layers and are connected through via holes, and the lengths of the first sub-wires are the same.
As above, optionally, each column of light emitting cells in the first display area and/or the second display area receives the second signal through one second trace; wherein the content of the first and second substances,
for any second routing line, the second routing line comprises a plurality of second sub-routing lines, a gap is formed between any two adjacent second sub-routing lines and the two adjacent second sub-routing lines are connected through a second auxiliary connecting line, the second sub-routing lines and the second auxiliary connecting line are located on different layers and are connected through via holes, and the lengths of the plurality of second sub-routing lines are the same.
The display panel as above, optionally, the display panel further comprises a main display area adjacent to the sub display area; each line of light-emitting units in the main display area receives a first signal through a first wire; each row of light-emitting units in the main display area receives a second signal through a second wire;
the functional area is a non-display area, the number of the light-emitting units in any row in the auxiliary display area is smaller than that of the light-emitting units in any row in the main display area, and the number of the light-emitting units in any column in the auxiliary display area is smaller than that of the light-emitting units in any column in the main display area; alternatively, the first and second electrodes may be,
the functional area is a display area, the functional area includes a light emitting unit, and a driving unit for driving the light emitting unit is located in the first display area and/or the second display area.
Optionally, in the display panel as above, the driving unit includes a thin film transistor, the thin film transistor includes a gate and a source/drain, the first trace is a gate trace, and the first signal is a gate signal; the second wire is a source drain wire, and the second signal is a source drain signal; alternatively, the first and second electrodes may be,
the first wiring is a source drain wiring, and the first signal is a source drain signal; the second wire is a gate wire, and the second signal is a gate signal.
As above, optionally, the light emitting unit includes an anode layer connected to the drain of the thin film transistor, the thin film transistor includes a first metal layer and a second metal layer, the gate of the thin film transistor is located on the first metal layer, and the source and/or the drain of the thin film transistor is located on the second metal layer.
The display panel as above, optionally, the first auxiliary connection line and the second auxiliary connection line are in the same layer as the anode layer;
preferably, the material of the first auxiliary connection line and the second auxiliary connection line includes at least one of indium tin oxide and indium zinc oxide.
The display panel as above, optionally, the thin film transistor further comprises a third metal layer; the third metal layer is located between the first metal layer and the second metal layer.
Optionally, the first auxiliary connection line and the second auxiliary connection line are on the same layer as the third metal layer;
preferably, the material of the first auxiliary connection line and the second auxiliary connection line includes at least one of a metal material and a metal alloy material.
As for the display panel, optionally, the width of the first auxiliary connection line is greater than or equal to the width of the first sub-trace; the width of the second auxiliary connecting line is greater than or equal to the width of the second sub-routing.
In a second aspect, an embodiment of the present invention further provides a display device, which includes a display panel having any one of the features of the first aspect.
The invention provides a display panel and a display device, wherein each row of light-emitting units in a first display area and/or a second display area receives a first signal through a first wire, the first wire is divided into a plurality of first sub-wires with the same length by designing the structure of the first wire, a gap is formed between any two adjacent first sub-wires and the first sub-wires are connected through a first auxiliary connecting wire, the first sub-wires and the first auxiliary connecting wire are positioned on different layers, and the first sub-wires and the first auxiliary connecting wires are connected through via holes, so that the characteristics of thin film transistor devices in the display panel are uniformly changed, and the problem of uneven display at the periphery of a punching area of the display panel is solved.
Drawings
FIG. 1 is a schematic diagram of a display panel with display unevenness;
fig. 2 is a schematic top view of a display panel according to an embodiment of the present invention;
fig. 3 is a schematic view of a first trace in a sub-display area of a display panel according to an embodiment of the invention;
fig. 4 is a schematic diagram of a second trace in a sub-display area of a display panel according to an embodiment of the invention;
fig. 5 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the invention;
fig. 6 is a schematic diagram illustrating an auxiliary connection line and a sub-trace according to an embodiment of the present invention;
fig. 7 is a schematic cross-sectional view illustrating another display panel according to an embodiment of the invention;
FIG. 8 is a schematic diagram illustrating another embodiment of the auxiliary connection line and the sub-trace being connected together;
fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Also, the drawings and description of the embodiments are to be regarded as illustrative in nature, and not as restrictive. Like reference numerals refer to like elements throughout the specification. In addition, the thickness of some layers, films, panels, regions, etc. may be exaggerated in the drawings for understanding and ease of description. It will also be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In addition, "on … …" means that an element is positioned on or under another element, but does not essentially mean that it is positioned on the upper side of the other element according to the direction of gravity. For ease of understanding, the figures of the present invention depict one element on top of another.
Additionally, unless explicitly described to the contrary, the word "comprise", and variations such as "comprises" or "comprising", will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.
It should also be noted that references to "and/or" in embodiments of the invention are intended to include any and all combinations of one or more of the associated listed items. Various components are described in embodiments of the present invention with "first", "second", "third", and the like, but these components should not be limited by these terms. These terms are only used to distinguish one component from another. Also, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
While certain embodiments may be practiced differently, the specific process sequence may be performed differently than described. For example, two processes described consecutively may be performed at substantially the same time or in an order reverse to that described.
In order to meet the market demand for narrow frames, existing electronic devices (such as mobile phones, tablet computers, and the like) generally need to have holes on a display screen for placing photosensitive elements such as front cameras, receivers, and the like. Fig. 1 shows a schematic diagram of a display panel in the prior art, where the display panel has a problem of uneven display, as shown in fig. 1, gate source-drain lines (only gate lines are shown in fig. 1) of a TFT around a punching region have uneven lengths, and the lines have different charge accumulation effects during a manufacturing process, which affects characteristics of the TFT device, and finally shows the problem that the display around the punching region is uneven on a product, that is, the display above and below the punching region in fig. 1 is abnormal. In order to solve the above problems, embodiments of the present invention provide a display panel and a display device, which can ensure uniform variation of characteristics of a thin film transistor device and improve the problem of uneven display around a punching area of the display panel.
Next, the structure of the display panel and its technical effects are described in detail.
In addition, the following embodiments are all exemplified by the case where the display panel is rectangular, and in practical applications, the display panel may be in a regular or irregular shape such as a circle, a polygon, and the like, and the present invention is not particularly limited thereto. Meanwhile, in order to describe the routing in the display panel more clearly, the following drawings in the embodiments of the present invention correspondingly adjust the size of each structure in the display panel.
Fig. 2 is a schematic diagram illustrating a top view structure of a display panel according to an embodiment of the present invention. The display panel at least comprises a driving unit and a light emitting unit which are arranged in a stacked mode, wherein the light emitting unit comprises an anode layer, a pixel layer and a cathode layer which are arranged in a stacked mode, for example, RGB pixels are formed, namely an R pixel is a light emitting unit capable of emitting red light, a G pixel is a light emitting unit capable of emitting green light, and a B pixel is a light emitting unit capable of emitting blue light. Of course, besides the red, green and blue colors, the display panel provided by the embodiment of the invention can emit light of other colors, such as white light, yellow light and the like. As shown in fig. 2, the display panel includes a sub-display area 10 (the display panel includes a sub-display area for example in fig. 2), and in another alternative embodiment, a main display area 20 adjacent to the sub-display area 10 may be further included. Wherein the main display area 20 and the sub display area 10 are provided with light emitting cells (not shown in fig. 2) arranged in an array. Each row of light emitting units in the main display area 20 receives a first signal through a first wire; each column of light emitting cells in the main display area 20 receives the second signal through a second trace.
The sub display region 10 includes a first display region 11 and a second display region 12, and a functional region 30 is provided between the first display region 11 and the second display region 12. The functional region 30 may be a non-display region (i.e., the functional region 30 is an opening, the functional region 30 does not need to be provided with a light emitting unit, and a driving unit corresponding to the light emitting unit does not need to be designed), or may be a display region (i.e., the functional region 30 displays an image, the functional region 30 includes a light emitting unit, a driving unit for driving the light emitting unit is located in the first display region 11 and/or the second display region 12, and the light emitting unit located in the functional region 30 and the driving unit located in the first display region 11 and/or the second display region 12 are connected by a wire, so that the light transmittance of the functional region may be improved).
Optionally, the functional region 30 is a non-display region, the display panel is designed to be an opening in the functional region, and the light emitting unit and the driving unit are not disposed in the functional region. At this time, the number of the light emitting units in any line in the sub display area 10 is smaller than that of the light emitting units in any line in the main display area 20, and the number of the light emitting units in any column in the sub display area 10 is smaller than that of the light emitting units in any column in the main display area 20, so that the sub display area 10 can be ensured to have a high transmittance, the photosensitive element is arranged below the sub display area 10, normal operation of the front photosensitive element can be ensured, meanwhile, the screen occupation ratio of the display panel is improved, and full-screen display of the display panel is facilitated.
Alternatively, the functional region 30 is a display region, and the functional region 30 includes a light emitting unit. In one embodiment, the number of any row/column light emitting units in the sub-display area 10 is smaller than the number of any row/column light emitting units in the main display area 20, the driving unit for driving the light emitting units in the functional area 30 is located in the first display area and/or the second display area, so that the functional area 30 of the sub-display area 10 can have a high transmittance, the front photosensitive element is arranged below the functional area 3, the front photosensitive element is ensured to work normally, and when the photosensitive element does not work, the display panel performs full display. In another embodiment, the number of any row/column of light emitting units in the sub-display area 10 is equal to the number of any row/column of light emitting units in the main display area 20, the driving units for driving the light emitting units in the functional area 30 are located in the first display area and/or the second display area, the number of the light emitting units in the sub-display area 10 is the same as that of the main display area 20, which is beneficial to achieving display uniformity, the driving units for driving the light emitting units in the functional area 30 are located in the first display area and/or the second display area, and the wiring density of the functional area is smaller than that of the main display area, so that the functional area 30 of the sub-display area 10 can be ensured to have higher transmittance, and the normal operation of the front photosensitive elements is ensured, and the uniformity of the full-screen display is ensured simultaneously when the photosensitive elements do not start to operate.
It should be noted that, in any implementation case that the functional area 30 is a display area or a non-display area, the number of any row/column driving units in the sub-display area is smaller than the number of any row/column driving units in the main display area, the length of the first trace in the row direction of the sub-display area is smaller than the length of the first trace in the main display area, and the length of the second trace in the column direction of any column of the sub-display area is smaller than the length of the second trace in the main display area. Fig. 3 is a schematic diagram illustrating a first trace in a sub-display area of a display panel according to an embodiment of the invention. As shown in fig. 3, for at least one of the first display area 11 and the second display area 12 in the sub-display area 10, each row of light emitting cells receives a first signal through one first wire 40, wherein for any first wire 40, the first wire 40 includes a plurality of first sub-wires 41, any two adjacent first sub-wires 41 have a gap therebetween and are connected through a first auxiliary connection line 42, the first sub-wires 41 and the first auxiliary connection line 42 are located at different layers, the first sub-wires 41 and the first auxiliary connection line 42 are connected through vias, and the plurality of first sub-wires 41 have the same length.
Through designing the structure of the first wire 40, the first wire 40 is divided into a plurality of first sub-wires 41 with the same length, and any two adjacent first sub-wires 41 have a gap and are connected through a first auxiliary connection line 42, and the first sub-wires are avoided in the functional area to reserve a light transmission area. The first sub-wires 41 and the first auxiliary connecting wires 42 are located on different layers, and the first sub-wires 41 and the first auxiliary connecting wires 42 are connected through the through holes, so that charge accumulation on each section of the first sub-wires 41 is the same during process manufacturing, and the first auxiliary connecting wires 42 are formed after the thin film transistor device structure is formed, and the characteristics of the thin film transistor device are not affected, so that the characteristics of the thin film transistor devices in the main display area and the auxiliary display area in the display panel are uniformly changed, and the problem of uneven display on the periphery of the functional area of the display panel is solved.
In order to ensure that the charge accumulation on each segment of the first sub-trace 41 is the same, the shortest distance from the functional region 30 to two frames (i.e. the left and right frames shown in fig. 3) of the display panel perpendicular to the extending direction of the first trace 40 is equal to an integral multiple of the length of the first sub-trace 41.
It should be noted that the first wires 40 in the first display area 11 and the second display area 12 located at the same horizontal position (i.e. the same row) are connected to each other, so that the wires in the same row in the secondary display area 10 are a complete wire, thereby reducing the delay difference between the secondary display area 10 and the main display area 20 during displaying and improving the display effect.
On the basis of the foregoing embodiments, fig. 4 illustrates a second trace schematic diagram in a sub-display area of a display panel according to an embodiment of the present invention. As shown in fig. 4, for at least one of the first display area 11 and the second display area 12 in the sub-display area 10, each row of light emitting units receives a second signal through one second wire 50, wherein for any second wire 50, the second wire 50 includes a plurality of second sub-wires 51, any two adjacent second sub-wires 51 have a gap therebetween and are connected through a second auxiliary connection line 52, the second sub-wires are avoided in the functional region to reserve a light transmission area, the second sub-wires 51 and the second auxiliary connection line 52 are located at different layers, the second sub-wires 51 and the second auxiliary connection line 52 are connected through a via, and the lengths of the plurality of second sub-wires 51 are the same.
Through designing the structure of the second wire 50, the second wire 50 is also divided into a plurality of second sub-wires 51 with the same length, and any two adjacent second sub-wires 51 have a gap and are connected through the second auxiliary connecting line 52, the second sub-wires 51 and the second auxiliary connecting line 52 are located at different layers, and the second sub-wires 51 and the second auxiliary connecting line 52 are connected through via holes, so that the charge accumulation on each section of the second sub-wires 51 is the same during the working and manufacturing process, and the second auxiliary connecting line 52 is formed after the thin film transistor device structure is formed, the characteristics of the thin film transistor device are not affected, so that the characteristics of the thin film transistor devices in the main display area and the auxiliary display area in the display panel are uniformly changed, and the problem of uneven display on the periphery of the functional area of the display panel is further improved.
In order to ensure that the charge accumulation on each section of the second sub-traces 51 is the same, the shortest distance from the functional region 30 to two frames (i.e., the upper and lower frames shown in fig. 4) of the display panel perpendicular to the extending direction of the second trace 50 is equal to an integer multiple of the length of the second sub-trace 51.
It should be noted that the second wires 50 located at the same vertical position (i.e. the same column) in the first display area 11 and the second display area 12 are connected to each other, so that the wires on the same column in the secondary display area 10 are a complete wire, thereby reducing the delay difference between the secondary display area 10 and the main display area 20 during displaying and improving the display effect.
As can be seen from fig. 3 and fig. 4, the first trace 40 is a gate trace, and the first signal is a gate signal; the second trace 50 is a source-drain trace, and the second signal is a source-drain signal; or, the first trace 40 is a source-drain trace, and the first signal is a source-drain signal; the second trace 50 is a gate trace, and the second signal is a gate signal. The grid routing and the source drain routing are vertically distributed.
It should be further noted that, for the case that the functional area 30 is a non-display area and a display area, since the driving units are located in the first display area 11 and/or the second display area 12, the above-mentioned solution of the present invention divides the first wire into a plurality of first sub-wires with the same length, divides the second wire into a plurality of second sub-wires with the same length, and connects the first sub-wires and the second self-propelled wires respectively through the first auxiliary connecting wire and the second auxiliary connecting wire, and the sub-wires in the main display area and the sub-display area have the same length, and the charge accumulation is the same during the process manufacturing, and the problem of non-uniform display of the periphery of the functional area can be solved when the functional area is displayed or not displayed.
In addition, in order to avoid the situation of resistance increase caused by the increase of the trace length, in the embodiment of the present invention, the width of the first auxiliary connection line 42 (i.e. the side length of the first auxiliary connection line 42 perpendicular to the extending direction of the first trace 40) may be greater than or equal to the width of the first sub-trace 41; the width of the second auxiliary connecting line 52 (i.e. the length of the second auxiliary connecting line 52 perpendicular to the extending direction of the second trace 50) may be greater than or equal to the width of the second sub-trace 51. Therefore, the problem that the path is lengthened due to the addition of the auxiliary connecting line is solved, and the resistance is reduced by widening the line width of the auxiliary connecting line.
Optionally, in a display panel, the length of the first sub-trace 41 and the length of the second sub-trace 51 may be the same or different, so that characteristics of the thin film transistor device can be changed uniformly, and the problem of uneven display around the display panel punching area is solved.
Optionally, for the wires in the main display area 20, a conventional structure may be selected, or a structure disclosed in the embodiment of the present invention may be adopted, that is, each row of light emitting units receives a first signal through one first wire, where the first wire includes a plurality of first sub-wires, any two adjacent first sub-wires have a gap therebetween and are connected through a first auxiliary connection line, the first sub-wires and the first auxiliary connection line are located on different layers, and the first sub-wires and the first auxiliary connection line are connected through via holes, and the lengths of the plurality of first sub-wires are the same; each row of light-emitting units receives a second signal through a second routing wire, the second routing wire comprises a plurality of second sub-routing wires, a gap is formed between any two adjacent second sub-routing wires and the two adjacent second sub-routing wires are connected through a second auxiliary connecting wire, the second sub-routing wires and the second auxiliary connecting wire are located on different layers and are connected through via holes, and the lengths of the plurality of second sub-routing wires are the same. The main display area 20 and the sub-display area 10 adopt the same routing structure, so that the manufacturing difficulty of the display panel can be reduced.
In order to reduce the manufacturing steps of the display panel, the first auxiliary connecting lines 42 and the second auxiliary connecting lines 52 may be located at the same layer. When the first auxiliary connection line 42 and the second auxiliary connection line 52 are specifically provided, the auxiliary connection lines may be provided in different layers of the display panel.
The driving unit comprises a thin film transistor, the thin film transistor comprises a grid electrode and a source drain electrode, the light emitting unit comprises an anode layer connected with the drain electrode of the thin film transistor, the thin film transistor comprises a first metal layer and a second metal layer, the grid electrode of the thin film transistor is located on the first metal layer, and the source electrode and/or the drain electrode of the thin film transistor is located on the second metal layer.
Fig. 5 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the present invention. As shown in fig. 5, a thin film transistor with a top gate structure is taken as an example, wherein the thin film transistor may include other layers in addition to the layers mentioned in the above embodiments. Specifically, the thin film transistor includes:
a substrate 100; a buffer layer 101 on the substrate 100, an active layer 102 on the buffer layer 101, a gate insulating layer 103 on the active layer 102, a gate electrode 104 on the gate insulating layer 103, an interlayer insulating layer 105 on the gate electrode 104, and a source electrode 106 and a drain electrode 107 on the interlayer insulating layer 105; a passivation layer 108 on the source electrode 106 and the drain electrode 107; the source electrode 106 and the drain electrode 107 may be located in the same layer and obtained through a single patterning process, and therefore, the source electrode 106 and the drain electrode 107 may also be referred to as a source-drain metal layer (i.e., a second metal layer).
In particular, the substrate 100 may be flexible and thus stretchable, foldable, bendable, or rollable, such that the display panel may be stretchable, foldable, bendable, or rollable. The substrate 100 may be formed of any suitable insulating material having flexibility. The substrate 100 may serve to block oxygen and moisture, prevent diffusion of moisture or impurities, and provide a flat surface on the upper surface of the substrate 100.
For example, it may be formed of a polymer material such as Polyimide (PI), Polycarbonate (PC), Polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), Polyarylate (PAR), or glass Fiber Reinforced Plastic (FRP), and the substrate 100 may be transparent, translucent, or opaque.
A buffer layer 101, the buffer layer 101 may cover the entire upper surface of the substrate 100. For example, the buffer layer 101 may be formed of a material selected from an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SioxNy), aluminum oxide (AlOx), or aluminum nitride (AlNx), or a material selected from an organic material such as acryl, Polyimide (PI), or polyester. Buffer layer 101 may include a single layer or multiple layers. The buffer layer 101 may block impurities in the substrate 100 from diffusing to other film layers.
The active layer 102 is positioned on the buffer layer 101, and the active layer 102 includes a source region and a drain region formed by doping N-type impurity ions or P-type impurity ions. The region between the source region and the drain region is the channel region.
The active layer 102 may be an amorphous silicon material, a polysilicon material, a metal oxide material, or the like. When the active layer is made of polycrystalline silicon material, the active layer can be formed by adopting a low-temperature amorphous silicon technology, namely, the amorphous silicon material is melted by the laser to form the polycrystalline silicon material. In addition, various methods such as a Rapid Thermal Annealing (RTA) method, a Solid Phase Crystallization (SPC) method, an Excimer Laser Annealing (ELA) method, a Metal Induced Crystallization (MIC) method, a Metal Induced Lateral Crystallization (MILC) method, or a Sequential Lateral Solidification (SLS) method may also be used.
The gate insulating layer 103 includes an inorganic layer such as silicon oxide, silicon nitride, and may include a single layer or a plurality of layers. The gate electrode 104 is located on the gate insulating layer 103 and is patterned from a first metal layer. The first metal layer may include a single layer or a plurality of layers of gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), aluminum (Al), Molybdenum (MO), or chromium (Cr), or a metal such as aluminum (Al): neodymium (Nd) alloy and Molybdenum (MO) alloy, tungsten (W) alloy.
An interlayer insulating layer 105 is positioned on the gate electrode 105. The interlayer insulating layer 105 may be formed of an insulating inorganic layer of silicon oxide, silicon nitride, or the like. Alternatively, the interlayer insulating layer 105 may be formed of an insulating organic layer.
Source and drain metal layers (i.e., source 106 and drain 107) are located on the interlayer insulating layer 105. The source electrode 106 and the drain electrode 107 are electrically connected to the source region and the drain region, respectively, through contact holes penetrating the gate insulating layer 103 and the interlayer insulating layer 105.
The passivation layer 108 is located on the source drain metal layer. The passivation layer 108 may be formed of an inorganic layer of silicon oxide, silicon nitride, or the like, or an organic layer. Illustratively, a planarization layer on the passivation layer 108 may also be included. The planarization layer includes an organic layer of acryl, Polyimide (PI), benzocyclobutene (BCB), or the like, and has a planarization effect.
A light emitting cell is disposed above the thin film transistor, and an anode layer 109 of the light emitting cell is electrically connected to a drain 107 of the thin film transistor. Specifically, the anode layer 109 is electrically connected to the drain electrode 107 through a via hole penetrating the passivation layer 108 and the planarization layer.
Fig. 6 is a schematic diagram illustrating a bonding between an auxiliary connection line and a sub-trace according to an embodiment of the present invention. In the actual manufacturing process, in order to reduce the manufacturing processes and the manufacturing difficulty and cost, the first auxiliary connecting line 42 and the second auxiliary connecting line 52 are formed in the same layer as the anode layer 109, i.e., in the same process step as the anode layer 109. As shown in fig. 6(a), the first auxiliary connecting line 42 is electrically connected to the first sub-trace 41 through a via, two adjacent first sub-traces 41 (respectively denoted as 41a and 41b in fig. 6) are connected through the first auxiliary connecting line 42, as shown in fig. 6(b), the second auxiliary connecting line 52 is electrically connected to the second sub-trace 51 through a via, and two adjacent second sub-traces 51 (respectively denoted as 51a and 51b in fig. 6) are connected through the second auxiliary connecting line 52. Specifically, the size and the position of the light emitting unit opening of the display panel can be designed to ensure that the first auxiliary connecting line 42 and the second auxiliary connecting line 52 are in the same layer as the anode layer 109 and do not contact with the anode layer.
When the first and second auxiliary connection lines 42 and 52 are layered with the anode layer 109, the material of the first and second auxiliary connection lines 42 and 52 includes at least one of indium tin oxide and indium zinc oxide.
Further, the thin film transistor further includes a storage capacitor, and fig. 7 shows a schematic cross-sectional structure of another display panel according to an embodiment of the present invention, and as shown in fig. 7, the storage capacitor includes at least two storage electrodes of the first to fourth storage electrodes 192, 194, 196, and 198. The first storage electrode 192 is formed of the same material as the active layer 102 on the buffer layer 101. The second storage electrode 194 is formed of the same material as the gate electrode 104 on the gate insulating layer 103. The third storage electrode 196 is formed of the same material as the gate electrode 104 and one of the source and drain electrodes 106 and 107 on a certain film layer within the interlayer insulating layer 105. The fourth storage electrode 198 is formed of the same material as the source and drain electrodes 106 and 107 on the interlayer insulating layer 105.
The third storage electrode 196 is located at a third metal layer between the first metal layer and the second metal layer. The first auxiliary connection line 42 and the second auxiliary connection line 52 are disposed on the third metal layer and disposed on the same layer as the third storage electrode 196, so that the manufacturing processes can be reduced, the manufacturing difficulty and cost can be reduced, and the size and position of the light-emitting unit opening of the display panel do not need to be additionally designed. Fig. 8 is a schematic diagram illustrating another alternative connection line and sub-trace overlapping according to an embodiment of the present invention. As shown in fig. 8(a), the first auxiliary connecting line 42 is electrically connected to the first sub-trace 41 through a via, two adjacent first sub-traces 41 (respectively labeled as 41a and 41b in fig. 8) are connected through the first auxiliary connecting line 42, as shown in fig. 8(b), the second auxiliary connecting line 52 is electrically connected to the second sub-trace 51 through a via, and two adjacent second sub-traces 51 (respectively labeled as 51a and 51b in fig. 8) are connected through the second auxiliary connecting line 52. The interlayer insulating layer 105 is formed of a plurality of insulating inorganic layers and/or insulating organic layers, and two layers are illustrated in fig. 8 and denoted by 105a and 105b, respectively.
When the first and second auxiliary connection lines 42 and 52 are in the same layer as the third metal layer, the material of the first and second auxiliary connection lines 42 and 52 includes at least one of a metal material and a metal alloy material.
In addition, the display panel provided by the embodiment of the application only needs to slightly change the manufacturing method of the anode layer/the third metal layer, and does not increase an additional process.
The functional region 30 of the display panel provided in the embodiment of the present application may be in the shape of a drop, a diamond, a circle, a rectangle, a semicircle, a semi-ellipse, or an ellipse. However, the shape of the sub-display area may be different depending on the actual situation.
An embodiment of the present invention provides a display panel, including: the display device comprises a first display area, a second display area, a first wire, a second wire and a plurality of light emitting units, wherein the first display area and the second display area are arranged in the same plane; for any first wire, the first wire comprises a plurality of first sub-wires, a gap is formed between any two adjacent first sub-wires and the first sub-wires are connected through a first auxiliary connecting wire, the first sub-wires and the first auxiliary connecting wire are located on different layers and are connected through via holes, and the lengths of the first sub-wires are the same. Through designing the structure of the first wiring, the first wiring is divided into a plurality of first sub-wirings with the same length, a gap is reserved between any two adjacent first sub-wirings and the first sub-wirings are connected through a first auxiliary connecting line, the first sub-wirings and the first auxiliary connecting line are located on different layers, and the first sub-wirings and the first auxiliary connecting line are connected through via holes, so that the characteristics of thin film transistor devices in the display panel are uniform and changed, and the problem of uneven display of the periphery of a punching area of the display panel is solved.
Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present invention. As shown in fig. 9, the display device 70 includes a display panel 71 provided in any embodiment of the present invention and a photosensitive element (not shown in fig. 9), where the photosensitive element is located below a functional area (shown by a dotted line in fig. 9) of the display panel, so as to implement full-screen display of the display device.
Illustratively, the light sensing elements may be front cameras and sensors. Optionally, besides the photosensitive element, other devices, such as a gyroscope or a receiver, may be disposed below the functional region.
The display panel 71 may be a flexible organic light emitting display panel or a non-flexible organic light emitting display panel. The light emitting mode of the organic light emitting display panel may be top emission, bottom emission, or dual emission.
The display device 70 provided by the embodiment of the present invention may be applied to an intelligent wearable device (such as an intelligent bracelet and an intelligent watch), and may also be applied to a smart phone, a tablet computer, a display, and the like.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A display panel including a driving unit and a light emitting unit which are arranged in a stacked manner, comprising:
the display device comprises a first display area, a second display area, a first wire, a second wire and a plurality of light emitting units, wherein the first display area and the second display area are arranged in a same plane; wherein the content of the first and second substances,
for any first wire, the first wire comprises a plurality of first sub-wires, a gap is formed between any two adjacent first sub-wires and the first sub-wires are connected through a first auxiliary connecting wire, the first sub-wires and the first auxiliary connecting wire are located on different layers and are connected through via holes, and the lengths of the first sub-wires are the same.
2. The display panel according to claim 1, wherein each column of light emitting cells in the first display area and/or the second display area receives a second signal through a second trace; wherein the content of the first and second substances,
for any second wire, the second wire comprises a plurality of second sub-wires, a gap is formed between any two adjacent second sub-wires and the two adjacent second sub-wires are connected through a second auxiliary connecting wire, the second sub-wires and the second auxiliary connecting wire are located on different layers and are connected through via holes, and the lengths of the plurality of second sub-wires are the same.
3. The display panel according to claim 2, further comprising a main display region adjacent to the sub display region; each line of light-emitting units in the main display area receives a first signal through a first wire; each row of light emitting units in the main display area receives a second signal through a second wire;
the functional area is a non-display area, the number of any row of light-emitting units in the auxiliary display area is smaller than that of any row of light-emitting units in the main display area, and the number of any column of light-emitting units in the auxiliary display area is smaller than that of any column of light-emitting units in the main display area; alternatively, the first and second electrodes may be,
the functional area is a display area, the functional area comprises a light emitting unit, and a driving unit for driving the light emitting unit is located in the first display area and/or the second display area.
4. The display panel according to claim 3,
the driving unit comprises a thin film transistor, the thin film transistor comprises a grid electrode and a source drain electrode, the first wiring is a grid electrode wiring, and the first signal is a grid electrode signal; the second wiring is a source drain wiring, and the second signal is a source drain signal; alternatively, the first and second electrodes may be,
the first wiring is a source drain wiring, and the first signal is a source drain signal; the second wire is a gate wire, and the second signal is a gate signal.
5. The display panel according to claim 4, wherein the light emitting unit comprises an anode layer connected to a drain electrode of the thin film transistor, the thin film transistor comprises a first metal layer and a second metal layer, a gate electrode of the thin film transistor is located on the first metal layer, and a source electrode and/or a drain electrode of the thin film transistor is located on the second metal layer.
6. The display panel according to claim 5, wherein the first auxiliary connection line and the second auxiliary connection line are in the same layer as the anode layer;
preferably, a material of the first auxiliary connection line and the second auxiliary connection line includes at least one of indium tin oxide and indium zinc oxide.
7. The display panel according to claim 5, wherein the thin film transistor further comprises a third metal layer; the third metal layer is located between the first metal layer and the second metal layer.
8. The display panel according to claim 7, wherein the first auxiliary connecting line and the second auxiliary connecting line are in the same layer as the third metal layer;
preferably, the material of the first auxiliary connection line and the second auxiliary connection line includes at least one of a metal material and a metal alloy material.
9. The display panel according to claim 2, wherein the width of the first auxiliary connection line is greater than or equal to the width of the first sub-trace; the width of the second auxiliary connecting line is greater than or equal to the width of the second sub-routing.
10. A display device comprising the display panel according to any one of claims 1 to 9 and a photosensitive element, the photosensitive element being located below the functional area of the display panel.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003110019A (en) * | 2001-10-01 | 2003-04-11 | Ricoh Co Ltd | Semiconductor device |
| US20050140570A1 (en) * | 2003-10-28 | 2005-06-30 | Toshiba Matsushita Display Technology Co., Ltd. | Circuit array substrate and flat panel display device provided with the same |
| US20130009154A1 (en) * | 2011-07-07 | 2013-01-10 | Hee-Dong Choi | Array substrate for organic electroluminescent display device and method of fabricating the same |
| CN108336117A (en) * | 2017-09-30 | 2018-07-27 | 云谷（固安）科技有限公司 | Display screen and electronic equipment |
| CN108417604A (en) * | 2018-02-27 | 2018-08-17 | 上海天马微电子有限公司 | Display panel and display device |
| CN108732841A (en) * | 2018-05-31 | 2018-11-02 | 厦门天马微电子有限公司 | A kind of display panel and preparation method thereof, display device |
| CN108777260A (en) * | 2018-06-11 | 2018-11-09 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN108807426A (en) * | 2018-06-29 | 2018-11-13 | 厦门天马微电子有限公司 | A kind of array substrate and display panel |
-
2020
- 2020-06-09 CN CN202010520074.3A patent/CN111554730B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003110019A (en) * | 2001-10-01 | 2003-04-11 | Ricoh Co Ltd | Semiconductor device |
| US20050140570A1 (en) * | 2003-10-28 | 2005-06-30 | Toshiba Matsushita Display Technology Co., Ltd. | Circuit array substrate and flat panel display device provided with the same |
| US20130009154A1 (en) * | 2011-07-07 | 2013-01-10 | Hee-Dong Choi | Array substrate for organic electroluminescent display device and method of fabricating the same |
| CN108336117A (en) * | 2017-09-30 | 2018-07-27 | 云谷（固安）科技有限公司 | Display screen and electronic equipment |
| CN108417604A (en) * | 2018-02-27 | 2018-08-17 | 上海天马微电子有限公司 | Display panel and display device |
| CN108732841A (en) * | 2018-05-31 | 2018-11-02 | 厦门天马微电子有限公司 | A kind of display panel and preparation method thereof, display device |
| CN108777260A (en) * | 2018-06-11 | 2018-11-09 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN108807426A (en) * | 2018-06-29 | 2018-11-13 | 厦门天马微电子有限公司 | A kind of array substrate and display panel |
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