JP2003109969A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a junction comprising a definite depth is formed with satisfactory reproducibility. SOLUTION: Germanium ions 14A are ion-implanted to the surface region of a semiconductor substrate 11 at a prescribed acceleration voltage and in a prescribed dose amount. As a result, an amorphous layer 15A in a prescribed depth is formed in the surface region of the semiconductor substrate 11. After that, by a downflow etching operation, the amorphous layer 15A is etched selectively with reference to the semiconductor substrate (a crystal layer). An etching amount at this time is controlled precisely and easily as compared with a case where merely the semiconductor substrate 11 is etched without the amorphous layer 15A. When a semiconductor layer containing impurities fills a hollow on the semiconductor substrate 11 formed by this etching operation, a shallow junction is formed with satisfactory reproducibility.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a shallow junction, and more particularly to a MISFET having an extension part of a source / drain region having a depth of 20 nm or less.
Applied to.

[0002]

2. Description of the Related Art Conventionally, for example, in a fine CMOS technology, in order to prevent a short channel effect and reduce a parasitic resistance, it is particularly necessary to make a depth of a pn junction of an extension portion of a source / drain region as shallow as possible. Is desired. However, in the conventional MISFET process technology, the pn of the extension part of the source / drain region is
It is extremely difficult to set the junction depth to 20 nm or less.

That is, in the conventional MISFET manufacturing process, the source / drain regions and the extension portions thereof are formed by ion implantation of impurities and subsequent rapid thermal annealing for activation of the impurities. It However, in ion implantation, it is essentially difficult to realize a steep impurity profile immediately after ion implantation, and accelerated diffusion of impurities occurs during annealing, so that the source / drain regions and their extension portions in the depth direction are formed. The gradient of impurity concentration is gentle (3n
The gradient becomes more than m / decade), and as a result, it is not possible to form the extension portion of 20 nm or less.

Further, in the conventional MISFET manufacturing process, the phenomenon that the impurity concentration in the source / drain regions and the extension portions thereof is lowered due to the accelerated diffusion of impurities also occurs.

Therefore, in the past, the source
There has been a problem that the depth of the pn junction in the extension part of the drain region cannot be adapted to the value (20 nm or less) required for the MISFET of the 50 nm generation or later.

By the way, in order to solve such a problem, conventionally, a shallow recess is formed in a semiconductor substrate by etching,
A silicon layer containing an impurity to be a source / drain region (or an extension thereof) is filled in the depression,
That process technology has been proposed (for example, Japanese Patent Application Laid-Open No. 8-153688). According to this technology,
It is possible to form the source / drain regions (or the extension portions thereof) having a high concentration and a steep concentration gradient.

However, this process technology is not perfect, and there is a problem that must be solved in mass production. The problem is reproducibility. That is, during mass production,
Although it is required that the depth of the depression is always substantially constant, as the depth of the depression becomes shallower, it becomes more difficult to control the etching amount. Especially, for a junction of 20 nm or less, a uniform depth It is becoming difficult to form with good reproducibility.

[0008]

As described above, conventionally, there has been proposed a process technique in which a shallow depression is formed in a semiconductor substrate and the source / drain region or a silicon layer to be an extension portion thereof is filled in the depression. . However, for a very shallow junction (a junction of 20 nm or less), it is difficult to control the etching amount of the semiconductor substrate when forming the depression, and there is a problem that it cannot be formed with a uniform depth and good reproducibility. .

An object of the present invention is to provide a semiconductor device capable of forming a shallow junction having a substantially constant depth (in particular, an extension portion of a source / drain region of a MISFET) with good reproducibility and a manufacturing method thereof. It is in.

[0010]

(1) A semiconductor device of the present invention includes a semiconductor substrate and a MISFET formed in a surface region of the semiconductor substrate, and a pn of an extension portion of a source / drain region of the MISFET. It contains germanium at the junction interface.

A semiconductor device of the present invention comprises a semiconductor substrate and a MISFET formed in a surface region of the semiconductor substrate, and a pn of a source / drain region of the MISFET.
Germanium is contained in at least a part of the interface of the junction.

The concentration of germanium is 1 × 10 ¹³
It is set in the range of cm ^-2 to 1 × ¹⁰ 15 ^{cm -2.}

The interface of the pn junction contains oxygen together with the germanium.

The depth of the extension portion is 20n.
m or less.

The extension portion is provided with the MISF.
It is arranged immediately below the sidewall formed on the sidewall of the ET gate electrode.

The germanium is contained in all of the pn junction interfaces of the source / drain regions.

(2) A method of manufacturing a semiconductor device according to the present invention is
Implanting semiconductor atoms into the surface region of the semiconductor substrate by ion implantation, and selectively etching the surface region amorphized by the semiconductor atoms with respect to the semiconductor substrate to form a recess in the semiconductor substrate. And filling the semiconductor layer containing impurities in the recess.

The semiconductor atom is germanium or silicon.

The depth of the recess is determined by the acceleration voltage and the dose amount of the semiconductor atom.

The depression is formed by downflow etching.

The ion implantation is performed in a self-aligned manner by using the gate electrode of the MISFET formed on the semiconductor substrate as a mask, and the semiconductor layer functions as a source / drain region of the MISFET.

The semiconductor atoms are obliquely implanted into the surface of the semiconductor substrate.

The method of manufacturing a semiconductor device according to the present invention comprises the steps of forming a gate electrode on a semiconductor substrate and implanting semiconductor atoms in a surface region of the semiconductor substrate in a self-aligned manner by ion implantation using the gate electrode as a mask. And a step of selectively etching the surface region amorphized by semiconductor atoms with respect to the semiconductor substrate to form a recess in the semiconductor substrate, and filling the semiconductor layer containing impurities in the recess. Forming an extension portion of the source / drain region.

The method of manufacturing a semiconductor device of the present invention further comprises the steps of forming a sidewall on the side wall of the gate electrode after forming the extension portion, and ion implantation using the gate electrode and the sidewall as a mask. Implanting impurities into the surface region of the semiconductor substrate in a self-aligned manner to form main portions of the source / drain regions.

The method of manufacturing a semiconductor device of the present invention further comprises the steps of forming a sidewall on the side wall of the gate electrode after forming the extension portion, and ion implantation using the gate electrode and the sidewall as a mask. Forming a recess in the semiconductor substrate by injecting the semiconductor atoms into the surface region of the semiconductor substrate in a self-aligned manner, and selectively etching the surface region amorphized by the semiconductor atoms with respect to the semiconductor substrate And a step of filling the recess with a semiconductor layer containing impurities to form a main part of the source / drain region.

In the method of manufacturing a semiconductor device of the present invention, a step of forming a gate electrode on a semiconductor substrate and a step of implanting semiconductor atoms in a surface region of the semiconductor substrate by self-alignment by ion implantation using the gate electrode as a mask. Forming a sidewall on the sidewall of the gate electrode, and implanting semiconductor atoms in a surface region of the semiconductor substrate in a self-aligned manner by ion implantation using the gate electrode and the sidewall as a mask. A step of selectively etching the surface region amorphized by the semiconductor atoms with respect to the semiconductor substrate to form a recess in the semiconductor substrate; and filling the semiconductor layer containing impurities in the recess with an extension. Forming a source / drain region including a portion.

[0027]

DETAILED DESCRIPTION OF THE INVENTION A method of manufacturing a semiconductor device of the present invention and a semiconductor device formed by this method will be described in detail below with reference to the drawings.

[First Embodiment] FIGS. 1 to 5 show a method of manufacturing a MISFET according to a first embodiment of the present invention.

First, as shown in FIG. 1, a thermal oxidation layer and a polysilicon layer containing impurities are formed on a semiconductor substrate (eg, a silicon substrate) 11, and then PEP (Photo Eng) is used.
raving Process) and RIE (Reactive Ion Etching)
) Pattern the silicon layer and the thermal oxide layer,
A gate insulating film 12 and a gate electrode 1 on a semiconductor substrate 11.
3 is formed.

After that, using the gate electrode 13 as a mask,
Self-aligningly, germanium ion (Ge ⁺ ) 14A
Is, for example, acceleration voltage 10 keV, dose amount 1 × 10
Ions are implanted into the surface region of the semiconductor substrate 11 under the condition of ¹⁴ cm ⁻² .

As a result, 10 n from the region where the germanium ions are implanted, for example, the surface position of the semiconductor substrate 11.
A semiconductor (for example, silicon) in a region up to a depth of about m is made amorphous, and the amorphous layer 15A is formed.
Becomes

Here, as a result of ion implantation, 1 × 10 ¹³ c is formed on the semiconductor substrate 11 immediately below the amorphous layer 15A.
m ^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, in the case of ion implantation under the above conditions, 5 × 10 5
Germanium (about ¹³ cm ⁻² ) is included.

Next, as shown in FIG. 2, an amorphous layer (FIG. 1) 15A in the surface region of the semiconductor substrate 11 is formed by down-flow etching using a halogen-based reactive gas.
Only the semiconductor layer (for example, silicon crystal) is selectively etched to remove the amorphous layer 15A. As a result, a recess 16A having a depth of about 10 nm is formed in the surface region of the semiconductor substrate 11.

Next, as shown in FIG. 3, after removing the natural oxide film formed on the surface of the semiconductor substrate 11 by the treatment with dilute hydrofluoric acid, the semiconductor substrate (wafer) 11 is immediately CVD-deposited.
Transport to equipment. Further, in the CVD apparatus, the semiconductor substrate 11 is subjected to hydrogen annealing at 600 ° C. for 3 minutes to remove the natural oxide film formed on the surface of the semiconductor substrate 11 during transportation.

Then, in the CVD apparatus, dichlorosilane was used.
(SiH2Cl2), hydrochloric acid (HCl), hydrogen (H2), and diborane (B2H6) mixed gas at 600 ° C., for example, 400, respectively.
Flow at a rate of 100, 14500, 100 sccm,
A conductive semiconductor layer (for example, a silicon layer) 17 containing boron is formed on the exposed portion (the surface of the recess 16A) of the semiconductor substrate 11.

The semiconductor layer 17 is formed to the extent that it fills the recess 16A, and as a result, the extension portion of the source / drain region having a steep profile with a depth of about 10 nm is formed.

Here, even if the semiconductor layer 17 is formed to be about 10 nm or more slightly beyond the initial height of the substrate surface, the depth Xj of the pn junction in the extension portion of the source / drain region is: It has virtually no effect.

Next, as shown in FIG. 4, the gate electrode 13
Side walls 21 are formed on the side walls. The sidewall 21 can be easily formed, for example, by forming an insulating layer on the entire surface of the semiconductor substrate 11 and then etching this insulating layer by RIE.

A resist layer is formed on the entire surface of the semiconductor substrate 11, and the resist layer is patterned by photolithography. The patterned resist layer (resist pattern) is, for example, an n-channel MISF.
It covers the region where ET is formed and serves as a mask for ion implantation performed thereafter.

That is, the resist pattern and the gate electrode 13
By ion implantation using the sidewalls 21 as a mask, for example, boron ions (B ⁺ ) are accelerated with an acceleration voltage of 3 ke.
It is self-alignedly injected into the semiconductor substrate 11 under the conditions of V and a dose amount of 4 × 10 ¹⁵ cm ⁻² . Then, after that, high-speed temperature rising / falling annealing is performed to form the source / drain regions (main part) 22A in the semiconductor substrate 11.

Next, as shown in FIG.
A refractory metal (for example, nickel, cobalt, titanium, titanium nitride, or the like) is formed on the source / drain regions 22A and the sidewalls 21. Further, annealing is performed to thermally react the refractory metal with silicon (the gate electrode 13 and the source / drain regions 22A) to form the silicide layers 23 on the gate electrode 13 and the source / drain regions 22A, respectively.

After that, the unreacted refractory metal present in the region such as the sidewall 21 is removed by chemical treatment (salicide process: self-aligned silicide pr
ocess).

Through the above steps, a MISFET having a pn junction depth of 20 nm or less in the extension portion of the source / drain region is completed.

In the above description of the manufacturing method, germanium is used to form the amorphous layer 15A, but instead of this, semiconductor atoms such as silicon may be used.

In the above description of the manufacturing method, the method of manufacturing the p-channel type MISFET has been described as a premise, but the present invention can naturally be applied to the method of manufacturing the n-channel type MISFET.

In this case, in the CVD process for forming the extension portion, diborane as a reaction gas is used.
Instead of (B2H6), phosphine (PH3) or arsine (AsH3)
To use. In the ion implantation process for forming the source / drain regions, instead of boron ions,
At least one of phosphorus ion and arsenic ion is used. The phosphorus ion implantation condition is, for example, an acceleration voltage of 5 ke.
V, the dose ¹ × ¹⁰ 1 5 ^{cm -2,} the ion implantation conditions arsenic, for example, acceleration voltage 40 keV, a dose of 5 × ¹⁰ 15 ^{cm -2.}

The present invention can also be applied to a method of manufacturing a MIS transistor in a CMOS device.

According to the manufacturing method of the invention relating to the present embodiment, for example, the 50 nm generation (20
11 years) required depth 10 nm, impurity concentration 1 × 1
0 ^{2 2} cm ^-3, it can be realized an extension portion having a steep profile of the above gradient 3 nm / decade.

In the MISFET formed by the manufacturing method of this embodiment, 1 × 10 ¹³ cm is formed at the interface of the pn junction in the extension portion of the source / drain region.
^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, 5 × 10 ¹³ cm ⁻² germanium) is included.

In addition to the fact that the germanium hardly diffuses itself, the conductive semiconductor layer 17 is formed in the recess 16A when forming the extension portions of the source / drain regions, that is, by the CVD method. It has a barrier function of suppressing diffusion of impurities (for example, boron, phosphorus, etc.) in the semiconductor layer 17 into the semiconductor substrate 11 at the time of performing, or at the time of subsequent annealing.

That is, impurities are introduced into the semiconductor layer 17 by so-called in-situ doping during the CVD, but the diffusion of the impurities toward the semiconductor substrate 11 is
Since it is suppressed by germanium, the profile of the extension portion of the source / drain region in the depth direction can be made steeper.

Here, the concentration of germanium is 1 ×.
If it is less than 10 ¹³ cm ^-2 , its barrier function deteriorates,
When the concentration of germanium exceeds 1 × 10 ¹⁵ cm ⁻² , the resistance of the extension portion of the source / drain region may increase due to deterioration of carrier mobility. Therefore, it is desired to keep the germanium concentration within the above range.

Further, in the manufacturing method according to the present embodiment, hydrogen annealing is performed before forming the conductive semiconductor layer 17 in the recess 16A to remove the natural oxide film formed on the surface of the recess 16A. is doing. However, in reality, even if this hydrogen annealing is performed, the natural oxide film formed on the surface of the depression 16A cannot be completely removed.

Therefore, 1 × is formed on the interface of the pn junction in the extension portion of the source / drain region of the MISFET.
Oxygen of about 1 × 10 ¹⁴ cm ⁻² may be contained together with germanium of 10 ¹³ cm ^{−2 to} 1 × 10 ¹⁵ cm ⁻² .

Although not so much as germanium, this oxygen is also used when forming the extension portions of the source / drain regions, that is, when forming the conductive semiconductor layer 17 in the recess 16A by the CVD method and the subsequent annealing. In some cases, impurities in the semiconductor layer 17 may become
It has a barrier function of suppressing diffusion inside.

As described above, according to the method of manufacturing the semiconductor device of the present embodiment and the semiconductor device formed by this method, the shallow junction having a substantially constant depth (in particular, MI junction) is formed.
The extension portion of the source / drain region of the SFET) can be formed with good reproducibility.

[Second Embodiment] This embodiment is an application example of the above-described first embodiment.

That is, in the above-described first embodiment, the manufacturing method of the present invention is applied to the extension portion of the source / drain region. However, in the present embodiment, the manufacturing method of the present invention is applied to the source / drain region and its extension. Applies to both extensions.

6 to 8 show a method of manufacturing a MISFET according to the second embodiment of the present invention.

In the manufacturing method of the present embodiment, the steps up to forming the extension portions of the source / drain regions are performed by the same method as the manufacturing method of the first embodiment described above.

That is, as shown in FIG. 1, after a thermal oxidation layer and a polysilicon layer containing impurities are formed on a semiconductor substrate (for example, a silicon substrate) 11, the silicon layer and the thermal oxidation layer are formed by PEP and RIE. By patterning, the gate insulating film 12 and the gate electrode 13 are formed on the semiconductor substrate 11.

After that, using the gate electrode 13 as a mask,
Self-aligningly, germanium ion (Ge ⁺ ) 14A
Is, for example, acceleration voltage 10 keV, dose amount 1 × 10
Ions are implanted into the surface region of the semiconductor substrate 11 under the condition of ¹⁴ cm ⁻² .

As a result, 10 n from the region where the germanium ions are implanted, for example, the surface position of the semiconductor substrate 11.
A semiconductor (for example, silicon) in a region up to a depth of about m is made amorphous, and the amorphous layer 15A is formed.
Becomes

Here, as a result of the ion implantation, 1 × 10 ¹³ c is formed on the semiconductor substrate 11 directly below the amorphous layer 15A.
m ^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, in the case of ion implantation under the above conditions, 5 × 10 5
Germanium (about ¹³ cm ⁻² ) is included.

Next, as shown in FIG. 2, the amorphous layer (FIG. 1) 15A in the surface region of the semiconductor substrate 11 is subjected to down-flow etching using a halogen-based reactive gas.
Only the semiconductor layer (for example, silicon crystal) is selectively etched to remove the amorphous layer 15A. As a result, a recess 16A having a depth of about 10 nm is formed in the surface region of the semiconductor substrate 11.

Next, as shown in FIG. 3, after removing the natural oxide film formed on the surface of the semiconductor substrate 11 by the dilute hydrofluoric acid treatment, the semiconductor substrate (wafer) 11 is immediately CVD-deposited.
Transport to equipment. Further, in the CVD apparatus, the semiconductor substrate 11 is subjected to hydrogen annealing at 600 ° C. for 3 minutes to remove the natural oxide film formed on the surface of the semiconductor substrate 11 during transportation.

Then, in the CVD apparatus, dichlorosilane was used.
(SiH2Cl2), hydrochloric acid (HCl), hydrogen (H2), and diborane (B2H6) mixed gas at 600 ° C., for example, 400, respectively.
Flow at a rate of 100, 14500, 100 sccm,
A conductive semiconductor layer (for example, a silicon layer) 17 containing boron is formed on the exposed portion (the surface of the recess 16A) of the semiconductor substrate 11.

The semiconductor layer 17 is formed to the extent that it fills the recess 16A, and as a result, the extension portion of the source / drain region having a steep profile with a depth of about 10 nm is formed.

Next, as shown in FIG. 6, the gate electrode 13
Side walls 21 are formed on the side walls. The sidewall 21 can be easily formed, for example, by forming an insulating layer on the entire surface of the semiconductor substrate 11 and then etching this insulating layer by RIE.

After that, the gate electrode 13 and the side wall 21 are used as a mask to self-align germanium ion (Ge ⁺ ) 14B, for example, at an acceleration voltage of 40 ke.
Ions are implanted into the surface region of the semiconductor substrate 11 under the conditions of V and a dose amount of 1 × 10 ¹⁴ cm ⁻² .

As a result, 50 n from the region where the germanium ions are implanted, for example, the surface position of the semiconductor substrate 11.
The semiconductor (for example, silicon) in the region up to the depth of about m is made amorphous, and the amorphous layer 15B is formed.
Becomes

Here, as a result of the ion implantation, 1 × 10 ¹³ c is formed on the semiconductor substrate 11 immediately below the amorphous layer 15B.
m ^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, in the case of ion implantation under the above conditions, 5 × 10 5
Germanium (about ¹³ cm ⁻² ) is included.

Next, as shown in FIG. 7, an amorphous layer (FIG. 6) 15B in the surface region of the semiconductor substrate 11 is formed by down-flow etching using a halogen-based reactive gas.
Only the semiconductor crystal (for example, silicon crystal) is selectively etched to remove the amorphous layer 15B. As a result, a recess 16B having a depth of about 50 nm is formed in the surface region of the semiconductor substrate 11.

Next, as shown in FIG. 8, after removing the natural oxide film formed on the surface of the semiconductor substrate 11 by the treatment with dilute hydrofluoric acid, the semiconductor substrate (wafer) 11 is immediately CVD-deposited.
Transport to equipment. Further, in the CVD apparatus, the semiconductor substrate 11 is subjected to hydrogen annealing at 600 ° C. for 3 minutes to remove the natural oxide film formed on the surface of the semiconductor substrate 11 during transportation.

Then, in the CVD apparatus, dichlorosilane was used.
(SiH2Cl2), hydrochloric acid (HCl), hydrogen (H2), and diborane (B2H6) mixed gas at 600 ° C., for example, 400, respectively.
Flow at a rate of 100, 14500, 500 sccm,
A conductive semiconductor layer (for example, a silicon layer) 22B containing boron is formed on the exposed portion (the surface of the recess 16B) of the semiconductor substrate 11.

The semiconductor layer 22B is formed to such an extent as to fill the recess 16B, and as a result, the main portion of the source / drain region having a depth of about 50 nm and a steep profile is formed.

A refractory metal (for example, nickel, cobalt, titanium, titanium nitride, etc.) is formed on the gate electrode 13, the source / drain regions 22B and the sidewalls 21. In addition, annealing is performed so that refractory metal and silicon (gate electrode 13 and source / drain region 2
2B) is thermally reacted with the gate electrode 13 and the source.
A silicide layer 23 is formed on each drain region 22B.

Thereafter, the unreacted refractory metal present in the region such as the sidewall 21 is removed by chemical treatment (salicide process: self-aligned silicide pr
ocess).

Through the above steps, a MISFET having a pn junction depth of 20 nm or less in the extension portion of the source / drain region is completed.

In the above description of the manufacturing method, germanium is used to form the amorphous layers 15A and 15B, but semiconductor atoms such as silicon may be used instead.

In the above description of the manufacturing method, the method of manufacturing the p-channel type MISFET has been described as a premise, but the present invention can naturally be applied to the method of manufacturing the n-channel type MISFET.

In this case, in the CVD process for forming the source / drain regions and the extension portions thereof, phosphine (PH3) or arsine (AsH3) is used instead of diborane (B2H6) as a reaction gas.

The present invention can also be applied to a method of manufacturing a MIS transistor in a CMOS device.

Also in the manufacturing method according to the present embodiment, it is possible to obtain the same effects as those of the manufacturing method of the first embodiment described above.

That is, the depth of 10 nm, the impurity concentration of 1 × 10 ²² cm ⁻³ , and the concentration gradient of 3 nm / decade required in the 50 nm generation (2011) of the international road map.
The extension part having the steep profile described above can be realized.

Further, it is formed by the manufacturing method of the present embodiment.
Is a source / drain region and its
1 × 10 on the pn junction interface of the extension part^Thirteen
cm ^-2Through 1 × 10¹⁵cm^-2Germanium (eg
For example, 5 × 10^Thirteencm^-2Contains germanium)
ing.

In addition to the difficulty of diffusion of germanium itself, the germanium is used when forming the source / drain regions and the extension portions thereof, that is, by CVD.
Conductive layer 1 in the depressions 16A, 16B by the method
When forming 7,22B or during subsequent annealing,
It has a barrier function of suppressing diffusion of impurities (for example, boron and phosphorus) in the semiconductor layers 17 and 22B into the semiconductor substrate 11.

That is, in the semiconductor layers 17 and 22B, C
Impurities are introduced by so-called in-situ doping during VD, but the diffusion of these impurities toward the semiconductor substrate 11 is suppressed by germanium, so that the profile in the depth direction of the extension portion of the source / drain region is further improved. Can be steep.

Here, the concentration of germanium is 1 ×.
If it is less than 10 ¹³ cm ^-2 , its barrier function deteriorates,
When the concentration of germanium exceeds 1 × 10 ¹⁵ cm ⁻² , the resistance of the extension portion of the source / drain region may increase due to deterioration of carrier mobility. Therefore, it is desired to keep the germanium concentration within the above range.

In the manufacturing method according to this embodiment, the conductive semiconductor layers 17 and 2 are formed in the depressions 16A and 16B.
Before forming 2B, a hydrogen anneal is performed to form the recess 16
The natural oxide film formed on the surfaces of A and 16B is removed. However, in reality, even if this hydrogen annealing is performed,
The natural oxide film formed on the surfaces of the depressions 16A and 16B cannot be completely removed.

Therefore, about 1 × 10 ¹⁴ cm ⁻² together with 1 × 10 ¹³ cm ^{−2 to} 1 × 10 ¹⁵ cm ⁻² of germanium is formed at the interface of the pn junction of the source / drain region of the MISFET and its extension. May contain oxygen.

Although this oxygen is not so much as germanium, it is formed in the recess 1 by the CVD method when forming the source / drain regions and the extension portions thereof.
When the conductive semiconductor layers 17 and 22B are formed in the 6A and 16B and during the subsequent annealing, the semiconductor layers 17 and 2 are
It has a barrier function of suppressing diffusion of impurities in 2B into the semiconductor substrate 11.

As described above, according to the method of manufacturing the semiconductor device of the present embodiment and the semiconductor device formed by this method, the shallow junction (especially MIS) having a constant depth is formed.
(Extension part of FET source / drain region)
Can be formed with good reproducibility.

[Third Embodiment] This embodiment is also an application example of the above-described first embodiment.

That is, in the above-described first embodiment, the manufacturing method of the present invention is applied to the extension portion of the source / drain region. However, in the present embodiment, the manufacturing method of the present invention is applied to the source / drain region and its extension. Applies to both extensions.

9 to 11 show a method of manufacturing a MISFET according to the third embodiment of the present invention.

In the manufacturing method of the present embodiment, the steps up to the ion implantation of germanium for forming the extension portions of the source / drain regions are performed by the same method as the manufacturing method of the first embodiment described above. .

First, as shown in FIG. 1, a thermal oxidation layer and a polysilicon layer containing impurities are formed on a semiconductor substrate (for example, a silicon substrate) 11, and then the silicon layer and the thermal oxidation layer are formed by PEP and RIE. By patterning, the gate insulating film 12 and the gate electrode 13 are formed on the semiconductor substrate 11.

After that, using the gate electrode 13 as a mask,
Self-aligningly, germanium ion (Ge ⁺ ) 14A
Is, for example, acceleration voltage 10 keV, dose amount 1 × 10
Ions are implanted into the surface region of the semiconductor substrate 11 under the condition of ¹⁴ cm ⁻² .

As a result, 10 n from the region where the germanium ions are implanted, for example, the surface position of the semiconductor substrate 11.
A semiconductor (for example, silicon) in a region up to a depth of about m is made amorphous, and the amorphous layer 15A is formed.
Becomes

Here, as a result of the ion implantation, the semiconductor substrate 11 immediately below the amorphous layer 15A has a dose of 1 × 10 ¹³ c.
m ^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, in the case of ion implantation under the above conditions, 5 × 10 5
Germanium (about ¹³ cm ⁻² ) is included.

Next, as shown in FIG. 9, the gate electrode 13
Side walls 21 are formed on the side walls. The sidewall 21 can be easily formed, for example, by forming an insulating layer on the entire surface of the semiconductor substrate 11 and then etching this insulating layer by RIE.

After that, the gate electrode 13 and the side wall 21 are used as a mask, and the germanium ion (Ge ⁺ ) 14B is self-aligned with, for example, an accelerating voltage of 40 ke.
Ions are implanted into the surface region of the semiconductor substrate 11 under the conditions of V and a dose amount of 1 × 10 ¹⁴ cm ⁻² .

As a result, 50 n from the region where the germanium ions are implanted, for example, the surface position of the semiconductor substrate 11.
A semiconductor (for example, silicon) in a region up to a depth of about m is amorphized, and the amorphous layer 15C is formed.
Becomes

Here, as a result of ion implantation, 1 × 10 ¹³ c is formed in the semiconductor substrate 11 immediately below the amorphous layer 15C.
m ^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, in the case of ion implantation under the above conditions, 5 × 10 5
Germanium (about ¹³ cm ⁻² ) is included.

Next, as shown in FIG. 10, an amorphous layer (FIG. 9) 15 in the surface region of the semiconductor substrate 11 is formed by down-flow etching using a halogen-based reactive gas.
Only A and 15C are selectively etched with respect to a semiconductor crystal (for example, silicon crystal) to form an amorphous layer 1
5A and 15C are removed. As a result, the surface region of the semiconductor substrate 11 has two kinds of depths (about 10 nm and 50 nm).
A depression 16C having a degree) is formed.

Next, as shown in FIG. 11, after removing the natural oxide film formed on the surface of the semiconductor substrate 11 by the dilute hydrofluoric acid treatment, the semiconductor substrate (wafer) 11 is immediately subjected to CV.
Transport to device D. Further, in the CVD apparatus, the semiconductor substrate 11 is subjected to hydrogen annealing at 600 ° C. for 3 minutes to remove the natural oxide film formed on the surface of the semiconductor substrate 11 during transportation.

Then, in the CVD apparatus, dichlorosilane was used.
(SiH2Cl2), hydrochloric acid (HCl), hydrogen (H2), and diborane (B2H6) mixed gas at 600 ° C., for example, 400, respectively.
Flow at a rate of 100, 14500, 100 sccm,
A conductive semiconductor layer (for example, a silicon layer) 22C containing boron is formed on the exposed portion (the surface of the recess 16C) of the semiconductor substrate 11.

The semiconductor layer 22C is formed to such an extent that it fills the depression 16C, and as a result, two kinds of depths (10
nm and about 50 nm), and the source / drain regions having steep profiles and their extension portions are formed.

A refractory metal (eg, nickel, cobalt, titanium, titanium nitride, etc.) is formed on the gate electrode 13, the source / drain regions 22C and the sidewalls 21. In addition, annealing is performed so that refractory metal and silicon (gate electrode 13 and source / drain region 2
2C) is thermally reacted with the gate electrode 13 and the source.
A silicide layer 23 is formed on each of the drain regions 22C.

After that, the unreacted refractory metal existing in the region such as the sidewall 21 is removed by chemical treatment (salicide process: self-aligned silicide pr
ocess).

Through the above steps, the MISFET having the pn junction depth of the extension portion of the source / drain region of 20 nm or less is completed.

Although germanium is used to form the amorphous layers 15A and 15C in the above description of the manufacturing method, semiconductor atoms such as silicon may be used instead.

Further, in the above description of the manufacturing method, the manufacturing method of the p-channel type MISFET has been described as a premise, but the present invention can of course be applied to the manufacturing method of the n-channel type MISFET.

In this case, in the CVD process for forming the source / drain regions and the extension portions thereof, phosphine (PH3) or arsine (AsH3) is used instead of diborane (B2H6) as a reaction gas.

The present invention can also be applied to a method of manufacturing a MIS transistor in a CMOS device.

Also in the manufacturing method of the present embodiment, the same effect as that of the manufacturing method of the above-described first embodiment can be obtained.

That is, the depth of 10 nm, the impurity concentration of 1 × 10 ²² cm ⁻³ and the concentration gradient of 3 nm / decade required in the 50 nm generation (2011) of the international road map.
The extension part having the steep profile described above can be realized.

Further, the MISFET formed by the manufacturing method according to the present embodiment has 1 × 1 at the interface of the pn junction of the source / drain region and its extension part.
0 ^{1 3} cm ^-2 to 1 × ¹⁰ 15 ^{cm -2} of germanium (e.g., germanium 5 × ¹⁰ 13 ^{cm -2)} is included.

This germanium is less likely to diffuse itself, and in addition, when forming the source / drain regions and the extension portions thereof, that is, in the CVD.
That the impurities (for example, boron, phosphorus, etc.) in the semiconductor layer 22C are prevented from diffusing into the semiconductor substrate 11 when the conductive semiconductor layer 22C is formed in the recess 16C by the method or at the time of subsequent annealing. Has a barrier function.

That is, impurities are introduced into the semiconductor layer 22C by so-called in-situ doping during CVD, but the diffusion of these impurities toward the semiconductor substrate 11 is
Since it is suppressed by germanium, the profile of the source / drain region and its extension in the depth direction can be made steeper.

Here, the concentration of germanium is 1 ×.
If it is less than 10 ¹³ cm ^-2 , its barrier function deteriorates,
When the concentration of germanium exceeds 1 × 10 ¹⁵ cm ⁻² , the resistance of the extension portion of the source / drain region may increase due to deterioration of carrier mobility. Therefore, it is desired to keep the germanium concentration within the above range.

Further, in the manufacturing method according to the present embodiment, hydrogen annealing is performed to remove the natural oxide film formed on the surface of the recess 16C before forming the conductive semiconductor layer 22C in the recess 16C. is doing. But in reality,
Even if this hydrogen annealing is performed, the natural oxide film formed on the surface of the recess 16C cannot be completely removed.

Therefore, about 1 × 10 ¹⁴ cm ⁻² together with 1 × 10 ¹³ cm ^{−2 to} 1 × 10 ¹⁵ cm ⁻² of germanium are formed at the pn junction interface of the source / drain region of the MISFET and its extension. May contain oxygen.

This oxygen, though not so much as in germanium, is used when forming the source / drain regions and the extension portions thereof, that is, by the CVD method.
It has a barrier function of suppressing diffusion of impurities in the semiconductor layer 22C into the semiconductor substrate 11 when the conductive semiconductor layer 22C is formed in the 6C and subsequent annealing.

As described above, according to the method of manufacturing the semiconductor device of the present embodiment and the semiconductor device formed by this method, the shallow junction (especially, the source / drain of the MISFET is formed). The extension part of the area) can be formed with good reproducibility.

[Fourth Embodiment] FIGS. 12 to 17 show
It shows a method of manufacturing a MISFET according to the fourth embodiment of the present invention.

First, as shown in FIGS. 12 and 13, a thermal oxide layer and a polysilicon layer containing impurities are formed on a semiconductor substrate (eg, a silicon substrate) 11, and then PEP is performed.
Then, the silicon layer and the thermal oxide layer are patterned by RIE to form the gate insulating film 12 and the gate electrode 13 on the semiconductor substrate 11.

After that, using the gate electrode 13 as a mask,
Self-aligningly, germanium ion (Ge ⁺ ) 14A
Is, for example, acceleration voltage 10 keV, dose amount 1 × 10
Ions are implanted into the semiconductor substrate 11 from a direction of about 60 ° with respect to the surface of the semiconductor substrate 11 under the condition of ¹⁴ cm ⁻² .

As a result, a region in which germanium ions are implanted, for example, 5 nm from the surface position of the semiconductor substrate 11
A semiconductor (for example, silicon) in a region up to a position of about a depth is amorphized to be an amorphous layer 15A.

Here, as a result of ion implantation, 1 × 10 ¹³ c is formed on the semiconductor substrate 11 immediately below the amorphous layer 15A.
m ^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, in the case of ion implantation under the above conditions, 5 × 10 5
Germanium (about ¹³ cm ⁻² ) is included.

In this embodiment, germanium is ion-implanted into the surface of the semiconductor substrate 11 from an oblique direction. In this case, the concentration peak value can be set at a shallower position than in the case where germanium is ion-implanted from the direction perpendicular to the surface of the semiconductor substrate 11. That is, it is possible to form a recess that is shallower than the recess formed by the method of the first embodiment.

Therefore, according to the method of this embodiment, the technique of controlling the etching amount by the etching time (for example, USP 5,864,161, USP 6,018,1) is used.
85, JP-A-11-186542, JP-A-09-82.
957, JP-A-08-153688, etc.), a shallow junction can be formed with good control.

Next, as shown in FIG. 14, only the amorphous layer (FIGS. 12 and 13) 15A in the surface region of the semiconductor substrate 11 is subjected to semiconductor crystal (down) by down-flow etching using a halogen-based reactive gas. For example, the amorphous layer 15A is removed by selectively etching the silicon crystal). As a result, a recess 16A having a depth of about 5 nm is formed in the surface region of the semiconductor substrate 11.

Next, as shown in FIG. 15, after removing the natural oxide film formed on the surface of the semiconductor substrate 11 by the dilute hydrofluoric acid treatment, the semiconductor substrate (wafer) 11 is immediately subjected to CV.
Transport to device D. Further, in the CVD apparatus, the semiconductor substrate 11 is subjected to hydrogen annealing at 600 ° C. for 3 minutes to remove the natural oxide film formed on the surface of the semiconductor substrate 11 during transportation.

Then, in the CVD apparatus, dichlorosilane was used.
(SiH2Cl2), hydrochloric acid (HCl), hydrogen (H2), and diborane (B2H6) mixed gas at 600 ° C., for example, 400, respectively.
Flow at a rate of 100, 14500, 100 sccm,
A conductive semiconductor layer (for example, a silicon layer) 17 containing boron is formed on the exposed portion (the surface of the recess 16A) of the semiconductor substrate 11.

The semiconductor layer 17 is formed to the extent that it fills the recess 16A, and as a result, has a depth of about 5 nm,
The extension portion of the source / drain region having a steep profile is formed.

Next, as shown in FIG. 16, the gate electrode 1
A side wall 21 is formed on the side wall of No. 3. The sidewall 21 can be easily formed, for example, by forming an insulating layer on the entire surface of the semiconductor substrate 11 and then etching this insulating layer by RIE.

A resist layer is formed on the entire surface of the semiconductor substrate 11, and the resist layer is patterned by photolithography. The patterned resist layer (resist pattern) is, for example, an n-channel MISF.
It covers the region where ET is formed and serves as a mask for ion implantation performed thereafter.

That is, the resist pattern and the gate electrode 13
By ion implantation using the sidewalls 21 as a mask, for example, boron ions (B ⁺ ) are accelerated with an acceleration voltage of 3 ke.
It is self-alignedly injected into the semiconductor substrate 11 under the conditions of V and a dose amount of 4 × 10 ¹⁵ cm ⁻² . Then, after that, high-speed temperature rising / falling annealing is performed to form the source / drain regions (main part) 22A in the semiconductor substrate 11.

Next, as shown in FIG. 17, the gate electrode 1
3, the source / drain regions 22A and the sidewalls 21 on the refractory metal (eg, nickel, cobalt,
Titanium, titanium nitride, etc.) is formed. Further, annealing is performed to thermally react the refractory metal with silicon (the gate electrode 13 and the source / drain regions 22A) to form the silicide layers 23 on the gate electrode 13 and the source / drain regions 22A, respectively.

Thereafter, the unreacted refractory metal present in the region such as the sidewall 21 is removed by chemical treatment (salicide process: self-aligned silicide pr
ocess).

Through the above steps, a MISFET having a pn junction depth of 20 nm or less in the extension portion of the source / drain region is completed.

In the above description of the manufacturing method, germanium is used to form the amorphous layer 15A, but instead of this, a semiconductor atom such as silicon may be used.

In the above description of the manufacturing method, the manufacturing method of the p-channel type MISFET has been described as a premise, but the present invention can of course be applied to the manufacturing method of the n-channel type MISFET.

In this case, the extension portion is formed.
In the CVD process for diborane as a reaction gas
Instead of (B2H6), phosphine (PH3) or arsine (AsH3)
To use. Also, the source / drain regions are formed.
In the ion implantation process for
Use at least one of phosphorus and arsenic ions
It The conditions for phosphorus ion implantation are: acceleration voltage 5 keV,
Dose 1 × 10¹⁵cm ^-2And the arsenic ion implantation
The conditions are an acceleration voltage of 40 keV and a dose amount of 5 × 10. ¹⁵c
m^-2And

The present invention can also be applied to a method of manufacturing a MIS transistor in a CMOS device.

According to the manufacturing method of the present embodiment, it is possible to obtain the same effects as those of the manufacturing method of the first embodiment described above. That is, a shallow junction having a substantially constant depth (especially MISF
ET source / drain region extension)
Can be formed with good reproducibility.

In the manufacturing method of this embodiment, germanium used for amorphization is ion-implanted from an oblique direction. Therefore, as shown in FIG. 18, the extension portion 17A in the source / drain region can be easily formed immediately below the gate electrode 13. In addition, 17B shows the extension part when ions are implanted from the vertical direction under the same conditions.

The ratio (yj / x) of the depth xj of the pn junction of the extension portion of the source / drain region and the length yj of the extension portion which enters directly below the gate electrode 13.
j) is 0.6-0.7 in the above-mentioned first embodiment, but can be set to a value of 1.0 or more in this embodiment.

This high ratio means that MISFE
Since T means that the current driving force is high, the manufacturing method of the present embodiment can easily form a MISFET having a high current driving force.

[Fifth Embodiment] In this embodiment, a MISFET having a shallow junction and a MISSF having a deep junction are used.
It relates to a method of manufacturing ET.

19 to 23 show a method of manufacturing a MISFET according to the fifth embodiment of the present invention.

First, as shown in FIG. 19, an STI (Shallow Trunk) is formed in a semiconductor substrate (for example, a silicon substrate) 11.
An element isolation insulating layer 20 having an enchIsolation structure is formed.

On the semiconductor substrate 11, a thermal oxide layer, a polysilicon layer containing impurities, and a silicon nitride film are deposited directly on the polysilicon layer. The silicon nitride film is an insulating film that serves as a gate cap and can be replaced with a silicon oxide film.

The silicon nitride film, the silicon layer and the thermal oxide layer are patterned by PEP and RIE to form the gate insulating film 12, the gate electrode 13 and the cap film on the semiconductor substrate 11. In addition, after the gate polysilicon and the substrate are oxidized by the post-gate oxidation step, the gate sidewalls 13-2 are formed on the side surfaces of the gate by etching back by RIE.

After that, using the resist pattern 18,
The region where the MISFET, which is required to operate at high speed, is formed is covered. Then, in the region where the MISFET such as the MISFET of the I / O portion which requires deep junction is formed,
Germanium ions (Ge ⁺ ) 14 are self-aligned using the gate electrode 13 and the resist pattern 18 as a mask.
A is, for example, acceleration voltage 50 keV, dose amount 1 × 1
Ions are implanted into the semiconductor substrate 11 from the direction perpendicular to the surface of the semiconductor substrate 11 under the condition of 0 ¹⁴ cm ⁻² .

As a result, a region where the germanium ions are implanted, for example, 10 n from the surface position of the semiconductor substrate 11
A semiconductor (for example, silicon) in a region up to a depth of about m is made amorphous, and the amorphous layer 15D is formed.
Becomes

Here, as a result of ion implantation, 1 × 10 ¹³ c is formed on the semiconductor substrate 11 immediately below the amorphous layer 15D.
m ^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, in the case of ion implantation under the above conditions, 5 × 10 5
Germanium (about ¹³ cm ⁻² ) is included.

Next, as shown in FIG. 20A, using the resist pattern 19, a MIS requiring deep bonding.
Cover the area where the FET is formed. Then, using the gate electrode 13 and the resist pattern 19 as a mask in the region where the MISFET that requires high-speed operation is formed,
Self-aligningly, germanium ion (Ge ⁺ ) 14A
Is, for example, acceleration voltage 10 keV, dose amount 1 × 10
Ions are implanted into the semiconductor substrate 11 from a direction of about 60 ° with respect to the surface of the semiconductor substrate 11 under the condition of ¹⁴ cm ⁻² . Subsequently, as shown in FIG. 20 (b), −60 °
Also from the direction of, the germanium ion (Ge ⁺ ) 14C is ion-implanted.

As a result, the region where the germanium ions are implanted, for example, 5 nm from the surface position of the semiconductor substrate 11
A semiconductor (for example, silicon) in a region up to a position of about a depth is made amorphous and becomes an amorphous layer 15E.

Here, as a result of ion implantation, 1 × 10 ¹³ c is formed in the semiconductor substrate 11 immediately below the amorphous layer 15E.
m ^{−2 to} 1 × 10 ¹⁵ cm ⁻² germanium (for example, in the case of ion implantation under the above conditions, 5 × 10 5
Germanium (about ¹³ cm ⁻² ) is included.

MISFETs required to operate at high speed
In the region where the
Since the ion implantation is performed obliquely to the surface of No. 1, the amorphous layer 15E sufficiently penetrates directly below the gate electrode 13.

Next, as shown in FIG. 21, the amorphous layer (FIG. 20) 1 in the surface region of the semiconductor substrate 11 was down-etched by down-flow etching using a halogen-based reactive gas.
Only 5D and 15E are selectively etched with respect to a semiconductor crystal (for example, a silicon crystal) to form an amorphous layer 1
Remove 5D and 15E. As a result, recesses 16D and 16E having a depth of about 10 nm and 5 nm are formed in the surface region of the semiconductor substrate 11.

Next, as shown in FIG. 22, after removing the natural oxide film formed on the surface of the semiconductor substrate 11 by the dilute hydrofluoric acid treatment, the semiconductor substrate (wafer) 11 is immediately subjected to CV.
Transport to device D. Further, in the CVD apparatus, the semiconductor substrate 11 is subjected to hydrogen annealing at 600 ° C. for 3 minutes to remove the natural oxide film formed on the surface of the semiconductor substrate 11 during transportation.

Then, in the CVD apparatus, dichlorosilane was used.
(SiH2Cl2), hydrochloric acid (HCl), hydrogen (H2), and diborane (B2H6) mixed gas at 600 ° C., for example, 400, respectively.
Flow at a rate of 100, 14500, 100 sccm,
The exposed portion of the semiconductor substrate 11 (the depressions 16D, 16
A conductive semiconductor layer (for example, a silicon layer) 17 containing boron is formed on the surface (E).

The semiconductor layer 17 is formed to the extent that it fills the depression 16D, and is required to operate at high speed.
In the region where T is formed, the semiconductor layer 17 is formed to the extent that it exceeds the initial height of the substrate surface, but the depth of the extension portion is substantially not affected.

Next, as shown in FIG. 23, the gate electrode 1
3 side wall, that is, the side wall 2 outside the gate side wall 13-2.
1 is formed. The side wall 21 can be easily formed, for example, by forming an insulating layer on the entire surface of the semiconductor substrate 11 and then etching this insulating layer by RIE.

Further, the cap film 13 on the gate electrode 13
After -1 is selectively removed by a wet process, a region where a MISFET that requires high-speed operation is formed is covered with a resist layer. Further, ion implantation of boron (B ⁺ ) is performed using the gate electrode 13 and the gate sidewall 21 as a mask in a region where a MISFET such as a MISFET in the I / O portion, which requires a deep junction, is formed.

Further, the region where the MISFET such as MISFET of the I / O portion where a deep junction is required is formed is covered with a resist layer, and the gate electrode 13 is applied to the region where the MISFET requiring high speed operation is formed. Further, boron (B ⁺ ) ion implantation is performed using the gate sidewall 21 as a mask.

Then, when high-speed temperature rising / falling annealing is performed thereafter, the source / drain regions 22D and 22E are formed in the semiconductor substrate 11.

After that, a refractory metal (for example, nickel, cobalt, titanium, titanium nitride, etc.) is formed on the gate electrode 13, the source / drain regions 22D and 22E, and the sidewall 21. Further, annealing is performed to thermally react the refractory metal with silicon (the gate electrode 13 and the source / drain regions 22D and 22E) to form the silicide layers 23 on the gate electrode 13 and the source / drain regions 22D and 22E, respectively. To do.

Thereafter, the unreacted refractory metal present in the region such as the sidewall 21 is removed by chemical treatment (salicide process: self-aligned silicide pr
ocess).

Through the above steps, sources with different depths
A plurality of types of MISFETs having a drain region and its extension portion are completed.

Although germanium is used to form the amorphous layers 15D and 15E in the above description of the manufacturing method, semiconductor atoms such as silicon may be used instead of germanium.

In the above description of the manufacturing method, the manufacturing method of the p-channel type MISFET has been described as a premise, but the present invention can naturally be applied to the manufacturing method of the n-channel type MISFET.

In this case, in the CVD process for forming the extension portion, diborane as a reaction gas is used.
Instead of (B2H6), phosphine (PH3) or arsine (AsH3)
To use. In the ion implantation process for forming the source / drain regions, instead of boron ions,
At least one of phosphorus ion and arsenic ion is used.

The present invention can also be applied to a method of manufacturing a MIS transistor in a CMOS device.

According to the manufacturing method of the present embodiment, it is possible to obtain the same effects as those of the manufacturing method of the first embodiment described above. That is, a shallow junction having a substantially constant depth (especially MISF
ET source / drain region extension)
Can be formed with good reproducibility.

Further, in the manufacturing method of the present embodiment, two types of junctions having different depths can be formed at the same time by changing the ion implantation conditions of germanium ions. Therefore, it is formed in one chip, for example,
M that requires deep junction such as MISFET in I / O part
The present invention can be simultaneously applied to the ISFET and the MISFET that is required to operate at high speed.

[Others] The ions used for ion implantation for amorphization are not limited to semiconductor atoms such as germanium and silicon as long as they are impurities that do not act electrically.

[0182]

As described above, according to the method of manufacturing a semiconductor device of the present invention, the surface region of the semiconductor substrate is made amorphous by ion implantation of impurities that do not act electrically, such as germanium and silicon. By etching the converted surface region selectively with respect to the semiconductor substrate, a very shallow depression is formed.

The depth of the amorphized surface region can be controlled more accurately and easily than the depth by etching, and the amorphized region can be formed on the semiconductor substrate (eg, silicon crystal). On the other hand, since a sufficiently large etching selection ratio can be secured, it becomes possible to form a junction having a substantially constant depth with good reproducibility.

In the ion implantation of semiconductor atoms, by implanting semiconductor atoms from an oblique direction, for example, the ratio (yj / xj) of the junction depth xj to the junction extension yj directly below the gate electrode is changed. The value can be made larger than that of the conventional example in which the depression is formed only by etching, and it can contribute to the improvement of the current driving force of the MISFET.

Furthermore, by changing the conditions for ion implantation of semiconductor atoms, it becomes possible to simultaneously form a plurality of junctions having different depths.

Further, in the MISFET of the present invention, germanium exists at the junction interface. Since germanium forms a junction, it can suppress the diffusion of impurities introduced into the semiconductor layer and make the concentration profile of the junction steep.

[Brief description of drawings]

FIG. 1 is a sectional view showing a manufacturing method according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a manufacturing method according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing the manufacturing method according to the first embodiment of the invention.

FIG. 5 is a sectional view showing the manufacturing method according to the first embodiment of the invention.

FIG. 6 is a sectional view showing a manufacturing method according to the second embodiment of the present invention.

FIG. 7 is a sectional view showing the manufacturing method according to the second embodiment of the invention.

FIG. 8 is a sectional view showing the manufacturing method according to the second embodiment of the invention.

FIG. 9 is a sectional view showing the manufacturing method according to the third embodiment of the invention.

FIG. 10 is a sectional view showing the manufacturing method according to the third embodiment of the invention.

FIG. 11 is a sectional view showing the manufacturing method according to the third embodiment of the present invention.

FIG. 12 is a sectional view showing the manufacturing method according to the fourth embodiment of the present invention.

FIG. 13 is a sectional view showing the manufacturing method according to the fourth embodiment of the present invention.

FIG. 14 is a sectional view showing a manufacturing method according to the fourth embodiment of the present invention.

FIG. 15 is a sectional view showing the manufacturing method according to the fourth embodiment of the present invention.

FIG. 16 is a sectional view showing the manufacturing method according to the fourth embodiment of the present invention.

FIG. 17 is a sectional view showing the manufacturing method according to the fourth embodiment of the present invention.

FIG. 18 is a cross-sectional view showing an extension part manufactured according to a fourth embodiment of the present invention.

FIG. 19 is a sectional view showing the manufacturing method according to the fifth embodiment of the present invention.

FIG. 20 is a sectional view showing the manufacturing method according to the fifth embodiment of the present invention.

FIG. 21 is a sectional view showing the manufacturing method according to the fifth embodiment of the present invention.

FIG. 22 is a sectional view showing the manufacturing method according to the fifth embodiment of the present invention.

FIG. 23 is a sectional view showing the manufacturing method according to the fifth embodiment of the present invention.

[Explanation of symbols]

11: Semiconductor substrate, 12: Gate insulating film, 13: Gate electrode, 14A, 14B, 14C: Germanium ion, 15A, 15B, 15C, 15D, 15E: Amorphous layer, 16A, 16B, 16C, 16D, 16E: Recess, 17, 17A, 17B: Extension part, 18, 19: Resist layer, 20: Element isolation insulating layer, 21: Side wall, 22A, 22B, 22C, 22D, 22E: Source
Drain region, 23: silicide layer.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 27/092 29/78 F term (reference) 5F048 AA01 AB03 AC01 AC03 BA01 BB05 BB08 BB12 BC06 BC19 BG14 DA23 5F140 AA13 AB03 BA01 BE07 BF04 BF11 BF18 BG08 BG34 BG38 BG45 BG51 BG53 BH06 BH13 BH14 BH15 BH22 BH30 BJ01 BJ08 BK02 BK09 BK10 BK11 BK13 BK18 BK21 BK34 BK39 CB04 CF04

Claims (17)

[Claims] 1. A semiconductor substrate, comprising: a MISFET formed in a surface region of the semiconductor substrate;
P of extension part of source / drain region of ET
A semiconductor device in which germanium is contained in the interface of the n-junction. 2. A semiconductor substrate and a MISFET formed on a surface region of the semiconductor substrate, wherein the MISSF is provided.
A semiconductor device comprising germanium in at least a part of an interface of a pn junction of a source / drain region of ET. 3. The concentration of germanium is 1 × 10.
3. The semiconductor device according to claim 1, wherein the semiconductor device is set within a range of ¹³ cm ^{−2 to} 1 × 10 ¹⁵ cm ⁻² . 4. The semiconductor device according to claim 1, wherein the interface of the pn junction contains oxygen together with the germanium. 5. The depth of the extension portion is 20.
The semiconductor device according to claim 1, wherein the semiconductor device has a thickness of not more than nm. 6. The extension unit includes the MIS.
The semiconductor device according to claim 1, wherein the semiconductor device is arranged immediately below a sidewall formed on the sidewall of the gate electrode of the FET. 7. The semiconductor device according to claim 1, wherein the germanium is contained in all of the interfaces of the pn junction of the source / drain regions. 8. A step of implanting semiconductor atoms into a surface region of a semiconductor substrate by ion implantation, and selectively etching the surface region amorphized by the semiconductor atoms with respect to the semiconductor substrate to form a semiconductor substrate on the semiconductor substrate. A method of manufacturing a semiconductor device, comprising: forming a depression; and filling the depression with a semiconductor layer containing impurities. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the semiconductor atom is germanium or silicon. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the depth of the depression is determined by an acceleration voltage and a dose amount of the semiconductor atom. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the recess is formed by downflow etching. 12. The ion implantation is performed in a self-aligned manner by using a gate electrode of a MISFET formed on the semiconductor substrate as a mask, and the semiconductor layer is formed by the MISFE.
9. The method of manufacturing a semiconductor device according to claim 8, which functions as a source / drain region of T. 13. The method of manufacturing a semiconductor device according to claim 12, wherein the semiconductor atoms are implanted obliquely with respect to the surface of the semiconductor substrate. 14. A step of forming a gate electrode on a semiconductor substrate, a step of implanting semiconductor atoms into a surface region of the semiconductor substrate in a self-aligned manner by ion implantation using the gate electrode as a mask, A step of selectively etching the amorphized surface region with respect to the semiconductor substrate to form a recess in the semiconductor substrate, and filling the semiconductor layer containing impurities in the recess to extend the source / drain regions. And a step of forming a portion. 15. A step of forming a sidewall on a side wall of the gate electrode after forming the extension part, and an impurity self-implanted in a surface region of the semiconductor substrate by ion implantation using the gate electrode and the side wall as a mask. 15. The method for manufacturing a semiconductor device according to claim 14, further comprising the step of implanting in a conformal manner to form a main part of the source / drain regions. 16. A step of forming a side wall on a side wall of the gate electrode after forming the extension part, and a step of forming semiconductor atoms in a surface region of the semiconductor substrate by ion implantation using the gate electrode and the side wall as a mask. Implanting in a self-aligned manner, selectively etching the surface region amorphized by the semiconductor atoms with respect to the semiconductor substrate to form a recess in the semiconductor substrate, and impurities in the recess. 15. The method of manufacturing a semiconductor device according to claim 14, further comprising the step of filling the included semiconductor layer and forming a main part of the source / drain region. 17. A step of forming a gate electrode on a semiconductor substrate; a step of implanting semiconductor atoms in a surface region of the semiconductor substrate in a self-aligned manner by ion implantation using the gate electrode as a mask; Forming sidewalls on the sidewalls; implanting semiconductor atoms in a self-aligned manner into the surface region of the semiconductor substrate by ion implantation using the gate electrode and the sidewalls as a mask; and amorphizing by the semiconductor atoms. A step of selectively etching the surface region with respect to the semiconductor substrate to form a recess in the semiconductor substrate; and a step of forming a source / drain region including an extension portion by filling the recess with a semiconductor layer containing impurities. And a step of forming the semiconductor device.