JP2003108079A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the degradation of display characteristics caused by stripes occurring in division boundary positions even when increasing the number of degrees of freedom of display area selection for picture-in-picture or the like. SOLUTION: A source driver SD1 for main video screen and a source driver SD2 for superimposition or picture-in-picture share signal lines SL1 to SLn, and a control part 3 outputs video signal sampling start signals SSP1 and SSP2 to the source drivers SD1 and SD2 with a lag between them so that the signal line SLx (1<=x<=N) which the source driver SD1 has finished driving may be driven further by the source driver SD2. Therefore, the main video screen given by the source driver SD1 can be overwritten on a screen for superposition or picture-in-picture given by the source driver SD2. In this case, the source drivers SD1 and SD2 themselves are not divided so as not to generate stripes in division boundary positions on the display screen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a display device such as a liquid crystal display device capable of superimposing a specific character or character or performing a picture-in-picture on a small image screen.

[0002]

2. Description of the Related Art Conventionally, the following image display devices have been proposed as display devices capable of performing picture-in-picture.

FIG. 7 is a block diagram showing a main configuration of a conventional liquid crystal display device. In FIG. 7, the liquid crystal display device 1
00 is a display unit 101 for displaying an image and a display unit 1
Signal line drive circuits SDV1 to SDV4 for driving the signal line group 01
A scanning line driving circuit GDV1, 2 for driving the scanning line group of the display unit 101, and a video signal selecting circuit 1 for selectively outputting a video signal input to the signal line driving circuit SDV1-4.
02 and.

The display area of the display unit 101 is divided into a plurality of display areas 1011 to 1014, for example.
The display area 1011 has a signal line group SL orthogonal to each other.
The display area 1012 includes a signal line group SLG2 and a scan line group GLG2 that include G1 and a scan line group GLG1 and are orthogonal to each other.
The display area 1013 includes a signal line group SLG3 and a scanning line group GLG3 which are orthogonal to each other.
14 is a signal line group SLG4 and a scanning line group G orthogonal to each other.
LG4 and. Of these signal line groups, a display element is provided in a portion surrounded by two adjacent signal lines and two adjacent scanning lines, and this display element constitutes one picture element. A large number of rows and columns are arranged in a matrix and displayed on the screen.

The signal line drive circuit SDV1 is a signal line group SLG.
1, the signal line drive circuit SDV2 is connected to one end of the signal line group SLG2, and the signal line drive circuit SDV3 is connected to one end of the signal line group SLG2.
Is connected to one end of the signal line group SLG3, and the signal line drive circuit SDV4 is connected to one end of the signal line group SLG4.
On the other hand, the video signal sampling clock signal SCK and the video signal sampling start signal SSP are externally input to the signal line drive circuits SDV1 to SDV4, respectively. Each of the signal line drive circuits SDV1 to SDV4 controls sampling of the data signal to the signal line based on the video signal sampling clock signal SCK and the video signal sampling start signal SSP.

The scanning line drive circuit GDV1 is composed of the scanning line group GLG.
1, and the scanning line drive circuit GDV2 is connected to one end of the scanning line group GLG2. Scan line drive circuit G
The scan selection clock signal GC is applied to each of DV1 and DV2.
K and the scanning line selection start signal GSP are input from the outside. The scanning line drive circuits GDV1 and GDV2 are controlled to sequentially output scanning signals to the respective scanning lines based on the scanning selection clock signal GCK and the scanning line selection start signal GSP.

A video signal Video1 for the main video screen and a video signal Video2 for the picture-in-picture video screen are input to the video signal selection circuit 102,
Either of the video signals Video1 and Video2 can be selectively output and supplied to the signal line drive circuits SDV1 to SDV4.

Here, for example, in the case of performing picture-in-picture in the display area 1014, FIG.
This will be described in detail with reference to the timing chart of each signal of the liquid crystal display device 100 shown in FIG.

The main video signal Video1 shown in FIG. 8A which is selectively output by the video signal selection circuit 102 is supplied to the signal line drive circuits SDV1 to SDV3, and the video signal is supplied to the signal line drive circuit SDV4. The picture signal Video2 for picture-in-picture shown in FIG. 8B, which is selectively output by the selection circuit 102, is supplied.

The video signal sampling clock signal SCK shown in FIG. 8C and the video signal sampling start signal SSP shown in FIG. 8D are supplied to the respective signal line drive circuits SDV1 to SDV4. There is.

A scanning line selection clock signal GCK and a scanning line selection start signal GSP are supplied to the scanning line drive circuits GDV1 and GDV2, respectively.

From the above, the display areas 1011 to 1013
Then, the main video by the video signal Video1 is displayed,
In the display area 1014 of the small screen, a video based on the picture-in-picture video signal Video2 is displayed. In this way, an image can be displayed on the main video screen by the picture-in-picture function.

It should be noted that it is possible to assume that an image is displayed by the picture-in-picture function at a new screen position between the display areas 1013 and 1014, but in this case,
This can be dealt with by further increasing the number of divisions of the signal line drive circuit and performing image display by the picture-in-picture function on the increased division signal line drive circuit.
Moreover, by increasing the number of divisions of the signal line driving circuit, the degree of freedom in selecting the position of the display area when performing picture-in-picture increases.

[0014]

However, as described above, increasing the number of divisions of the signal line drive circuit is not preferable from the viewpoint of display characteristics because stripes are likely to appear at the division boundary positions. That is, in the above-mentioned conventional split drive method,
The degree of freedom in selecting a display area when displaying an image by the picture-in-picture function and the display characteristic are in a conflicting relationship. That is, if the degree of freedom in selecting the display area is increased, stripes are more likely to appear as a display characteristic.

The present invention has been made in view of the above circumstances, and even if the degree of freedom in selecting a display area when performing picture-in-picture or the like is increased, the display characteristics due to stripes at division boundary positions are not deteriorated. An object is to provide a display device.

[0016]

A display device according to the present invention comprises a scanning line driving circuit for sequentially supplying scanning signals to a plurality of scanning lines and a plurality of columns arranged so as to intersect the plurality of scanning lines. In a display device having a signal line drive circuit for supplying a video signal (video data) to a signal line and displaying a screen by a video signal output according to a scanning signal output, the signal line drive circuit is provided for at least a main video screen. A first signal line drive circuit,
The second signal line drive circuit for the sub-picture screen is configured, and the first signal line drive circuit and the second signal line drive circuit share the same one or a plurality of signal lines. To drive the signal line (for example, sampling operation), and to control the second signal line drive circuit to drive the first signal line.
Driven by signal line drive circuit (eg sampling operation)
The above-mentioned object is achieved by having control means for further driving (for example, sampling operation) the signal line.

Further, preferably, in the control means in the display device of the present invention, the first signal line drive circuit and the second signal line drive circuit use the same signal line at different times (or different signal lines at the same time). To drive the first signal line drive circuit and the second signal line drive circuit, the drive start signal that shifts the drive start of the first signal line drive circuit and the second signal line drive circuit in time is output, and the first signal line drive circuit and the second signal line drive circuit output 1 All the signal lines to be driven are driven within the horizontal scanning period.

Further, preferably, at least one of the first signal line drive circuit and the second signal line drive circuit in the display device of the present invention, and at least one of the first signal line drive circuit and the second signal line drive circuit. Is provided with storage means for temporarily storing video data for all signal lines to be driven within one horizontal scanning period, and the control means is such that the first signal line drive circuit and the second signal line drive circuit have the same signal. A transfer signal for outputting the video data stored in the storage means to all the signal lines is output so that the lines are driven at different times (or different signal lines are driven at the same time).

Further preferably, in the control means in the display device of the present invention, at least the first signal line drive circuit among the first signal line drive circuit and the second signal line drive circuit has all the signal lines within one horizontal scanning period. (For example, sampling operation).

Further, preferably, the second signal line drive circuit in the display device of the present invention is connected to a part of the signal line group of all the signal lines.

Further preferably, the frequency of the driving clock signal to the second signal line driving circuit in the display device of the present invention is the driving clock signal to the first signal line driving circuit connected to all the signal lines. It is set lower than the frequency of.

Further, preferably, the first signal line driving circuit and the second signal line driving circuit in the display device of the present invention are respectively one end side and the other end side of the plurality of signal lines arranged in a row, The display units are arranged on opposite sides of the display unit.

Further, preferably, the first signal line drive circuit and the second signal line drive circuit in the display device of the present invention are respectively one end side or the other end side of the plurality of signal lines arranged in a row. And is disposed on one side of both opposing sides of the display unit for displaying a screen.

Further, preferably, in the display device of the present invention, at least one of the signal line driving circuit and the scanning line driving circuit is formed on the same substrate as the substrate on which the display section for screen display is formed. Has been done.

With the above configuration, the operation will be described below.

The first signal line drive circuit for the main video screen and the second signal line drive circuit for the sub video screen share the same signal line, and the first signal line drive circuit is controlled to connect the signal lines. In addition to driving, the second signal line driving circuit is controlled to further drive the signal line driven by the first signal line driving circuit, so that the main image screen by the first signal line driving circuit is changed by the second signal line driving circuit. Since it is overwritten on the sub-picture screen, superimposing and picture-in-picture can be performed easily. In this case, the first signal line drive circuit and the second signal line drive circuit are not divided by themselves, and no stripe is generated at the division boundary position. Therefore, the degree of freedom in selecting a display area when performing superimpose or picture-in-picture is increased, and in this case as well, deterioration of display characteristics due to stripes at the division boundary position on the display screen does not occur at all.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments 1 to 3 of the present invention in which the display device of the present invention is applied to, for example, a liquid crystal display device will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a block diagram showing a main configuration of a liquid crystal display device according to Embodiment 1 of the present invention.

In FIG. 1, the liquid crystal display device 1 includes a display section 2 for displaying a screen, a scanning line driving circuit GD (hereinafter referred to as a gate driver GD) for sequentially driving the scanning line group GL,
It has a signal line drive circuit SD for sequentially driving the signal line group SL, and a control unit 3 (control means) for driving and controlling the gate driver GD and the signal line drive circuit SD.

The display unit 2 has a pixel PI in a portion surrounded by two adjacent signal lines SL and two adjacent scanning lines GL.
X are arranged, and a large number of pixels PIX are arranged in a matrix in the vertical and horizontal directions. The pixel PIX is composed of a liquid crystal display cell. In the display unit 2, the data video signal supplied to the signal line SL is supplied to each pixel PIX by the scan signal sequentially supplied to the scan line GL to be displayed on the screen.

The gate driver GD is connected to each one end of the scanning line group GL arranged in a large number in the display section 2, and sequentially supplies a scanning signal to each scanning line of the scanning line group GL. The scanning line selection clock signal GCK for driving the drive circuit and the scanning line selection start signal GSP are input to the gate driver GD.

The signal line drive circuit SD has a multi-driver configuration in which a plurality of drive circuits capable of independently displaying an image are provided, and here, for example, the first signal line drive circuit on the upper side of the display unit 2 ( Hereinafter referred to as source driver SD1)
And a second signal line drive circuit (hereinafter referred to as source driver SD2) on the lower side of the display unit 2.

The source driver SD1 is a signal line driving circuit for the main video screen, and has a large number of signal lines SL1 to SLn (1 <n≤N; n and N are positive integers of 2 or more) arranged in the display section 2. ), The main video signal Video1 is sequentially sampled and sequentially supplied to the signal lines SL1 to SLn. The source driver SD1 includes a video signal sampling clock signal SCK for operating the drive circuit.
1, the video signal sampling start signal SSP1, and the main video signal Video1 to be sampled are input.

The source driver SD2 is a signal line drive circuit for a sub-picture screen such as superimpose or picture-in-picture, and has signal lines SL1 to SLn (1 <n.
≦ N; n and N are positive integers of 2 or more) and are connected to the other end of the video signal Video2 for superimpose or picture-in-picture and sequentially supplied to the signal lines SL1 to SLn. is there. The source driver SD2 includes a video signal sampling clock signal SCK2 for driving a drive circuit, a video signal sampling start signal SSP2, a write enable signal SWE for writing video data to a signal line, and a superimpose or picture to be sampled. In-picture video signal Vi
deo2 has been input. The source drivers SD1 and SD2 share the same signal lines SL1 to SLn.

The control section 3 delays the video signal sampling start signal SSP2 output to the source driver SD2 with respect to the video signal sampling start signal SSP1 output to the source driver SD1, and outputs the video signal sampling start signal SSP2 to the source drivers SD1 and SD2. In contrast, the same signal lines SL1 to SLn are sequentially driven within one horizontal scanning period. That is, the control unit 3 further samples (selects) the same signal line sampled (selected by the source driver SD1) by the source driver SD2. 2) Sampling (selection operation).

Here, a driving method of the image display device 1 that executes the superimpose and picture-in-picture functions will be described with reference to FIG.

With the above structure, first, the frequency αMH is set as the main video signal Video1 shown in FIG. 2A and the video signal sampling clock signal SCK1 shown in FIG. 2B.
z clock signal and the main video signal Video as the video signal sampling start signal SSP1 shown in FIG.
The pulse signal indicating the head position of the effective display area in one horizontal scanning period 1 is supplied to the source driver SD1.

Similarly, the video signal Vi for superimpose or picture-in-picture shown in FIG.
deo2, a clock signal having a frequency of α'MHz as the video signal sampling clock signal SCK2 shown in FIG. 2E, and a superimpose or picture-in-picture image as the video signal sampling start signal SSP2 shown in FIG. 2F. A pulse signal indicating the start position of the effective display area in one horizontal scanning period of the signal Video2;
The write enable signal SWE to the signal line of the video data shown in FIG. 2G is supplied to the source driver SD2.

At this time, the scanning line selection clock signal GCK
Is supplied to the gate driver GD as a clock signal having a frequency of β KHz and a pulse signal indicating the start position of the effective display area in one vertical scanning period of the main video signal Video1 as the scanning line selection start signal GSP.

However, each signal supplied to the source drivers SD1 and SD2 and the gate driver GD must satisfy the following three conditions (1) to (3).

(1) The video signal sampling clock signal SCK2 is the video signal sampling clock signal SCK.
Although the frequency and the phase may be different from those of 1, all signal lines SL1 to SL are surely included in one horizontal scanning period.
It is necessary to set the frequency so that the sampling of the video data for n is completed. It is desirable that the video signal sampling clock signals SCK1 and SCK2 have the same frequency.

(2) The signal line SLx (1≤x≤N; x and N are positive integers) by which the source driver SD1 performs sampling, and the signal line SLx '(1≤x'≤ by which the source driver SD2 performs sampling). N; x'is a positive integer), the sampling timing is controlled so that x = x 'does not hold at the same time. That is, both source drivers SD
It is necessary to control so that 1 and SD2 do not sample the video signal on the same signal line at the same time.

For example, as shown in FIG. 2, when the video signal sampling clock signals SCK1 and SCK2 have the same frequency and the same phase, after the source driver SD1 samples one or more signal lines (after a predetermined delay period elapses). ), So that the source driver SD2 starts sampling, the video signal sampling start signal SSP2 is supplied with a delay for a predetermined period from the output time point of the video signal sampling start signal SSP1. That is, the control unit 3 controls the output of the video signal sampling start signals SSP1 and SSP2 by making them differ by one cycle or more of the video signal sampling clock signals SCK1 and SCK2. by this,
It is possible to overwrite the main video data with video data for superimpose or picture-in-picture.

(3) The start data of the effective display area of the video signal Video2 for superimpose or picture-in-picture is one or more source drivers SD1 as compared with the start data of the effective display area of the main video signal Video1. The signal is output after a delay of the sampling period.

The first embodiment is based on the above three conditions (1)-
Assuming that (3) is satisfied, the description of the driving method of the liquid crystal display device 1 that executes the superimpose and the picture-in-picture operations will be continued.

The source driver SD1 receives the video signal sampling start signal SSP1 supplied from the controller 3 and starts sampling of the main video signal Video1 in synchronization with the video signal sampling clock signal SCK1. Main video data V obtained by sampling
DAT1 to VDATn (1 <n ≦ N; n and N are positive integers) respectively pass through the respective signal lines SL1 to SLn and are sequentially selected (so-called line sequential scanning) by the gate driver GD. It is sequentially written in each pixel PIX connected to GLm. That is, the main video data VD
AT1 is supplied to the signal line SL1, and the main video data VDA
T2 is supplied to the next signal line SL2, ... The main video data VDATn is sequentially supplied to the signal line SLn.

At this time, like the source driver SD1, the source driver SD2 receives the video signal sampling start signal SSP2 supplied from the control unit 3 and synchronizes with the video signal sampling clock signal SCK2 to superimpose or Sampling of the video signal Video2 for picture-in-picture and the write enable signal SWE to the video data signal line is started.

Write enable data SWE1 'to signal lines for each video data obtained by sampling
Video data VDAT1 'to VDAT for superimpose and picture-in-picture obtained by sampling, which is determined to be "write permitted" based on n'
n ′ (1 <n ′ ≦ N; n ′, N is a positive integer) is connected to one scanning line GLm sequentially selected (sequential scanning) by the gate driver GD through each signal line SL1 to SLn. It is sequentially written in each pixel PIX that is present. If the data write is enabled when the write enable signal SWE is “L” (low level), in FIG.
The video data VDAT3 'and VDAT4' are not written in the pixel PIX. The other video data VDAT1 'is supplied to the signal line SL1, the main video data VDAT2' is supplied to the next signal line SL2, ... Main video data VDAT.
n ′ is sequentially supplied to the signal line SLn and data is written in each pixel PIX.

That is, the main video data sampled first by the source driver SD1 is overwritten by the sub video data (superimpose or picture-in-picture video data) sampled by the source driver SD2.

As described above, according to the first embodiment, the source driver SD1 for the main video screen and the source driver SD for the superimpose or picture-in-picture are used.
2 share the same signal lines SL1 to SLn, and the control unit 3 causes the signal line SLx (1 ≦ x ≦ N), which the source driver SD1 has finished driving, to be further transferred to the source driver SD2. The video signal sampling start signals SSP1 and SSP2 are shifted in time so as to be output to the source drivers SD1 and SD2 so that the main video screen by the source driver SD1 is used for superimposing or picture in picture by the source driver SD2. It can be easily overwritten on the screen.

By doing so, it becomes possible to easily execute the superimpose or picture-in-picture function at any position on the display screen of the display unit 2. At this time, the source driver S
Since there is no division of D1 and SD2 itself, no stripe is generated at the division boundary position. In this way, it is possible to increase the degree of freedom in selecting the display area when performing superimpose or picture-in-picture, and in this case, the display characteristics do not deteriorate due to stripes at the dividing boundary positions on the display screen.

When the video signal Video2 for superimpose or picture-in-picture is an analog signal and the sampled video data is lower or higher than a certain voltage value, the video data is written to the signal line. When a circuit for preventing the inclusion is included in the source driver SD2, or when the video signal Video2 for superimpose or picture-in-picture is a digital signal and the video data at the time of sampling has a certain digital value, In any case where the source driver SD2 includes a circuit for preventing the video data from being written to the signal line, the write enable signal SWE for writing the video data to the signal line can be omitted. In the first embodiment, the write enable signal SW
The write control function is realized by using E.

Further, in the first embodiment, as in the driving method shown in FIG.
Although the sampling timings of 1 and SD2 are slightly shifted (the sampling timing has a delay time), both source drivers SD are simultaneously sampled so that all the signal lines SL1 to SLn are sampled within one horizontal period.
1, SD2 is operating. Not limited to this, as long as the above conditions (1) to (3) are satisfied, after the sampling operation of the source driver SD1 is completed, the source driver SD
It is also possible to configure such that only one of the source drivers performs the sampling operation within one horizontal period so that the sampling operation 2 is started.

Further, in the first embodiment, both source drivers SD1 and SD2 are respectively arranged on the upper and lower opposite sides of the display section 2 and connected to the respective signal lines.
Both source drivers SD1 and SD2 may be disposed on either one of the upper and lower opposite sides of the display unit 2 so as to be connected to the respective signal lines (all signal lines SL1 to SLn). .

Further, although not particularly described in the first embodiment, the source drivers SD1 and SD2 and the gate driver GD are monolithically formed on the same substrate on which the display unit 2 is formed. Alternatively, they may be connected using a connecting means such as a flexible substrate. (Second Embodiment) In the second embodiment, a video signal Video
Sampling of 1 and 2 is started simultaneously, and the main video signal V
Each time-sampling potential of video1 and video signal V for superimpose or picture-in-picture
The time-series sampling potentials of video2 are temporarily stored in the respective memories, and the source drivers SD11, 1
2 is a case where the above sampling potentials are supplied to the signal lines SL1 to SLn from 2 at different timings.

FIG. 3 is a block diagram showing a main configuration of a liquid crystal display device according to the second embodiment of the present invention.

In FIG. 3, the liquid crystal display device 11 includes a display section 12 for displaying a screen and a scanning line driving circuit GD (hereinafter referred to as a gate driver GD) for sequentially driving the scanning line group GL.
And a signal line drive circuit SD ′ for driving the signal line group SL,
The controller 13 controls the gate driver GD and the signal line drive circuit SD ′.

The display section 12 has two adjacent signal lines SL.
The pixel PI in the portion surrounded by the two scanning lines GL adjacent to
X are arranged, and a large number of pixels PIX are arranged in a matrix in the vertical and horizontal directions. The pixel PIX is composed of a liquid crystal display cell. In the display unit 12, the data video signal supplied to the signal line SL is supplied to the pixel PIX and the image is displayed for each scanning signal supplied to the scanning line GL.

The gate driver GD is connected to one end of each of the scanning line groups GL arranged in a large number on the display section 12, and sequentially supplies a scanning signal to each scanning line of the scanning line group GL. The scanning line selection clock signal GCK for driving the drive circuit and the scanning line selection start signal GSP are input to the gate driver GD.

The signal line drive circuit SD 'has a multi-driver structure in which a plurality of drive circuits capable of independently displaying an image are provided and has a multi-driver configuration. Source driver SD11)
And a second signal line drive circuit (hereinafter referred to as source driver SD12) below the display unit 2.

The source driver SD11 is connected to one end of a plurality of signal lines SL1 to SLn (1 <n ≦ N) arranged in the display section 12, and sequentially samples the main video signal Video1 to sequentially output the signal lines SL1 to SL1. It is sequentially supplied to SLn. The source driver SD11 includes a video signal sampling clock signal SCK for driving the drive circuit.
1, a video signal sampling start signal SSP1, a main video signal Video1 to be sampled, and a data transfer signal TRF1 to be described later are input.

The source driver SD11 supplies the main video signal V
For video 1, for each signal line, L latch memories (not shown) as temporary storage means for all pixels PIX connected to one scanning line (the number of signal lines per line n) are connected. Minute (1 ≤ L; L for each signal line)
The latch memory of the source driver SD11 uses all the signal lines SL1 to SLn in response to the data transfer signal TRF1.
Output controlled.

The source driver SD12 is connected to the signal line SL1.
To SLn (1 <n ≦ N), the signal lines SL1 to SLn are sequentially sampled to sequentially sample video signals Video2 for superimpose and picture-in-picture.
It is sequentially supplied to SLn. The source driver SD12 includes a video signal sampling clock signal SCK2 for driving a drive circuit, a video signal sampling start signal SSP2, a write enable signal SWE for writing video data to a signal line, and a superimpose or picture to be sampled. Video signal Video for in-picture
o2 and a data transfer signal TRF2 described later are input.

The source driver SD12 is a video signal Vid for superimpose and picture-in-picture.
As a write enable signal SWE for writing the eo2 and video data to the signal line, a latch memory for all pixel PIX (the number of signal lines per line n) connected to one scanning line for each signal line ( L (1 ≦ L; L for each signal line) built in (not shown), and the latch memory of the source driver SD12 is output controlled to all the signal lines SL1 to SLn by the data transfer signal TRF2.

The control unit 13 uses the source drivers SD11, S
D12 includes video signal sampling start signals SSP1 and SSP2.
At the same time, and then the data transfer signal T
RF1 and RF2 are output differently for a predetermined time (not simultaneously output). Using these data transfer signals TRF1 and TRF2, the control unit 13 sends the main video signal Vid from the source driver SD11 to the signal lines SL1 to SLn.
After the time series sampling potentials of eo1 are simultaneously supplied, the signal lines SL1 to SL from the source driver SD12 are supplied.
Control is performed so that the time-series sampling potentials of the superimpose or picture-in-picture video signal Video2 are simultaneously supplied to n.

Here, a driving method of the image display device 11 that executes the superimpose and picture-in-picture functions will be described with reference to FIG.

With the above configuration, first, the frequency αMH is set as the main video signal Video1 shown in FIG. 4A and the video signal sampling clock signal SCK1 shown in FIG. 4B.
z clock signal and the main video signal Video1 as the video signal sampling start signal SSP1 shown in FIG.
Pulse signal indicating the head position of the effective display area in one horizontal scanning period and the data transfer signal (timing shown in FIG. 4D for outputting the video data stored in the latch memory in the source driver SD11 to the signal line. Pulse signal) TRF1 is supplied to the source driver SD11.

Similarly, the video signal Vi for superimpose or picture-in-picture shown in FIG.
deo2, a clock signal having a frequency α'MHz as the video signal sampling clock signal SCK2 shown in FIG. 4F, and a superimpose or picture-in-picture video signal as the video signal sampling start signal SSP2 shown in FIG. 4G. A pulse signal indicating the start position of the effective display area in one horizontal scanning period of Video2, a write enable signal SWE to the signal line of the video data shown in FIG. 4 (h), and a latch signal in the source driver SD12 are stored. The data transfer signal (timing pulse signal) TRF2 shown in FIG. 4 (i) for outputting the video data stored in the signal line is supplied to the source driver SD12.

At this time, the scanning line selection clock signal GCK
Is supplied to the gate driver GD as a clock signal having a frequency of β KHz and a pulse signal indicating the start position of the effective display area in one vertical scanning period of the main video signal Video1 as the scanning line selection start signal GSP.

However, the source drivers SD11 and SD1
2 and each signal supplied to the gate driver GD must satisfy the following two conditions (1) and (2).

(1) The video signal sampling clock signal SCK2 is the video signal sampling clock signal SCK.
Although the frequency and the phase may be different from those of 1, all signal lines SL1 to SLn must be included in one horizontal scanning period.
The frequency is set so that the sampling operation of the video data is completed. Video signal Sampling clock signal S
It is desirable that CK1 and SCK2 have the same frequency.

(2) A data transfer signal (timing pulse signal) TRF1 for outputting the video data stored in the latch memory in the source driver SD11 to the signal line and stored in the latch memory in the source driver SD12. Data transfer signal (timing pulse signal) for outputting existing video data to the signal line
The output timing is set so that TRF2 and TRF2 are not simultaneously selected.

The second embodiment is based on the above two conditions (1),
Assuming that the condition (2) is satisfied, the description of the driving method of the image display device 11 that executes the superimpose or the picture-in-picture operation will be continued.

In the source driver SD11, the control unit 13
Video signal sampling start signal SSP1 supplied from
In response to the video signal sampling clock signal SCK1
Starts sampling of the main video signal Video1, and the main video data VD obtained by sampling
AT1 to VDATn (1 <n ≦ N) are stored in the latch memory.

On the other hand, the source driver SD12, like the source driver SD11, receives the video signal sampling start signal SSP2 supplied from the control unit 13 and uses the video signal sampling clock signal SCK2 for superimposing or picture-in-picture. Of the video signal Video2 and the video data write enable signal SWE to the signal line are started, and the video data VDAT1 'to VDAT for superimpose and picture-in-picture obtained by this sampling are started.
DATn ′ (1 <n ′ ≦ N), write enable data SWE1 ′ to n ′ (1 <n ′) for each video data to the signal line.
≦ N) is stored in the latch memory.

After the video data has been stored in the latch memory, the data transfer signal (timing pulse signal) TRF1 for outputting the video data stored in the latch memory in the source driver SD11 to the signal line is sent from the control unit 13 by the source. The main video data VDAT1 to VDATn (1 <n ≦ N) supplied to the driver SD11 are simultaneously transmitted through the signal lines SL1 to SLn and the gate driver GD.
Data is written in each pixel PIX connected to one scanning line GLm selected (so-called line-sequential scanning) by. That is, the main video data VDAT1 is supplied to the signal line SL1, and the main video data VDAT2 is supplied to the next signal line SL2.
The main video data VDATn is supplied to the signal line S.
It is supplied to Ln and data is written in each pixel PIX.

Main video data VDAT1 to VDATn (1
After the writing of <n ≦ N) to each pixel PIX is completed, the data transfer signal (timing pulse signal) TRF2 for outputting the video data stored in the latch memory in the source driver SD12 to the signal line is sourced from the control unit 13. Superimpose or picture-in obtained by sampling determined to be “write-enabled” based on write-enable data SWE1′-n ′ to the signal line of each video data supplied to the driver SD12 and obtained by sampling Video data for picture VDAT
1 ′ to VDATn ′ (1 <n ′ ≦ N) are simultaneously selected through the signal lines SL1 to SLn and selected by the gate driver GD (so-called line-sequential scanning).
The data is written in each pixel PIX connected to. If the data write is possible when the write enable data SWE is'L '(low level), FIG.
In (h), the video data VDAT2 'is not written. The other video data VDAT1 'is supplied to the signal line SL1, and the main video data VDATn' is supplied to the signal line SLn.
Is being supplied to.

That is, the video data previously sampled by the source driver SD11 is converted to the source driver SD12.
Will be overwritten with video data sampled later.

As described above, according to the second embodiment, the source driver SD11 for the main video screen and the source driver S for the superimpose or picture-in-picture are used.
D12 shares the same signal lines SL1 to SLn,
Further, the control unit 13 causes the data transfer signal (timing pulse signal) TRF so that the source driver SD2 drives the signal line groups SL1 to SLn, which the source driver SD11 has driven all at once, all at once.
Source drivers SD11 and S are shifted in time from 1 and 2.
Source driver S to output to D12 separately
The main video screen by D11 can be easily overwritten by the superimpose or picture-in-picture screen by the source driver SD12.

By doing so, superimposing or picture-in-picture can be easily displayed at any position on the display screen of the display unit 12, and the source drivers SD11 and SD12 themselves ( Since there is no division of the signal line drive circuit), stripes do not occur at the division boundary positions on the display screen, and an image display device with good display characteristics can be obtained. In this way, it is possible to increase the degree of freedom in selecting the display area when performing superimpose or picture-in-picture, and even in this case, there is no deterioration in display characteristics due to stripes at the division boundary positions on the display screen. It won't happen.

When the video signal Video2 for superimpose or picture-in-picture is an analog signal and the sampled video data is lower or higher than a certain voltage value, the video data is written to the signal line. The circuit that acts so as not to include the source driver SD
If it is included in 12, video signal Video for superimpose or picture-in-picture
2 is a digital signal, and when the sampled video data has a certain digital value, a circuit that acts so as not to write the video data in the signal line is the source driver SD12.
In either case, the write enable signal SWE for writing the video data to the signal line can be omitted. In the second embodiment, the write control signal is realized by using the write enable signal SWE.

Further, the source drivers SD11 and SD12
When the control circuit (control means) that writes the latched video data to the signal line all at once when the latching process of the video signal data is finished is included in each, the video stored in the latch memory The timing pulse signals TRF1 and TRF2 for outputting data to the signal lines can be omitted. In that case, the circuit configuration must be such that the source drivers SD11 and SD12 do not write to the signal lines at the same time.

In the driving method shown in FIG. 4, both source drivers SD11 and SD1 are simultaneously operated within one horizontal period.
2 is operating, but as long as the above conditions (1) and (2) are satisfied, one of the two operations is performed within one horizontal period so that the operation of the source driver SD12 starts after the sampling operation of the source driver SD11 is completed. Alternatively, only one signal line drive circuit may be operating.

When the number L of the latch memories is 2 or more, one latch memory is a data latch of the video signal, and the other latch memory is a data output to the signal line. It is possible to do both contents at the same time within the horizontal period.

Further, the source drivers SD11 and SD12
Both do not have to have the circuit configuration of the second embodiment, and only one of them may have the circuit configuration of the first embodiment. At that time, the source driver SD1
The source drivers SD11 and SD12 prevent the SD1 and SD12 from simultaneously writing video data on the same signal line.
Each input signal to (especially data transfer signal TRF
You must pay attention to the timing of 1) and 2).

For example, when the source driver SD 'is composed of the source drivers SD1 and SD12, the source driver SD1 of the first embodiment sends video data to all the signal lines SL1 to SLn within one horizontal scanning period. In the horizontal blanking period after sampling (driving), the source driver SD12 receives the data transfer signal TRF2 from the control unit 13 and outputs all the video data in the latch memory to all the signal lines SL1 to SLn all at once. It can also be configured to.

Further, the source drivers SD11 and SD12
Is connected to both opposite sides of the display unit 12,
Both source drivers SD11, S on one side on either side
D12 may be connected.

Further, the source drivers SD11 and SD12
The gate driver GD may be monolithically formed on the same substrate as the substrate on which the display unit 12 is formed, or may be connected using a connecting means such as a flexible substrate. (Third Embodiment) In the third embodiment, the superimpose or the picture-in-picture is always performed at a fixed position such as when the battery level symbol of a mobile phone is displayed at a predetermined position on the display screen. is there. In this case, it is not necessary for the signal line drive circuit SD22 shown in FIG. 5 to be connected to all the signal lines, and it is better in terms of circuit scale and power consumption to drive only the necessary signal lines corresponding to the display position. Is effective for. Hereinafter, Embodiment 3 of the present invention will be described in detail with reference to FIGS. 5 and 6.

FIG. 5 is a block diagram showing a main configuration of a liquid crystal display device according to the third embodiment of the present invention.

In FIG. 5, the liquid crystal display device 21 includes a display section 22 for displaying a screen and a scanning line driving circuit GD (hereinafter referred to as a gate driver GD) for sequentially driving the scanning line group GL.
And a signal line drive circuit SD ″ for sequentially driving the signal line group SL
And a control unit 23 (control means) for driving and controlling the gate driver GD and the signal line drive circuit SD ″.

The display section 22 includes two adjacent signal lines SL.
The pixel PI in the portion surrounded by the two scanning lines GL adjacent to
X are arranged, and a large number of pixels PIX are arranged in a matrix in the vertical and horizontal directions. The pixel PIX is composed of a liquid crystal display cell. The display unit 22 displays an image by supplying the data video signal supplied to the signal line SL to each pixel PIX for each scanning signal supplied to the scanning line GL.

The gate driver GD is connected to one end of each of the scanning line groups GL arranged in a large number in the display section 22, and sequentially supplies a scanning signal to each scanning line of the scanning line group GL. The scanning line selection clock signal GCK for driving the drive circuit and the scanning line selection start signal GSP are input to the gate driver GD.

The signal line drive circuit SD ″ has a multi-driver configuration in which a plurality of drive circuits capable of independently displaying an image are provided. For example, the first signal line drive circuit on the upper side of the display unit 22 (hereinafter Source driver SD1)
Two second signal line drive circuits (hereinafter referred to as source driver SD22) below the display unit 2 are arranged.

The source driver SD1 is connected to one end of a plurality of signal lines SL1 to SLn (1 <n ≦ N) provided in the display section 22, and sequentially samples the main video signal Video1 to sequentially connect the signal lines SL1 to SL1. It is sequentially supplied to SLn. The source driver SD1 includes a video signal sampling clock signal SCK1 for driving the drive circuit.
The video signal sampling start signal SSP1 and the sampled main video signal Video1 are input.

The source driver SD22 is connected to the signal line SL1.
To SLn (1 <n ≦ N), which are part of the signal lines SLp to S
It is connected to the other end of Lq (1 ≦ p <q, 1 <q ≦ N) and sequentially samples the video signal Video2 for superimpose or picture-in-picture and sequentially supplies it to the signal lines SLp to SLq. Is. The source driver SD22 includes a video signal sampling clock signal SCK2 for driving the drive circuit, a video signal sampling start signal SSP2, a write enable signal SWE for writing the video data to the signal line, and a superimpose or picture-in signal to be sampled. Video signal V for picture
video2 is input. In this case, the display positions of superimpose and picture-in-picture correspond to the positions of the signal lines SLp to SLq.

The control section 23 supplies the source driver SD to the signal line SLx to which the time-series sampling potentials of the main video signal Video1 are supplied from the source driver SD1.
Video signal sampling is performed by different signals for a predetermined time so as to supply time-series sampling potentials of the superimpose or picture-in-picture video signal Video2 from 12, ie, driving the same signal line at different times (sampling operation). The start signals SSP1 and SSP2 are output.

Here, a driving method of the image display device 21 that executes the superimpose and picture-in-picture functions will be described with reference to FIG.

With the above structure, first, the frequency αMH is set as the main video signal Video1 shown in FIG. 6A and the video signal sampling clock signal SCK1 shown in FIG. 6B.
z clock signal and the main video signal Video1 as the video signal sampling start signal SSP1 shown in FIG.
And a pulse signal indicating the head position of the effective display area in one horizontal scanning period are supplied to the source driver SD1.

Similarly, the video signal Vi for superimpose or picture-in-picture shown in FIG.
deo2, a clock signal of frequency α'MHz as the video signal sampling clock signal SCK2 shown in FIG. 6 (e), and a video for superimpose or picture-in-picture as the video signal sampling start signal SSP2 shown in FIG. 6 (f). A pulse signal indicating the start position of the effective display area in one horizontal scanning period of the signal Video2;
The video data write enable signal SWE shown in FIG. 6G is supplied to the source driver SD22.

At this time, in the scanning line driving circuit GD, the head of the effective display area in one vertical scanning period of the clock signal of the frequency βKHz as the scanning line selection clock signal GCK and the main video signal Video1 as the scanning line selection start signal GSP. A pulse signal indicating the position is supplied.

However, the source drivers SD1 and SD22
And each signal supplied to the gate driver GD must satisfy the following three conditions (1) to (3).

(1) The video signal sampling clock signal SCK2 is the video signal sampling clock signal SCK.
Although the frequency and the phase may be different from those of 1, the frequency must be such that the sampling operation of the video data is completed for all the signal lines SLp to SLq to be driven within one horizontal scanning period. To do. Signal line drive circuit SD2
2 has a smaller number of samplings than the signal line drive circuit SD1 (the number of all signal lines SLp to SLq to be driven is smaller than the number of all signal lines SL1 to SLn), so SC
K1 frequency α (MHz)> SCK2 frequency α '(M
Hz) is desirable in terms of power consumption.

(2) The signal line SLx (1.ltoreq.x.ltoreq.N) in which the source driver SD1 performs sampling and the signal line SLx '(p.ltoreq.p in which the source driver SD22 performs sampling).
x ′ ≦ q), so that x = x ′ does not hold at the same time. That is, both source drivers SD1 and SD22 are prevented from simultaneously sampling on the same signal line. For example, as shown in FIG. 5, the source driver SD1
However, as compared with the sampling operation for the signal line (for example, the signal line SLp) by the source driver SD22, sampling is performed for at least one signal line (for example, the signal line SLp + 1) first. After that, the source driver SD2
The video signal sampling start signal SSP2 may be supplied to the source driver SD22 so that the signal No. 2 starts the sampling operation on the signal line (for example, the signal line SLp + 1).

(3) The head of the effective display area of the video signal Video2 for superimpose or picture-in-picture is sampled first by the source driver SD1 on one or more signal lines as compared with that of the main video signal Video1. It's delayed by the period of time.

In the third embodiment, the above three conditions (1) to
Assuming that (3) is satisfied, the description of the driving method of the image display device 21 that executes the superimpose and the picture-in-picture operations will be continued.

The source driver SD1 receives the video signal sampling start signal SSP1 supplied from the control section 23, starts sampling of the main video signal Video1 by the video signal sampling clock signal SCK1, and obtains the main video obtained by the sampling. Data VDA
T1 to VDATn (1 <n ≦ N) are signal lines SL1 to S
Through Ln, data is sequentially written in each pixel PIX connected to one scanning line GLm selected (line-sequential scanning) by the scanning line driving circuit GD. That is, the main video data VD
AT1 is supplied to the signal line SL1, and the main video data VDA
T2 is supplied to the next signal line SL2, ... The main video data VDATn is sequentially supplied to the signal line SLn and data is written.

In the same manner as the source driver SD1, the source driver SD22 receives the video signal sampling start signal SSP2 supplied from the control unit 23, and in response to the video signal sampling clock signal SCK2, the video for superimposing or picture-in-picture. Signal Vi
The sampling operation of deo2 and the write enable signal SWE to the video data signal line is started.

Write enable data SWEp 'to the signal line of each video data obtained by this sampling
Video data VDATp 'to VDA for superimpose and picture-in-picture obtained by sampling, which are determined to be "write-enabled" based on ~ q'
Tq ′ (1 ≦ p ′ <q ′, 1 <q ′ ≦ N) is connected to one scanning line GLm selected (line-sequential scanning) by the scanning line driving circuit GD through each signal line SLp to SLq. Are sequentially written in each pixel PIX. If data writing is enabled when the write enable signal SWE is'L '(low level), the video data VDATp + 1' is not written in FIG. 6 (g). The other video data VDATp ′ is supplied to the signal line SLp, and the main video data VDATq ′ is sequentially supplied to the signal line SLq and written therein.

That is, the video data sampled first by the source driver SD1 is overwritten by the video data sampled later by the source driver SD22.

As described above, according to the third embodiment, the source driver SD1 for the main video screen and the source driver SD for the superimpose or picture-in-picture are used.
22 share the same signal lines SLp to SLq, and the control unit 23 causes the source driver SD22 to further move the signal line SLx (1 ≦ x ≦ N) that the source driver SD1 has finished driving first. So that the video signal sampling start signals SSP1 and SSP2 are temporally shifted and output to the source drivers SD1 and SD22, the main video screen by the source driver SD1 is changed to the source driver SD2.
It can be easily overwritten by the superimpose by 2 and the picture for picture screen.

By doing so, superimposing or picture-in-picture can be easily displayed at any position on the display screen of the display unit 12, and the source drivers SD1 and SD22 themselves ( Since there is no division of the signal line drive circuit), stripes are not generated at the division boundary positions on the display screen, and the liquid crystal display device 21 having good display characteristics can be obtained. As described above, even if the degree of freedom in selecting the display area when performing the superimpose or the picture-in-picture is increased, the display characteristics are not deteriorated due to the stripes at the division boundary positions. Furthermore, the frequency of the driving clock signal to the source driver SD22 can be set lower than the frequency of the driving clock signal to the source driver SD1 connected to all the signal lines, so that superimposing or picture-in-picture can be performed. Do not generate extra power when doing.

When the video signal Video2 for superimpose or picture-in-picture is an analog signal and the sampled video data is lower or higher than a certain voltage value, the video data is written to the signal line. The circuit to prevent the signal line drive circuit SD22
, The video signal Video2 for superimpose and picture-in-picture is a digital signal, and the sampled video data is
When there is a circuit for preventing the video data from being written in the signal line at a certain digital value in the signal line drive circuit SD22, a write enable signal for writing the video data in the signal line is provided. SWE can be omitted. In the third embodiment, the write enable signal SW
The write control function is realized by using E.

In the driving method shown in FIG. 6, both source drivers SD1 and SD22 are operating simultaneously within one horizontal period. However, as long as the above conditions (1) to (3) are satisfied, the source driver SD1 After the sampling operation is completed, the operation of the source driver SD22 is started,
Only one of the source drivers may be operating within one horizontal period.

Further, in the third embodiment, the above first embodiment is adopted.
The same drive is performed, but the source driver SD1,
The SD 22 does not have to have the circuit configuration of the third embodiment, and either one may have the circuit configuration of the second embodiment. At that time, the source drivers SD1, S
Care must be taken in the timing of each input signal so that D22 does not write to the same signal line at the same time.

Further, the source driver SD1 and the source driver SD22 are connected to both sides of the display unit 22 which face each other in the vertical direction, but both source drivers SD1 and SD22 are connected to one side of either side. It may be arranged.

Further, the source driver SD1, the source driver SD22, and the gate driver GD may be monolithically formed on the same substrate on which the display section 22 is formed, and a connecting means such as a flexible substrate is used. May be connected.

[0116]

As described above, according to the present invention, the first signal line drive circuit for the main video screen and the second signal line drive circuit for the sub video screen share the same signal line, and After the first signal line drive circuit drives the signal line, the first signal line drive circuit controls so that the second signal line drive circuit further drives the first signal line drive circuit.
The main video screen by the signal line drive circuit can be easily overwritten by the sub video screen by the second signal line drive circuit, and superimposing or picture-in-picture can be easily performed. In this case, the first signal line drive circuit and the second signal line drive circuit are not divided by themselves, and no stripe is generated at the division boundary position on the display screen. Therefore,
Even if the degree of freedom in selecting the display area at the time of performing superimpose or picture-in-picture is increased, the display characteristics due to the stripes at the division boundary position are not deteriorated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main configuration of a liquid crystal display device according to a first embodiment of the present invention.

2A to 2G are timing charts of respective signals in the liquid crystal display device of FIG.

FIG. 3 is a block diagram showing a main configuration of a liquid crystal display device according to a second embodiment of the present invention.

4 (a) to (i) are timing charts of respective signals in the liquid crystal display device of FIG.

FIG. 5 is a block diagram showing a main configuration of a liquid crystal display device according to a third embodiment of the present invention.

6A to 6G are timing charts of respective signals in the liquid crystal display device of FIG.

FIG. 7 is a block diagram showing a main configuration of a conventional liquid crystal display device.

8A to 8D are timing charts of respective signals in the liquid crystal display device of FIG. 7.

[Explanation of symbols]

1, 11, 21 Liquid crystal display device 2, 12, 22 Display unit 3, 13, 23 Control unit (control means) SD1, SD2, SD11, SD12, SD22 Source driver (signal line drive circuit) SL1 to SLn, SLp to SLq Signal line GD Gate driver (scanning line drive circuit) GL Scanning line group Video1 Main video signal SCK1, SCK2 Video signal sampling clock signal SSP1, SSP2 Video signal sampling start signal (driving start signal) Video2 Superimpose or picture-in-picture video Signal SWE Write enable signal TRF1, TRF2 Data transfer signal (transfer signal)

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 660 G09G 3/20 660A 680 680G H04N 5/45 H04N 5/45 5/66 102 5/66 102B F-term (reference) 2H093 NA16 NC16 NC32 ND60 5C006 AC21 AF38 AF43 BB11 BC20 BF11 FA04 FA05 FA06 FA07 FA21 5C025 AA28 BA28 CA06 CA09 DA06 5C058 AA07 AA08 BA03 BA21 JJ02 01702 DD1717 DD021717 DD021717 DD01 BB01 DD020517 A01DD02 BB12 BB01 BB01 BB01 CB01

Claims (9)

[Claims] 1. A scanning line drive circuit that sequentially supplies scanning signals to a plurality of scanning lines, and a signal line that supplies a video signal to a plurality of signal lines that intersect the plurality of scanning lines. In a display device having a drive circuit and displaying a screen by outputting a video signal according to the scanning signal output, the signal line drive circuit includes at least a first signal line drive circuit for a main video screen and a sub-video screen. Second signal line drive circuit, the first signal line drive circuit and the second signal line drive circuit share the same signal line, and drive the signal line by controlling the first signal line drive circuit. In addition, the display device having a control means for controlling the second signal line drive circuit to further drive the signal line driven by the first signal line drive circuit. 2. The control means controls the first signal line drive circuit and the second signal line drive circuit so that the first signal line drive circuit and the second signal line drive circuit drive the same signal line at different times. A drive start signal for shifting the drive start of the line drive circuit with respect to time is output, and the first signal line drive circuit and the second signal line drive circuit drive all signal lines to be driven within one horizontal scanning period. 1
Display device described. 3. At least one of the first signal line drive circuit and the second signal line drive circuit, and at least one of the first signal line drive circuit and the second signal line drive circuit within one horizontal scanning period. Storage means for temporarily storing video data for all the signal lines to be driven is provided, and the control means is configured such that the first signal line drive circuit and the second signal line drive circuit cause the same signal line at different times. The display device according to claim 1, wherein a transfer signal for outputting the video data stored in the storage means to all signal lines so as to be driven is output. 4. The control means drives at least a first signal line drive circuit of the first signal line drive circuit and the second signal line drive circuit for all signal lines within one horizontal scanning period. 3. The display device according to item 3. 5. The display device according to claim 1, wherein the second signal line drive circuit is connected to a part of a signal line group of all signal lines. 6. The frequency of the drive clock signal to the second signal line drive circuit is lower than the frequency of the drive clock signal to the first signal line drive circuit connected to all the signal lines. The image display device according to claim 5, which is set. 7. The first signal line drive circuit and the second signal line drive circuit are respectively on one end side and the other end side of a plurality of signal lines arranged in a row, and of a display unit for performing screen display. The display device according to claim 1, wherein the display device is provided on each of opposite sides. 8. The first signal line drive circuit and the second signal line drive circuit are each one of one end side and the other end side of a plurality of signal lines arranged in a row, and screen display is performed. The image display device according to claim 1, wherein the image display device is disposed on one side of both opposing sides of the display unit. 9. The display according to claim 1, wherein at least one of the signal line driving circuit and the scanning line driving circuit is formed on the same substrate as a substrate on which a display unit for screen display is formed. apparatus.