JP2003108056A - Display memory, driver circuit, and display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display memory, a driver circuit, and a display device using the driver circuit which reduce the power consumption and enable quick plotting and eliminate a need of memory mapping. SOLUTION: A read circuit for CPU is connected to one bit line of a display memory, and a read circuit for display is connected to the other bit line, and a write circuit is connected to both bit lines, and the read circuit for CPU and the write circuit are assigned for access from a CPU, and the read circuit for display is assigned for screen display on the display device, and access from the CPU and read to the display screen are assigned to both level periods different by clock signals of the memory and are controlled independently of each other. A driving power of the display memory is separated to supply a driving supply voltage to the display memory by memory cells or plural memory cells.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display memory for storing pixel data to be supplied to pixels of a display, a driver circuit having the display memory, and a display using the driver circuit.

[0002]

2. Description of the Related Art Liquid crystal displays make use of features such as light weight, thinness, and low power consumption, and are used in mobile phones and PDAs (Personal).
Widely used as a display system for portable information devices such as Digital Assistants). In addition, with the spread of mobile phones and the Internet, it is strongly demanded that the display of mobile information devices should have higher image quality such as larger size and color support, and ultra-low power consumption for long-term use. Therefore, it has become important for liquid crystal drivers to realize low power consumption while responding to large screens and colorization.

However, in the conventional liquid crystal driver configuration, the LS
I have been working to reduce the power consumption of the internal logic circuit by various methods.
It was accompanied by an increase in power consumption.

In order to realize low power consumption, a method of incorporating a display memory (also called a frame memory) in a liquid crystal driver has been adopted. This eliminates the need for a controller memory to transfer display data, reducing the number of parts and reducing power consumption. In addition, power consumption was reduced by adopting a new drive method.

Regarding this problem, for example, Japanese Patent Laid-Open No. 7-6
Japanese Patent No. 4514 discloses a liquid crystal driver having a built-in general-purpose memory that realizes high speed and low power consumption, and a liquid crystal display using the driver. Further, Japanese Patent Laid-Open No. 2000-293144 discloses a liquid crystal display device using a liquid crystal driver with a built-in memory, which can perform drawing operation at low power consumption and high speed and reduce the load on the CPU 2. Further, in Japanese Patent Laid-Open No. 7-281634,
A liquid crystal display using a memory-embedded liquid crystal driver that realizes high-speed drawing access while achieving low power consumption is disclosed. Further, in Japanese Unexamined Patent Publication No. 7-230265, a method of supplying power is improved to realize a liquid crystal driving device having a low power consumption and a large-capacity memory. Also,
In Japanese Unexamined Patent Publication No. 7-175445, a display memory accessible by a general-purpose memory interface is built in a liquid crystal driver to achieve low power consumption and high drawing speed without lowering the operating efficiency of the system. .

[0006]

However, in the layout of a conventional liquid crystal driver LSI having a built-in display memory, the interface has terminals on one side of a general-purpose memory cell, and it is necessary to route general-purpose interface signal wiring. , The electric power for that wiring is required.

Further, in the conventional display memory, it is required to perform bus arbitration by using a data bus, an address bus and a control signal bus for display and drawing. Due to this, when the number of accesses for display is large, the time for drawing is reduced.

Further, in the conventional method, since the memory is accessed from the CPU 2 for every plural unit pixels, for example, when the data for one screen is to be stored in the memory from the CPU 2, (the number of pixels for one screen is ) / (The number of pixels in a plurality of unit pixels) write operations to the memory are required, so the number of memory operations was large. Since the operating power consumption of the memory is proportional to the number of writes / reads, the power consumption was high.

Further, when the display data was transferred from the memory to the liquid crystal panel, the display data for one horizontal line on the display screen was output at the same time. The data for one line is not used, but the output data line for the liquid crystal driver is used. For example, when trying to display the data for one screen stored in the memory on the LCD display screen, (the number of pixels for one screen) / (multiple unit pixels) times of reading the memory are required. There was a problem that power was consumed for the number of accesses.

Further, in the conventional method, it is necessary to operate at a high frequency of the memory, it is not possible to give a margin to the access time of the CPU 2, and there is a problem that it is not suitable for displaying a moving image which requires a quick screen change. there were.

Further, when the conventional memory is used, the images of the memory array and the pixel array of the liquid crystal are not the same, and it is necessary to calculate where the pixel is in the memory when drawing.

Further, in the conventional display memory, when writing data, all the data to be written are rewritten at once. Therefore, if there is data that you do not want to change in the data to be written at one time, you need to read the data before rewriting the data, change the bit to be rewritten while masking the data you do not want to rewrite, and write it to the memory. So-called read mod write (Rea
d modify Write) method was adopted. Therefore, there is a problem that the number of operations is large and power is consumed.

Further, conventionally, the image data stored in the display memory is converted into a digital-analog converter (Digital Analyst).
When outputting to gue Converter or DAC), RGB cannot be time-divided and output, so the output of the display memory was directly connected to the DAC on a one-to-one basis. Since a DAC is required for each RGB data, the number of DACs is large and power consumption is high. To reduce the power consumption of the DAC, it is necessary to adjust the settling time, and since it is different from the operation speed of the DAC and the display memory, it is necessary to control them separately. Depending on the characteristics of the DAC, the phase of the input signal can be adjusted. However, in the past,
When outputting the data in the display memory to the DAC, the timing for outputting the RGB data is fixed, and the phase of the data cannot be changed freely according to the characteristics of the DAC.
We could not meet such a need.

In order to reduce the power consumption of the liquid crystal liquid crystal display, there is a method of lowering the power supply voltage. However, if the operating power supply voltage becomes lower than 3.0V, a malfunction occurs. Furthermore, regarding the method of supplying power in consideration of power saving, there is a partial display mode used for the standby screen of mobile phones. In this partial display mode, nothing is displayed on the screen, but the leakage current of the memory cell There was also a problem that it was still flowing and consumed power.

The present invention has been made in view of the conventional problems, and its object is to reduce the power consumption, to perform drawing at a high speed, and to eliminate the need for memory mapping.
It is to provide a driver circuit and a liquid crystal display using the driver circuit.

[0016]

In order to achieve the object of the present invention, a display memory according to the present invention is a display memory for storing pixel data to be supplied to pixels of a display, the display memory comprising at least one pair of bits. Line, at least one column of memory cells having a first storage node and a second storage node capable of holding complementary first level and second level states, and one bit of the bit line pair A first read out of the stored data of the first storage node output to the line
Read circuit and a second read circuit for reading the storage data of the second storage node output to the other bit line of the bit line pair. Further, the second read circuit inverts the level of the storage data of the second storage node output to the other bit line and outputs the inverted data. The memory cell further includes a write circuit that outputs the data of the first level and the second level to the first and second storage nodes of each of the bit line pairs and writes the data to the display memory.

Further, the display memory includes control means for controlling the operation of the display memory, a write port including at least one of the write circuits, and a first read port including at least one of the first read circuits. When,
A second including at least one said second readout circuit
Read port, the first read port supplies data stored in the display memory to the display, and the second read port reads data from the display memory. And the write port writes the data from the control means to the display memory. Further, during the first level period of the clock signal of the display memory, the first read port makes a first access to output the data read via the first read circuit to the display. During the second level period of the clock signal of the display memory, the second read port and the write port output the data read via the second read circuit to the control means. , A second access for inputting write data to be written in the display memory from the control means.

Further, the display memory has a bit selecting means for selecting a memory cell to be written, and a write control signal inputted to the bit selecting means for controlling writing to the memory cell to be written, The write circuit is controlled by the bit selection means and the write control signal to apply the first level and the second level to the first and second storage nodes of the memory cell selected by the bit selection means. The data is output to each bit line pair of the memory cell to be written.

Further, the display memory has a driving power supply voltage source for the display memory, and a switching element for selectively connecting the power supply voltage supply end of at least one memory cell and the driving power supply voltage source. .

The first memory may be provided on one side of the display memory.
Access signal terminals are arrayed, the second access signal terminals are arrayed on the other side different from the one side, and the first interface for the first access and the second access Second interface is connected to the first access signal terminal and the second access signal terminal of the display memory, with the display memory interposed therebetween. Preferably, the first interface has a first line latch for storing one line of image data in the horizontal direction of the pixels arranged in the matrix, and the first line latch is used to store the image data. The write port outputs the data for one line to the selected bit line, and the second read port outputs the data for one line from the display memory to the control means. Preferably, the second interface has a second line latch for storing one line of image data in the horizontal direction of the pixels arranged in the matrix,
The first read port outputs the data for one line from the display memory to the display via the second line latch.

The display has a plurality of pixels arranged in a matrix, and the display memory has a plurality of memory cells arranged in a matrix corresponding to the matrix arrangement of the plurality of pixels. Pixel data for driving the pixels of the corresponding matrix of the display is stored in each memory cell by the write port, and the first read port latches the image data in the second line latch on a line-by-line basis. To the pixels of the corresponding line of the display.

In order to achieve the object of the present invention, a driver circuit according to the present invention is a driver circuit for outputting signals corresponding to image data stored in a display memory to pixels arranged in a matrix. The driver circuit has the display memory and functions as the display memory.

Further, in the driver circuit, the first interface has a first line latch for storing one line of image data in the horizontal direction of the pixels arranged in the matrix, and the first interface is provided. Via the line latch, the write port outputs the data for one line to the selected bit line, and the second read port controls the data for one line from the display memory. Output to the means. The first line latch stores, for each pixel, write control data designating pixel data to be written in the display memory among the pixel data latched by the first line latch. The port writes the pixel data latched by the first line latch designated by the write control data to the display memory.

The display has a plurality of pixels arranged in a matrix, and the display memory has a plurality of memory cells arranged in a matrix corresponding to a matrix arrangement of the pixels. Pixel data for driving the pixels of the corresponding matrix of the display is stored in each memory cell by the write port, and the first read port latches the image data in the second line latch on a line-by-line basis. To the pixels of the corresponding line of the display. Further, each pixel data in the pixel data for one line of the display latched by the first line latch is a pixel for driving each corresponding pixel in the pixels of the corresponding one line of the display by the write port. The data is stored in the display memory.

In the driver circuit, the second interface has a second line latch for storing one line of image data in the horizontal direction of the pixels arranged in the matrix, and the second interface is provided. The first read port outputs the data for one line from the display memory to the display through the line latch of. Preferably, the bit width of the second line latch is the same as the bit width of the image data for one line in the horizontal direction of the pixels arranged in the matrix. Preferably, the second interface sequentially selects R, G, B data included in the image data held in the second line latch, and converts the image data into a time division signal. And a digital-analog converter for converting a digital signal into an analog signal, wherein the selection circuit digital-analog converts the time-division signal obtained by time-division of R, G, B data included in the image data. The time-divided signal is converted into an analog signal and supplied to the display. Further, the selection circuit selects R, G, B data included in the pixel data held in the second line latch asynchronously with a clock signal of the display memory, and converts the R, G, B data into a time division signal. .

In order to achieve the object of the present invention, the display according to the present invention includes a display screen, a scanning circuit, the above-mentioned display memory, and the above-mentioned driver circuit, and the above-mentioned driver circuit and display memory. Produce the effect of.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a display memory, a driver circuit, and a display using the driver circuit according to the present invention will be described below with reference to the accompanying drawings. First Embodiment FIG. 1 is an overall configuration diagram of a first embodiment of a display 1 according to the present invention. Here, a liquid crystal driver and a liquid crystal display using the liquid crystal driver circuit will be described as an example. In the liquid crystal display 1 shown in FIG. 1, a processor (CPU) 2 for controlling the operation of the entire apparatus, a liquid crystal driver 3, a display screen 4 for displaying an image (in the case of a liquid crystal display, it is a liquid crystal panel 4), a liquid crystal panel 4 A scanning circuit 5 for selecting a row of pixels to which an address is applied in the horizontal direction and applying a voltage to each pixel to turn them on is included.

The liquid crystal driver 3 receives data for each pixel from the display memory 7 and the CPU 2 and writes the pixel data into the display memory 7 or reads the pixel data stored in the display memory 7 on the CPU side interface (CPU I / F). ) 6 and the pixel data including the red, green, and blue colors output from the display memory 7 and output to the liquid crystal panel 4 for display. F) Have 8.

The CPU side interface (CPU I / F) 6 is C
It has a data latch 9 for accumulating pixel data from PU2 and a selector circuit 10. Panel side interface
The (LCD I / F) 8 is a digital-analog that converts the data latch 11 that buffers the output of the memory, the selector circuit 12, and the image data to be displayed from a digital signal into an analog signal, and outputs the analog signal to the pixels of the liquid crystal panel 4. It includes a converter (DAC) 13.

In order to display an image on the liquid crystal panel 4, CP
Data for each pixel is transferred from U2, and is stored in the data latch 9 of the CPU I / F 6 for one line in the horizontal direction of the liquid crystal panel 4, and then that one line of data is simultaneously transferred to the display memory 7. It From the display memory 7, pixel data for one line in the horizontal direction of the liquid crystal panel 4 is simultaneously output and latched in the data latch 11 of the LCD I / F 8, and at the same time, a voltage according to the pixel data is applied to the liquid crystal panel. . Thereby, the pixel data is displayed on the screen.

In the present embodiment, the display memory 7 is composed of, for example, a single port SRAM. As shown in FIG. 2, the display memory 7 includes a memory cell 21, a sense amplifier 22 as a first read circuit, a sense amplifier 23 as a second read circuit, and a write circuit 2.
4, bit line pairs 25a and 25b, and word line 26. In FIG. 2, the memory cell 21 of the display memory 7
Are two inverters 29a and 29b whose input and output are connected to each other, and an NMOS as an access transistor.
A first storage node 28a is formed by the connection point of the output of the inverter 29a and the input of the inverter 29b, and has the second storage by the connection point of the input of the inverter 29a and the output of the inverter 29b. The node 28b is configured. Bit line 25a is NMOS
The bit line 25b is connected to the first storage node 28a via the transistor 27a and is connected to the NMOS transistor 27b.
Is connected to the second storage node 28b via.
Then, the NMOS transistors 27a, 2a of the memory cell 21
The gate of 7b is connected to a common word line 26.
When outputting data to the liquid crystal panel 4, the sense amplifier 22 is used to read image data from the memory 7. The sense amplifier 23 is used when the CPU 2 reads data from the memory 7. The CPU 2 writes the data in the memory 7 using the write circuit 24. RC1 and RC2 indicate control signals (sense amplifier control) of the sense amplifiers 22 and 23, and RD1 and RD2 are output data of the sense amplifiers 22 and 23.
(read data) is shown. Writing circuit 24 for WC and WD
Control signal (write control) and write data to the memory cell 21. Writing circuit 24
Has a first driver 24a, 24b connected in series and operating at a low level active control signal WC.

The display memory 7 of this embodiment is, for example,
It is a dedicated SRAM built in the liquid crystal driver 3. As shown in FIG. 2, as constituent elements of the memory cell 21,
The read-out sense amplifier 22 at the time of display and the sense amplifier 23 for the CPU 2 to read data from the memory cell are
The sense amplifiers 22 and 23 are connected to the bit lines 25a and 25b, respectively, and can control reading independently. The sense amplifier 23 and the write circuit 24 can operate simultaneously, that is, they can be read while writing.

Next, the operation of the display memory 7 will be described. The pair of CMOS inverters 29a and 29b may have, for example, V
Apply the drive power supply voltage of _DD = 3.3V. The CMOS inverter pair 29a, 29b is a bistable flip-flop circuit, and stores data "1" when the node 28a is at a high level and the node 28b is at a low level in the bistable state. Conversely, when the node 28a is at the low level and the node 28b is at the high level, it is defined that data "0" is stored.

When reading the data stored in the memory cell 21, first, the scanning circuit 5 scans the memory cell matrix, and a word line designated by a row address decoder (not shown), for example, a word line. 26 is selected, a voltage is applied, and NMOS transistors 27a, 2
7b becomes conductive. When reading bit by bit,
A memory cell to be further read, for example, the memory cell 21 is designated by a column address decoder (not shown). At this time, the read control signal RC1,
Alternatively, RC2 goes high, turning on sense amplifier 22 or sense amplifier 23. When reading is performed for each line or for each of a plurality of memory cells, a memory cell line including a memory cell 21, for example, or a plurality of memory cells to be read is designated by means not shown. Since the NMOS transistors 27a and 27b are conductive, the states of the nodes 28a and 28b are the sense amplifier 22 connected to the bit line pair 25a and 25b, respectively.
And 23.

When the data stored in the memory is output to the liquid crystal panel, the read control signal RC1 becomes high level, the sense amplifier 22 is turned on, and the current state of the memory cell 21, that is, the node 28a. The stored “1” or “0” is taken out from the sense amplifier 22. When reading the data stored in the memory from the CPU2, the read control signal RC2 goes high,
Sense amplifier 23 turns on and node 28
The value "0" or "1" complementary to the node 28a stored in b is inverted by the sense amplifier 23 to generate
Data having the same value as 8a is taken out.

When writing data from the CPU 2 to the memory cell 21, the memory cell or a plurality of memory cells are selected as described above, the word voltage is applied, and the NMOS transistors 27a and 27b are rendered conductive. The write control signal WC of the selected memory cell becomes low level, and the write circuit 24 is turned on. As shown in FIG. 2, the write circuit 24 has a first write driver 24a and a second write driver 24b, and the write data WD input to the write circuit 24 is first written in the second write driver 2a.
4b and is stored in the storage node 28b via the NMOS transistor 27b which is turned on. Second
The inverted output of the write driver 24b is input to the first write driver 24a and further inverted,
It is stored in the storage node 28a via the NMOS transistor 27a which is turned on. For example, write data W
When the value of D is 1, it becomes 0 at the output of the second write driver 24b and is stored in the storage node 28b. The output 0 of the second write driver 24b is input to the first write driver 24a, 1 is output, and stored in the storage node 28a. Similarly, when the value of the write data WD is 0, 0 is stored in the storage node 28a and 1 is stored in the storage node 28b.

FIG. 3 shows a main part of the liquid crystal driver 3 having the display memory 7 built therein. In FIG. 3, the same numbers are used for the same components as in FIG. In FIG. 3, the CPU-side interface circuit (CPU I / F) is designated by 6, and includes a data latch 9, a selector 10, and the like. Reference numeral 7 denotes a display memory of this embodiment, and 8 denotes an interface circuit for displaying a liquid crystal panel. The display interface 8 includes circuits such as a data latch 11, a selector 12 and a DAC 13.
Reference numerals 34 and 35 respectively denote a data bus for transferring the image data output from the memory 7 to the liquid crystal panel, and a data bus for the CPU 2 to transfer the data to the memory 7.

The liquid crystal driver 3 shown in FIG. 3 operates as follows. When the CPU 2 writes pixel data in the display memory 7, the CPU 2 sends image data to be displayed to the display memory 7 pixel by pixel. Pixel data sent for each pixel is first stored in the data latch 9. The data stored in the data latch 9 up to a predetermined number of bits is output to the selector 10, selected, and written to the display memory 7 via the data bus 35. Alternatively, when the CPU 2 reads the pixel data stored in the display memory 7, the display memory 7
The pixel data stored in is stored in the data latch 9 via the data bus 35 and the selector 10 in units of a predetermined number of bits, and the data held in the data latch 9 is stored in the CPU 2 for each pixel. Read out.

When the pixel data stored in the display memory 7 is read out and displayed on the liquid crystal panel, the pixel data stored in the display memory 7 is in units of a predetermined number of bits via the data bus 34 and the data latch 11. Held in. Then, the data held in the data latch 11 is output to the selector 12, and the selector 12 outputs each pixel data
The R, G, and B parts are sequentially selected by a predetermined method, output to the digital-analog converter (DAC) 13, and further output to the pixels of the liquid crystal panel.

In the present embodiment, the data bus 34 has the necessary number of data for one horizontal line of the liquid crystal panel. The number of data for one line is the number of pixels for one line x color
It can be calculated by (number of bits). Specifically, the number of pixels for one line is 176 pixels and the color is 18 bits (R, G, B
6 bits each) results in a 3168-bit output data bus. The number of bits of the data bus 35 is the same as that of the data bus 3
As in the case of 4, when the number of data bits for one line is 176 pixels and the color is 18 bits, it becomes 3168 bits.

As shown in FIG. 3 and above, the display memory 7 is
It has two read ports and one write port,
One read port and one write port
It is assigned to access from the CPU 2, and the other read port is assigned to the liquid crystal panel 4 for displaying pixel data. The read and write access from the CPU2 to the display memory can be performed simultaneously because the read access from the display memory to the liquid crystal panel is controlled independently.

Further, the read and write access to the display memory 7 of the CPU 2 and the read access from the display memory 7 to the liquid crystal panel 4 are performed in the high level period and the low level period of the clock signal for controlling the operation of the display memory 7. Access from the CPU 2 and the reading operation to the liquid crystal panel 4 are performed in parallel without interfering with each other.

FIG. 4 is a timing chart showing the above operation. In FIG. 4, (A) shows a read access address signal DRA for display. DRA is generated once for each line display. (B) shows an address signal CAA for the CPU 2 to access the display memory 7. (C) shows the clock signal MCLK of the display memory 7. The high level period of MCLK is
This is a period during which the CPU 2 accesses the display memory 7, and during this period, the CPU 2 reads image data from the display memory 7 or the CPU 2 writes image data into the display memory 7. The low level period of MCLK is used for the readout period for display. During this period, the image data stored in the display memory 7 is read out and output to the pixels of the liquid crystal panel. (D) shows a signal DR indicating a reading period for display. Reading from the display memory 7 is performed while the clock signal MCLK of the display memory 7 is at a low level. (E) indicates a signal CR indicating a period during which the CPU 2 reads from the display memory 7. The CPU 2 reads from the display memory while the clock signal MCLK of the display memory 7 is at a high level. (F) shows the signal CW indicating the period in which the CPU 2 writes to the display memory 7,
The CPU2 writes to the display memory while the clock signal MCLK of is high level.

According to the present embodiment, in the dedicated display memory with a built-in liquid crystal driver, each memory cell is equipped with two read sense amplifiers for the CPU and for display at both ends of the bit line, and for the CPU. By providing a write driver, it is possible to control access for display and read access from the CPU independently. Thereby,
Since two read ports and one write port can be equipped, they are assigned to the CPU and LCD panel display respectively, and the CPU access and display access are performed in the high level period and low level period of the system clock respectively. If assigned, the CPU and the reading operation for display can be performed in parallel, and they do not overlap. That is, the display operation, the drawing, and the data reading can be independently performed. As a result, even when the number of accesses for display increases, the time for drawing and reading is not reduced, and the CPU does not have to wait for display.

Further, in the display memory of this embodiment, terminals are provided on opposite sides of the display memory, and both interfaces are arranged with the display memory sandwiched therebetween. One of them is CP
It can be directly connected to the display memory for the U side interface and the other for the LCD panel side interface. As a result, there is no need to lay out the signal line, and the amount of wiring can be reduced as compared with the conventional general-purpose interface, and the power consumption for the wiring can be reduced. In addition, the normal Dual Port SRAM
Compared to the case of using the Single Port SR of the present embodiment.
AM can significantly reduce the cell size.

Second Embodiment In this embodiment, in order to further reduce the power consumption, an example will be described in which the power supply of the memory is divided and the power is independently supplied to different image data areas of the memory. The display memory according to the present embodiment has the configuration of the display memory according to the first embodiment, and further, in the present embodiment, the display memory is divided into a plurality of regions, and each divided region or operation mode is Power on / off is controlled.

FIG. 5 shows the structure of the display memory in which the power supply is divided. In FIG. 5, the same numbers are used for some of the same components as in FIG. In FIG. 5, 51a, 51b,
51c is a memory cell of the display memory 7 according to the first embodiment shown in FIG. 2, 52a and 52b are bit line pairs, 53a,
53b and 53c are word lines, 54a, 54b and 54c are N
Wells, 55a, 55b, 55c represent P wells. In the memory cell 51a, the N well 54a forms the PMOS transistors P1 and P2, and the P well 55a forms the NMOS transistors N1, N2, 27a and 27b. NMOS N1 and PMOS P1
Constitutes a CMOS inverter circuit 29a, and includes NMOS N2 and PMOS P
2 constitutes the CMOS inverter circuit 29b. This pair of CM
The OS inverters 29a and 29b are connected in a flip-flop configuration to form a bistable flip-flop circuit. When the driving voltage V _DD is applied to the pair of CMOS inverters 29a and 29b by the driving power supply line 56a, the bistable flip-flop circuit is set to 2 at the nodes 28a and 28b.
Two complementary stable states are maintained, nodes 28a and 2
A storage node 8b can store data. For example,
When the node 28a is at the high level and the node 28b is at the low level, it is defined as storing data "1". Conversely, when the node 28a is at the low level and the node 28b is at the high level,
It is defined that the information “0” is stored.

When reading this data, first, a word line voltage is applied to a word line designated by a row address decoder (not shown), for example, the word line 53a, and the NMOS transistors 27a and 27b are turned on. When reading bit by bit, a memory cell to be read, for example, the memory cell 51, is read by a column address decoder (not shown).
The memory cell 51a is selected by designating a, 51b, and 51c and designating the word line. When reading is performed for each line or for each of a plurality of memory cells, for example, a memory cell line including the memory cell 51a or a plurality of memory cells is designated. NMOS transistor 27
Since a and 27b are conductive, the states of the nodes 28a and 28b are transmitted to the read sense amplifier (not shown) connected to the bit line pair 52a and 52b.

When outputting the data stored in the memory to the liquid crystal panel, the current state of the memory cell 51a is taken out by a display sense amplifier (not shown). Also, C
When reading the data stored in the memory from PU2, use the CPU2 sense amplifier (not shown)
Retrieve the current state of 1.

When writing data from the CPU 2 to the memory cell 51a, the line of the memory cell
Alternatively, a plurality of memory cells or one memory cell are selected to turn on the NMOS transistors 27a and 27b, and the write data input to the write driver (not shown) is written to the NMOS transistors 27a and 27b.
It is stored in both storage nodes 28a and 28b via b. That is, when the value of the write data is 1, the storage node 28a is at a high level and the storage node 28b is at a low level, and when the data value is 0, the storage node 28a is at a low level and the storage node 28b is at a high level. To do. Since the memory cells 51b and 51c have exactly the same configuration as the memory cell 51a and operate in the same manner as 51a, the memory cell 5
In 1b and 51c, the same number as that of the memory cell 51a is used for each component other than the power supply.

Further, in the present embodiment, as shown in FIG. 5, the PMOS transistors Tr1, Tr2, and Tr which function as power supply switching to the drive power supply lines 56a, 56b, 56c of the memory cells 51a, 51b, 51c, respectively.
3 are connected, and memory cells 51a, 51b, and 5 are connected.
Controls turning on / off of power to 1c.

Memory cells 51a, 51b and 51c
Drive power lines 56a, 56b, and 56c are connected to each other, and Nwe11 54a, 54b, and 54c are separated from each other. Furthermore, the drive power supply lines 56a, 56b, 56
c is a transistor Tr1, Tr2, Tr for turning the power on and off
3 are connected to the drive power supply lines 56a, 56b, 56c of the PMOS transistors of the memory cells 51a, 51b, 51c via the memory cells 3, so that the power supply to the memory cells 51a, 51b, 51c is also separated from each other. In FIG.
The VDD controllers VCTR1, VCTR2, and VCTR3 control ON / OFF of the transistors Tr1, Tr2, and Tr3, and thereby control power on / off of the memory cells 51a, 51b, and 51c. This control is VDD controller VCTR
Set in 1, VCTR2, and VCTR3 operating modes.

Although an example of three cells is shown here,
The same applies to the case of division into three cells or more. Further, although one power switch transistor is provided in each memory cell here, it is no problem to collectively control the power supplies of the memory cells in a predetermined area of the memory according to the actual conditions.

According to the display memory of the present embodiment, the power supply is separated for each predetermined area of the memory, and the on / off of the power supply is controlled independently to reduce the leak current of the memory cell in the unused area. it can. Further, by separating Nwe11 of the memory cell, it is possible to reduce the power consumption by cutting off the power supply to the unused memory cell area.

Third Embodiment The display memory according to this embodiment has the same basic configuration as the display memory according to the first embodiment. However, in the present embodiment, the address array of the display memory corresponds to the pixel array of the liquid crystal panel so that the image of the image data stored in the display memory becomes the same as the screen of the liquid crystal panel. Further, read or write access to the display memory is performed in units of pixel data for one row on the screen. FIG. 6 is a schematic diagram of the address array of the display memory and the pixel array of the liquid crystal panel according to the present embodiment. Figure 6
At line line 0 to line N and pixel pixel 0
~ The array with pixel N as a subscript represents the address array of the memory and the pixel matrix of the liquid crystal panel. The image of the memory address and the pixel array of the liquid crystal panel is the same. That is, the addresses of the memory are distributed according to the arrangement of the pixels of the liquid crystal panel. For example, the number of memory cells connected to one word line of the memory and the number of memory cells connected to a pair of bit lines are as follows. Determined by the number of color bits.

Since the arrangement of the addresses of the memory and the arrangement of the pixels of the liquid crystal panel are the same, the lines line 0 to
Of the data stored in the memory, the data of the pixel to be accessed can be specified with the subscripts of line N and pixels pixel 0 to pixel N. From the CPU2, a line address and a pixel address are designated, and reading and writing are performed. When displaying on a liquid crystal panel, a line address is designated and the operation for reading one line at a time is performed.

Next, the read or write operation will be concretely described in units of one row of pixel data. FIG. 7 shows a configuration for accessing the display memory for each line.
In FIG. 7, reference numeral 71 denotes a plurality of display sense amplifiers, 7
2 is a memory cell for one line of the liquid crystal panel, and 73 is a plurality of memory cells.
A write driver for CPU, and 74 are sense amplifiers for a plurality of CPUs, respectively. The memory cell 72 for one line of the liquid crystal panel serves as a unit of transfer data at the time of reading and writing, and reading and writing are performed with this amount of data. The display sense amplifier 71 is equipped with the number of pixels for one row of the liquid crystal panel. When the data stored in the display memory is read and output to the liquid crystal panel, these sense amplifiers all operate at once. CPU
Write driver 73 is a display sense amplifier 71.
It is equipped with the same number as. When the CPU 2 reads the data stored in the display memory, these write drivers 7
All 3 work at the same time. The CPU sense amplifier 74 is
The same number of display sense amplifiers 71 and CPU write drivers 73 are provided. When the CPU2 writes data to the display memory, these sense amplifiers all operate at the same time. Note that the write driver at the time of writing can simultaneously write to a required place (bit or a plurality of predetermined bits) according to a write control signal for each bit described later.

In this embodiment, since the liquid crystal panel and the memory address array are handled by the same subscript, a simple mapping is performed, so that the calculation for associating the address and the pixel of the liquid crystal panel is not necessary, and , It is easy to support liquid crystal panels with various numbers of pixels. In addition, the number of times the memory is read to display one line can be reduced to one. In addition, the CPU 2 also has a circuit that can access pixel information from a row by row. That is, the operation of the memory is based on the access for one line. As a result, the number of memory operations can be reduced and low power consumption can be realized.

Fourth Embodiment In the conventional display memory, when it is desired to write a predetermined bit, read-modify-write is required, that is, data is not read and rewritten before data is rewritten. Change the bit to be rewritten while masking the data and write to the memory. In this embodiment, a column decoder for designating a memory cell in the bit direction and a write signal for controlling a write operation are provided on the above-mentioned display memory so that any one memory cell can be selected and only any bit can be written. The display memory will be described. The display memory according to the present embodiment has the basic configuration of the display memory according to the first embodiment.

FIG. 8 shows a main part of the display memory according to this embodiment. In FIG. 8, some of the same components as in FIG. 2 have the same numbers. In FIG. 8, 81a and 81b
Is a memory cell, 82 is a memory row decoder, and 83a, 8
Reference numeral 3b denotes write drivers for the memory cells 81a and 81b, respectively. Further, 84a and 84b are column decoders and 85
Is a read row address latch, 86 is a pixel address latch, and 87 is a write data latch. 88a and 8
8b, 88c and 88d are memory cells 81a and 8a, respectively.
1b indicates a bit line pair, and 89 indicates memory cells 81a and 8a.
1b shows a common word line. In FIG. 8, the memory cell 81a has two inverters 29a and 29b whose input and output are connected to each other, and NMOS transistors 27a and 27b as access transistors. Constitutes a first storage node 28a, and a connection point between the input of the inverter 29a and the output of the inverter 29b constitutes a second storage node 28b. The bit line 88a is connected to the first storage node 28a via the NMOS transistor 27a, and the bit line 88b is connected to the second storage node 28b via the NMOS transistor 27b. The gates of the NMOS transistors 27a and 27b of the memory cell 81a have a common word line 89.
It is connected to the. The write circuit 83a includes a first driver 24a which operates with a control signal formed by the output of the column decoder 84a connected in series and active at a low level.
24b. The row address decoder 82, based on the row address data of the read row address latch 85,
A word line voltage is output to a common word line of a predetermined memory cell row to turn on the NMOS transistors 27a and 27b. The output of the column address decoder 84a is inverted based on the column address data of the pixel address latch 86,
The write drivers 24a and 24b of the memory cell column to be written in the bit direction are input and operated. The write signal WRT is input to the column decoder circuits 84a and 84b, and WRT
Column decoders 84a, 84b only if the signal is high
Works.

Next, the operation of the memory having the above configuration will be described. When the drive voltage V _DD is applied to the CMOS inverter pair 29a and 29b, the bistable flip-flop circuits 29a and 29b hold two complementary stable states at the nodes 28a and 28b, and the nodes 28a and 28b store data. I can remember. For example, when the node 28a is at the high level and the node 28b is at the low level, it is defined that the data "1" is stored. Conversely, when the node 28a is at the low level,
When the node 28b is at the high level, it is defined as storing data "0".

Since the NMOS transistors 27a and 27b are in the conductive state, the nodes 28a and 28b are connected to the write driver 83a via the bit line pair 88a and 88b, and data can be written. For example, when writing data from the CPU 2 to the memory cell 81a, based on the row address data of the read row address latch 85,
The row address decoder 82 selects, for example, the word line 89, applies a voltage to the word line 89, and the NMOS transistors 27a and 27b are rendered conductive. Next, it is assumed that the column address decoder 84a designates a memory cell to be written in the bit direction, for example, the memory cell 81a based on the column address data of the pixel address latch 86. The memory cell 81a is selected together with the designation of the word line.

In this embodiment, the write signal WRT for controlling the write operation to the memory cell is applied to the column decoder circuit 84.
Only when input to a, 84b and the WRT signal is high level,
Writing to the memory cells designated by the coders 84a and 84b in the column is possible. For example, as described above, when the memory cell 81a is selected and the WRT signal is at high level, the output of the column decoder element 84a becomes low level and the write driver 83a becomes operable. Therefore, the data held in the write data latch 87 is transferred to the memory cell 81 a designated by the row decoder 82 and the column decoder 84.
Can be written on. As shown in FIG. 8, the write driver 84a has a first write driver 24a and a second write driver 24b. The data held in the write data latch 87 is written in the write driver 8 one after another.
4a, and the data of each bit is first inverted by the second write driver 24b and turned on.
It is stored in the storage node 28b via the NMOS transistor 27b. The inverted output of the second write driver 24b is input to the first write driver 24a, further inverted, and turned on.
It is stored in the storage node 28a via 7a. For example,
When the value of the write data is 1, it becomes 0 at the output of the second write driver 24b and is stored in the storage node 28b. The output 0 of the second write driver 24b is input to the first write driver 24a, 1 is output, and stored in the storage node 28a. Similarly, when the value of the write data is 0, 0 is stored in the storage node 28a and 1 is stored in the storage node 28b.

On the other hand, when the WRT signal is low level, the output of the decoder element 84a designating the memory cell 81a becomes high level and the write driver 83a of the memory cell 81a becomes inoperable. The data held in 87 cannot be written in the memory cell 81a designated by the row decoder 82 and the column decoder 84.

The memory cell 81b operates in the same manner.
The display memory of the present embodiment has a write control signal (write signal) for each bit, and based on this control signal, the CP
U2 can write only one arbitrary bit to the display memory. Compared with the conventional display memory, the same effect is realized only by the writing operation without performing the reading operation in advance. The number of memory operations can be reduced by the write method that does not require read-modify-write. As a result, the power consumption of the memory can be reduced.

Fifth Embodiment As described above, in the display memory of the present invention, since the terminals are arranged on opposite sides of the memory with the memory interposed, one terminal for the CPU is One terminal can be arranged for the liquid crystal panel. In the liquid crystal driver of the present invention, the CPU interface and the liquid crystal panel interface sandwich the display memory and are arranged at both ends of the display memory. Between the display memory and the CPU2, the interface for the CPU, between the display memory and the liquid crystal panel,
It has an interface for a liquid crystal panel.

This embodiment relates to data transfer between the CPU interface and the display memory. FIG. 9 shows a schematic circuit configuration of a part of the CPU side of the liquid crystal driver according to this embodiment. In FIG. 9, 91 is a line latch circuit, 92 is a selector circuit, 93 is a data bus, and 94 is a display memory. Image data is sent from the CPU2 or logic circuit for each pixel. Pixel data sent for each pixel is first stored in the data latch 91. Data latch 91
When the data for one line of the liquid crystal panel is stored in, the data is output to the selector 92, selected, and written in the display memory 94 via the data bus 93. Alternatively, when the CPU 2 reads the pixel data stored in the display memory 94, the pixel data stored in the display memory 94 uses the data for one line as a unit and the data bus 94
Via the selector 92, the data latch 91
The data held in the data latch 91 is read out to the CPU 2 for each pixel. The data in the display memory 94 is read out and displayed on the liquid crystal panel side.

The bit width of the line latch 91 is the same as the bit width of the image data for one line in the horizontal direction of the display screen. For example, if the size of the LCD panel is 176 pixels x 240 rows, and R, G, and B colors are each represented by 6 bits and 260,000 colors can be displayed, then the required memory capacity is 176 x 3 x 6
× 240 is 760320 bits, and the data capacity and bit width of the line latch 91 is 176 × 3 × 6 × 1 which is 3168 bits. The data bus 93 also has the same bit width.

FIG. 10 shows a timing chart of the write operation in units of lines by the circuit configuration of FIG. Figure 10
, (A) is the image data DATA for one pixel sent from the CPU side, and (B) and (C) are the addresses in the X direction (column direction) and Y direction (row direction) in the display memory 94. Shows ADD-X and ADD-Y. (D) is a write command XLATW from the CPU 2 to the line latch 91, and (E) is a line latch 91.
Write commands XRAMW, (F) from the display memory 94 to the display memory 94 indicate latch data, respectively. The data stored in the line latch 91 can be read out to the CPU side. Image data for one line is input from the CPU side while specifying the X address for each pixel. At this time, XLATW inputs "L", and the image data of each pixel is sequentially stored in the position corresponding to the X address in the line latch 91. After the image data for one line is stored in the line latch 91,
When the Y address is designated and XRAMW is set to "L", the image data for one line stored in the line latch 91 is written in the position designated by the Y address in the display memory 94.

The read command from the line latch 91 to the display memory 94 is XRAMR. FIG. 11 shows a timing chart of a read operation in units of lines by the circuit configuration of FIG. 11, (A) and (B) show addresses in the display memory 94 in the X direction (column direction) and in the Y direction (row direction) ADD-X and ADD-Y. (C) is a read command XLATR from the line latch 91, (D) is a read command XRAMR from the line latch 91 to the display memory 94,
(E) shows the latch data, and (F) shows the read image data DATA for one pixel. From the CPU side, specify the Y address of the position you want to read from the display memory 94 and XRAMR
Is set to "L", the data at the position designated by the Y address in the display memory 94 is read, and the data for one line is stored in the line latch 91. In line latch 91
After the data for one line is stored, XLATR is set to "L" and the X address is designated pixel by pixel to read the data stored in the line latch 91. In this way
It is possible to read and write access to the memory on a line-by-line basis.

By providing a line latch for one line between the display memory and the CPU 2, the read and write operations to the display memory are simultaneously performed for one line, thereby reducing the number of accesses to the display memory. . Since the operating power consumption of the display memory is proportional to the number of accesses, low power consumption can be realized.

Sixth Embodiment In the liquid crystal driver according to the present embodiment, based on the configuration of the fifth embodiment, the arrangement of pixels on the liquid crystal panel, the arrangement of addresses of the display memory, and the addresses of the data in the line latches. And correspond one-to-one, and writing can be performed from the line latch to the display memory for each pixel. The liquid crystal driver of the present embodiment is similar to the display memory described in the third embodiment in that the pixel array on the liquid crystal panel and the address array of the display memory have a one-to-one correspondence. That is, a display memory having X-direction and Y-direction addresses corresponding to the X (column) and Y (row) coordinates on the liquid crystal panel is provided, and the X and Y coordinates on the display panel and the X and Y directions of the display memory are provided. Address positions are associated one-to-one.

Next, with reference to the timing chart of FIG. 10, the writing operation from the line latch to the display memory for each pixel will be described with reference to FIGS. 12 and 13 and the timing chart of FIG. FIG. 12 shows the writing operation for each pixel. In FIG. 12, 121 is
Data bus for image data (number of data pits for 1 pixel) sent from CPU2 or logic circuit, 122 is line latch, 123 is data bus for reading or writing data from line latch 122 to display memory (Number of data pits for one line), 124 is a display memory, and 125 is a data bus sent to the liquid crystal panel side for displaying the data of the display memory. The display memory 124 has X-direction and Y-direction addresses corresponding to X- and Y-coordinates on a liquid crystal panel (not shown), and the sizes in the X-direction and Y-direction have the data sizes in the X-direction and Y-direction for one screen. . The line latch 122 stores the data for one line from the CPU 2 (not shown), the position of the line latch 122 in the X direction, the X direction address in the memory 125, and the X on the screen.
The coordinates are in one-to-one correspondence.

Next, the address (05H,
The operation of writing the image data in (03H) will be described as an example. First, when writing is performed by designating the image data and the X address (05H) from the CPU side (that is, XLATW = "L" in FIG. 10), the image data is written at the position indicated by the address 05H on the line latch 122. Is stored. At the same time, after the image data is written in the line latch 122, XRAMW = "L" is set and the Y address (0
If 3H) is specified, the color data of one pixel is written at the address position (05H, 03H) in the memory.

Next, referring to FIG. 13, a method for realizing the above-described operation of writing in the display memory 124 for each pixel will be described. In FIG. 13, 131 is a part of the display memory,
132 is a line latch. In the line latch 132, 133 is a storage area occupied by one pixel, and
34 is a write flag (WRITE FLA) provided for each pixel.
G). As shown in FIG. 13, the line latch 132
Then, for each pixel address, the line latch 13
A write flag for writing data from 2 to the display memory 131 is provided, and WRITE FLAG is set to stand only for the pixels written in the line latch 132 from the CPU side (that is, WRITE FLAG = 1). When writing to the display memory 131, only the pixels for which the WRITE FLAG has become 1 are written, so that only the desired pixels can be written and the surrounding pixel data are not affected. Further, this WRITE FLAG can be used to rewrite only arbitrary plural pixels on the same line. Line latch 132 to display memory 1
After writing data to 31, this WRITE FLAG is all
Reset to O.

FIG. 14 is a timing chart showing the above operation. In FIG. 14, (A), (B), (C), (D),
(E) and (F) are latch write signals Latch WriteRQ,
Line write signal Line WriteRQ, write address signal WriteADR, clock signal CK, write flag signal Writ
e Flag and word line signal WL are shown. As shown in FIG.
The line latch 13 indicated by the write address signal WriteADR
When writing is performed on the second pixel, the latch write signal Latch WriteRQ becomes high level for the pixel, that is, Latch WriteRQ = 1. Then, the write flag signal Write Flag of the pixel is set, that is, becomes a high level (Write Flag = 1). Line latch 132
The line write signal Line WriteRQ is set to the pixel of the memory 131 corresponding to the pixel of Write Flag = 1, and becomes a high level, that is, Line WriteRQ = 1. A voltage is applied to the word line WL designated by the write address signal WriteADR of the display memory 131 to enable writing to the pixel of the memory associated with the word line WL, and
Writing starts (Write Start). That is, the display memory 1
When writing to 31, the data is written only to the pixel (Line WriteRQ = 1) corresponding to the pixel of Write Flag = 1 of the line latch 132 of the display memory 131. Write
It is also possible to rewrite only arbitrary multiple pixels on the same line using Flag. After writing data from the line latch 132 to the display memory 131 (Write End)
Causes the Write Flag to be reset to O.

Conventionally, since the read / write to the display memory is performed for every plural unit pixels, if it is desired to write one pixel in the display memory from the CPU2, if the data for one pixel is directly written, it is It will rewrite multiple pixels of. Therefore, a read-modify-write sequence is performed in which pixels of a plurality of units are read once, only the data of the pixel to be rewritten is rewritten outside the memory, and the rewritten plural unit pixels are stored in the memory. By giving the above-mentioned WRITE FLAG to the line latch, it is possible to rewrite only the pixel to be written. By having the WRITE FLAG for each pixel in the line latch, the desired pixel data can be written without affecting the pixel data around the pixel to be written.
The read-modify-write sequence, which was required in the past, is no longer required.

In addition, X, Y on the screen outside the display memory
There is no need to generate a memory address corresponding to the coordinates. From the CPU side, simply specify the X and Y coordinates on the screen as the X and Y addresses, and the image data is displayed in pixel units at the memory location corresponding to the screen. Can write. Further, even when writing a plurality of pixels on the same line, the line latch and the display memory need only be accessed once.

Seventh Embodiment As described above, in the display memory of the present invention, since the terminals are arranged on the opposite sides of the memory with the memory sandwiched, one terminal is used for the CPU. One terminal can be arranged for the liquid crystal panel. In the liquid crystal display of the present invention, the CPU interface and the liquid crystal panel interface have a configuration in which the display memory is sandwiched and the CPU interface and the liquid crystal panel interface are arranged at both ends of the display memory. Between the display memory and the CPU2, the interface for the CPU, between the display memory and the liquid crystal panel,
It has an interface for a liquid crystal panel.

This embodiment relates to data transfer from the display memory to the liquid crystal panel interface. Figure 15
Shows a partial circuit configuration on the panel side of the liquid crystal display according to the present embodiment. In FIG. 15, 141 is a display memory, 142 is a data latch circuit, 143 is a selector circuit, and 144 is a digital-analog converter (DAC). Reference numeral 145 is a data bus for the liquid crystal panel, and 145
Pixel data is read from the display memory 141 to a liquid crystal panel (not shown) via. The line latch 142 can store data for one line in the horizontal direction on the screen, and the bit width is the same as the bit width for one line. For example, if the size of the liquid crystal panel is 176 pixels x 240 rows, and the three colors of R, G, and B are represented by 6 bits, and 260,000 colors can be displayed,
The required memory capacity is 176 × 3 × 6 × 240, which is 760320 bits, and the data capacity and bit width of the line latch 142 is 176 × 3 × 6 × 1, which is 3168 bits.

When the pixel data stored in the display memory 141 is read out and displayed on the liquid crystal panel, the pixel data for one line is set as a unit in the horizontal direction of the liquid crystal panel (not shown), via the data bus 145. Data latch 14
Held at 2. Then, the data held in the data latch 142 is output to the selector 143, and the selector 14
The R, G, and B parts of each pixel data are sequentially selected by the predetermined method by 3, and the digital-analog converter (DAC) 1
44, and further to pixels of the liquid crystal panel.
Thereby, the pixel data is displayed on the screen. In this way, the line latch 142 performs a series of operations of fetching one line of data in the horizontal direction on the liquid crystal screen from the display memory 145 and outputting the data to the DAC 144 at a constant cycle.

In addition, 1 stored in the display memory 145
The operation of writing the line data into the line latch 142 is performed in synchronization with the clock of the display memory. After the data for one line is held in the line latch 142, the memory 145 can be freed, so that the time thereafter can be devoted to the access time of the CPU2, and as a result, the screen display needs to be switched quickly. Can also be used.

As described above, in a liquid crystal driver having a built-in display memory, in order to drive one line at a time in the horizontal direction on the liquid crystal panel screen, DACs operating simultaneously are used.
Need a latch circuit to hold the data. 1 between the display memory and DAC in the horizontal direction on the LCD panel screen
By providing a latch circuit having a capacity necessary to hold data for one line, it becomes possible to read / write one line of data at a time in the horizontal direction on the liquid crystal panel screen, and to access the memory. The number of times can be reduced and power consumption can be reduced.

Eighth Embodiment The configuration of the liquid crystal display according to this embodiment is substantially the same as that of the seventh embodiment. The difference is that the data held in the line latch is converted to a digital-analog converter. When output to (DAC), the selector circuit (selector) that can output the data by time division (RGB time division) with three colors of red (red), green (green) and blue (blue) , RGB selector). FIG. 16 shows the configuration of the main part of the liquid crystal display according to this embodiment. In FIG. 16, reference numeral 150 denotes a liquid crystal panel and 151 denotes
RGB selector circuit, 152 is line latch circuit, 153
Is a data bus for image data sent from the display memory, 154 is a data bus for image data output from the line latch 152, 155 is a display memory, and 156 is a data bus for image data output from the selector circuit 151, 1
57 is a digital-analog converter (DAC), 158 is R
Time-divided red (Red), green (G
reen), and image data having a blue (Blue) color, R, G,
Selector circuit for converting to B pararail data, 159
Are pixels represented by red, green, and blue colors.

The liquid crystal display having the above structure operates as follows. The image data sent from the display memory 155 is output to the line latch 152 for each line and held. The data held in the line latch 152 is synchronized with the horizontal synchronizing signal (Hsync), and DAC 157
To the digital-analog converter (DAC) 157. The R, G, and B components of the image data are switched by the RGB selector 151 asynchronously with the clock of the memory, and are time-divided. It by this,
The number of output terminals of the selector 151 and the number of DACs 157 is one third of the bit width number of the line latch 152. DAC157
The time-division image data output from the selector circuit 158
Is divided into R, G, B data, becomes R, G, B pararail data, which is output to the pixel 159 and displayed.

For example, the size of the liquid crystal panel 150 is 176.
Pixel x 240 lines, each of R, G, B three colors is represented by 6 bits. If 260,000 colors can be displayed, RGB selector 151
Has an input terminal of 3168 bits, which is the same as the bit width of the line latch 152, and outputs R, G, and B data of 6 bits to one DAC 157 by switching in time division.
Therefore, the selector 151 has an output terminal of 1056 bits.

The data held in the line latch 152 is output to the DAC 157 in synchronization with the horizontal synchronizing signal (Hsync). At that time, the RGB selector 151 switches the R, G, and B components of the color image data, and outputs them in time division. Conventionally, when outputting the data of the memory to the DAC, the output of the memory was directly connected to the DAC on a one-to-one basis without outputting RGB in a time division manner. By outputting the image data by time-sharing with RGB, the output of the line latch 152 is 1: 1 with the DAC 15
The number of DACs 157 can be reduced to one-third as compared with the case of directly connecting to seven.

When the data held in the line latch 152 is output to the digital-analog converter (DAC) 157, RGB switching of the color image data is controlled asynchronously with the clock of the memory. There is. FIG. 17 is a timing chart of RGB time division of the output data of the line latch 152. In FIG.
(A) is the memory clock signal, (B) is the line latch 152
Output data (3168 bits), (C), (D) and (E) are red (R) data, green (G) data, blue (B) data, (F) is RGB data output by the RGB selector circuit. Indicates (1056 bits). The R, G, B data output from the line latch 152 is converted into a time division signal asynchronously with the clock by the RGB selection circuit 151, and output from the same terminal as the RGB selection circuit 151. The 3168-bit data output from the line latch 152 becomes 1056 bits at the output terminal of the RGB selection circuit 151.

Conventionally, in order to reduce the power consumption of the DAC,
It is necessary to adjust the settling time. Since the operation speeds of the DAC and memory are different, it is necessary to control them separately. However, when outputting the data of the display memory to the DAC, the timing of outputting the RGB data is fixed, and the phase of the data cannot be freely changed according to the characteristics of the DAC. According to the present embodiment, the RGB switching of the data output to the DAC can be controlled asynchronously with the clock of the memory, so that it can be adjusted according to the settling time of the DAC and even if an interrupt occurs. The read system is not disturbed. Also, the power consumption can be reduced because the timing can be adjusted according to the settling time of the DAC. The DAC and memory can be controlled separately, and different operating speeds can be supported. Furthermore, the phase of the input signal can be easily adjusted. By providing an RGB selector that can output the data to be output to the DAC by RGB in a time-division manner, the output of the line latch can be
The number of ACs can be significantly reduced (two thirds), and the power consumption can be significantly reduced.

Next, an example of a suitable configuration of the liquid crystal driver according to the above-mentioned embodiment will be described. This LCD driver is, for example, a single port or dual
One-chip driver with built-in port display memory (frame memory), oscillator, timing generator, liquid crystal gradation display reference voltage source, and CPU interface circuit
IC. Specifically, 176 (H) x 3 x 6 (RGB) x 240 (V) = 76
It has a built-in 0320-bit dual port memory and is designed to support liquid crystal panels with different numbers of pixels such as 120 x 160 dots, 132 x 176 dots, 144 x 176 dots, 176 x 240 dots depending on the settings. The applicable liquid crystal panel has, for example, a diagonal length of about 2.2 inches, and the horizontal driver is a TFT selector and the memory built-in driver I of the present invention.
Including C, vertical driver becomes TFT driver, CO
It is implemented by F method or COG method. The 1H / 1V (VCOM inversion) method is adopted as the inversion method.

The logic system terminal of this liquid crystal driver IC is CP
Chip select, read, write for U interface,
It has terminals for data bus, address bus, reset, main clock, horizontal sync, vertical sync, serial data, etc., and also has terminals for liquid crystal panel control.

It is assumed that the asynchronous mode, synchronous mode, color mode, screen mode, alternation mode, refresh rate, standby mode, etc. can be changed by setting the mode register of the present liquid crystal driver.

Specifically, in the asynchronous mode, the TFT
The timing of scanning the panel and the timing of rewriting the display memory by the CPU may be asynchronous. The display memory is a dual port memory, so the CPU cannot wait. The scan of the display memory and the TFT panel are synchronized, and the contents of the built-in display memory are D / D in parallel for each R, G, and B color by the clock of the internal / external oscillator.
When output in parallel to the A conversion circuit (self-refresh), when outputting in parallel, blue data in the first half period of one cycle of the clock signal of the vertical driver shift register, 1/3 period in the middle stage Is output as green data, and red data is output during the latter half of the period.

Asynchronous mode CPU interface and parallel interface. If you do not use the parallel interface, you can use the serial interface to perform the same function as the 8-bit parallel interface, except that the serial interface is write-only and not readable.

In the synchronous mode, the image data is continuously sent in synchronization with the image clock, the horizontal synchronizing signal and the vertical synchronizing signal. Since the TFT panel is scanned using the horizontal / vertical sync signal, all timings are synchronized with the scanning of the TFT panel. In the synchronous mode, normally, the image data is directly written in the line buffer immediately before the DAC, and the contents of the display memory retain the information before switching to the synchronous mode. In synchronous mode, image data is transferred without interruption, so there is a buffer that transfers data to the DAC and a buffer that sequentially receives data.
RGB data with 18-bit width is input to the line buffer that alternates in the (Hsync) cycle.
B data is sent to the DAC with a 6-bit width in the first 1/3 period of ync, then G data is sent to the DAC with a 6-bit width in the middle 1/3 period of Hsync. In 3 periods, B data is sent to DAC with 6-bit width. There is also a so-called capture type image data handling method in which the image data is temporarily taken into the display memory in the synchronous mode.

The synchronous mode RGB parallel bus interface will be described. By default, the image data is latched at the rising edge of the image signal clock synchronized with the image signal, but it can be changed from the CPU. By default, the polarity of the horizontal sync signal is negative (changeable from the CPU). One cycle consists of the horizontal blanking period + video signal period. By default, the polarity of the vertical sync signal is negative (changeable from the CPU). One cycle consists of the vertical blanking period + video signal period. The image signal is latched by the image clock.

Regarding the CPU interface in the synchronous mode, only the serial interface can be used in the synchronous mode. The serial interface is write-only and cannot be read. The serial interface is based on the operation in parallel 8-bit bus mode.

Various color modes can be set by setting the mode register of the liquid crystal driver. In full color mode, the built-in 6-bit DAC is used to convert and output each of the RGB 6-bits into 64-step voltage.

In the reduced color mode (8-color mode), the 6 bits of RGB are set to 1 page according to the page indicated by each special effect register.
Is the most significant bit (MSB) of the 6 bits, the page is the 2nd bit from the most significant bit when the page is 2, and the least significant bit (LSB) when the page is 6.
According to B), ground or output level VCC of high voltage power supply for output amplifier. At this time, the power supply to the built-in 6-bit DAC is stopped.

The screen mode will be described. Full screen mode displays the entire screen in the color mode specified by the status register. In partial screen mode, only the part specified by the status register is displayed in the color mode specified by the status register, and white is displayed in the specified color mode when scanning other parts. .

Next is the standby mode.
I will describe. During the transition to standby mode,
Refer to the value of the standby mode in the mode register, one phase per field period, and change the state according to that value. If the mode is entered, the sequence is restored and the sequence is restored. This LCD driver IC is in asleep mode after power is turned on or after a hardware reset.

In the awake mode, the internal oscillator starts oscillating from the asleep state → the DC / DC converter starts →
Panel reset → common voltage coupling capacitor quick charge → full white display sequence, then awake (normal) mode.

In the asleep mode, the sequence of full white display → common voltage coupling capacitor rapid discharge → panel reset → DC / DC converter stop → internal oscillator oscillation start sequence from awake state (normal) After running, it goes into asleep mode.

The display memory access mode will be described. Depending on the contents of the display memory access mode register, eight types of sequential memory access are available: portrait (vertical), landscape (horizontal), normal, mirror (mirror image), and usually upset (upside down).

The special function of the present liquid crystal driver will be described. With the image capturing function, the contents of the frame memory of the moving image signal are held while the capture of the frame memory access register is "0". capture is "1"
Then, one frame after the next vertical sync signal is taken into the frame memory. When capture changes from "1" to "0", the contents of the frame memory are retained after the next vertical sync signal.

With respect to the common voltage initial charging function, the DC cutting capacitor at the common voltage output terminal can be rapidly charged and discharged. A DC offset terminal is connected to the opposite side of the DC cut capacitor at the output terminal of the common voltage, and sag occurs. In order to suppress sag in the display mode as well, the DC offset terminal has a high resistance, and it takes time to charge and discharge the DC offset to the capacitor. However, when the power is turned on / off, unless the DC offset is rapidly charged / discharged, the display quality deteriorates during the transition period from the initial state to the steady state. In particular, an afterimage is displayed when a DC offset still remains after the power is cut off during discharging, which requires rapid charging / discharging.

In the reset function, the hardware
The reset is a reset by the reset signal from the reset pin connected to the CPU, and the register / frame memory is not reset. Software reset, reset by command from CPU, contents of display memory / some registers are retained.

In the contrast control function, the display that uses a lot of black consumes a large amount of power, so the contrast is lowered and the black display is avoided. (Reducing the contrast means increasing the brightness of black while maintaining the brightness of white.) For 6-bit RGB data, 00H → 6V amplitude charge / discharge the panel → black display → high power consumption. 20H → 3V amplitude panel charging / discharging → Gray display. 3FH → Charge panel with 0.4V amplitude → White display. So, divide it by 2 of 6 bits (discard the lower 1 bit) and get 20H
, 00H → 20H → Charge / discharge the panel with 3V amplitude → Black display, 20
H → 30H → Charge / discharge panel with 1.5V amplitude → Gray display,
3FH → 3FH → Charge the panel with 0.4V amplitude → White display. 30,000
Reduce the contrast by making it 2,000 colors.

The scroll function is a function of switching the data transferred from the frame memory to the panel by controlling the panel end memory pointer so that the data is rolled and displayed on the display. Roll start line, roll line width, roll speed / direction can be controlled by the dedicated register.

Negative-positive inversion
The sion function is a function that, when two points on the screen are specified by a dedicated register, the inside of a rectangle with the two points being diagonal is negative / positive inverted. The panel end memory pointer is monitored and the output of the display memory is inverted and sent to the DAC while the pointer is within the specified range.

The blinking function is a function in which, when two points on the screen are designated by a dedicated register, the inside of a rectangle having two points diagonally blinks. The panel end memory pointer is monitored, and the AND of the output of the display memory and the output of the blinking cycle counter is sent to the DAC while the pointer is within the specified range.

In the built-in DC / DC converter control function, the CPU sets a switch for setting use / sealing of the built-in DC / DC converter and ON / OF of each channel of the DC / DC converter.
F switch can be controlled.

In the built-in LED driver control function, the CPU
From, you can set the switch to use / seal the built-in LED driver and adjust the current sink capacity of the LED driver (8 levels).

The liquid crystal driver is provided with a large number of registers and pointers to realize the above specifications.

The present invention is not limited to the above-described embodiments, and within the scope of the present invention,
Various modifications are possible. In the first embodiment, the first access for outputting the data from the display memory to the pixel is performed during the low level period of the clock signal of the display memory, and the external control means reads the data from the display memory and outputs the data to the display memory. Although the second access for writing is performed during the high level period of the clock signal of the display memory, the first access may be performed during the high level period of the clock signal and the second access may be performed during the low level period of the clock signal. Good. Further, in the second embodiment, one power supply switch transistor is provided for each memory cell, but the power supplies of the memory cells in a predetermined area of the memory may be collectively controlled according to actual conditions.

[0116]

According to the present invention, two lines are provided on both sides of the display memory.
By providing a system read port and a system write port, the cell size can be significantly reduced compared to the case of using a dual port memory, and wiring resources and wiring power can be reduced. . Further, by assigning the display access and the CPU access to the memory to the high level period and the low level period of the clock signal of the memory, the waiting time of the CPU for the display can be reduced. By separating the power supply and supplying the drive power supply voltage to the memory, the power supply to the areas of the memory cells that are not used can be cut off, thereby reducing power consumption.

Read Modify Write (Read Mo
The number of memory operations can be reduced by a bit-by-bit or pixel-by-pixel writing method that does not require dify write). Since data can be written to the memory of only one arbitrary pixel with one access, the read-modify-write sequence is unnecessary. Rewriting on a pixel-by-pixel basis also consumes less power than before.

Since the simple mapping between the driver circuit and the memory array is enabled, the calculation for obtaining the correspondence between the address and the pixel of the display screen is not required, and the correspondence to the driver circuit having various numbers of pixels is made possible. Can be taken easily. By mapping the screen and memory and line latches, data can be written to the memory of only one arbitrary pixel, and data of any plural pixels on the same line can be written with one access to the memory. It is only necessary to specify the X and Y coordinates on the display screen as the address from the CPU side.

By providing a line latch between the processor and the display memory and operating by reading once for each line display, the number of times the memory is operated can be reduced, thereby reducing the power consumption of the memory. The display memory built into the driver circuit is equipped with a line latch between the display memory and the DAC that has the capacity necessary to hold one line of data in the horizontal direction on the LCD panel screen. By equipping the line latch with the same bit width as the above, it becomes possible to read / write one line of data at a time in any horizontal direction on the screen, and to reduce the number of memory accesses. Thus, power consumption can be reduced. By reading / writing the data for one line held in the memory at once in synchronization with the clock of the memory, the time after holding the data for one line can be allocated to the access time of the CPU. It can also be used for video displays that require quick screen switching.

The number of DACs is reduced to one third as compared with the case where the output of the line latch is directly connected to the DAC in a one-to-one correspondence by the RGB selection circuit capable of time-divisionally outputting the data to be output to the DAC in RGB. The power consumption can be reduced. Since the RGB switching of the data output to the DAC can be controlled asynchronously with the clock of the memory, the DAC and memory can be controlled separately, and different operating speeds can be supported. Further, even if an interrupt occurs, the read system is not disturbed, and the phase of the input signal can be easily adjusted. The power consumption can be reduced by adjusting the timing according to the DAC settling time.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a display according to the present invention.

FIG. 2 is a configuration diagram of a memory cell of the display memory according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram of a main part of a driver circuit according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing the operation of the display memory according to the first embodiment of the present invention.

FIG. 5 shows a configuration of a display memory in which a power supply is divided according to a second embodiment of the present invention.

FIG. 6 is a schematic diagram of an address array of a display memory and an array of pixels on a display screen according to a third embodiment of the present invention.

FIG. 7 shows a configuration for accessing a display memory in line units according to a third embodiment of the present invention.

FIG. 8 shows a configuration of a main part of a display memory that can be written bit by bit according to a fourth embodiment of the present invention.

FIG. 9 is a CP of a driver circuit according to a fifth embodiment of the present invention.
The schematic circuit configuration of the U side is shown.

FIG. 10 shows a timing chart of a write operation in line units of the driver circuit according to the fifth embodiment of the present invention.

FIG. 11 is a timing chart of an operation of reading line by line in the driver circuit according to the fifth embodiment of the present invention.

FIG. 12 shows a schematic circuit configuration of a driver circuit according to a sixth embodiment of the present invention when writing is performed for each pixel.

FIG. 13 shows a configuration in which a pixel can be written in a display memory for each pixel in a driver circuit according to a sixth embodiment of the present invention.

FIG. 14 shows a timing chart of an operation of writing pixel by pixel in a display memory using a write flag signal according to a sixth embodiment of the present invention.

FIG. 15 shows a schematic circuit configuration on a display screen side of a driver circuit according to a seventh embodiment of the present invention.

FIG. 16 shows a structure of a main part of a display according to an eighth embodiment of the present invention.

FIG. 17 shows a timing chart of RGB time-sharing of image data in the display according to the eighth embodiment of the present invention.

[Explanation of symbols]

1 ... Display, 2 ... CPU, 3 ... Driver circuit, 4 ...
Display screen, 5 ... Scanning circuit, 6 ... CPU I / F, 7 ...
Display memory, 8 ... LCD I / F, 9 ... Data latch, 10 ...
Selector circuit, 11 ... Data latch, 12 ... Selector circuit, 13 ... DAC, 21 ... Memory cell, 22 ... Display sense amplifier, 23 ... CPU sense amplifier, 24, 24a,
24b ... Write driver, 25a, 25b ... Bit line, 26 ... Word line, 27a, 27b ... NMOS transistor, 28a, 28b ... Storage node, 29a, 29b ... CMOS
Inverter, 34 ... Display data bus, 35 ... CPU data bus, 51a, 51b, 51c ... Memory cell, 52
a, 52b ... Bit line, 53a, 53b, 53c ... Word line, 54a, 54b, 54c ... N well, 55a, 55b,
55c ... P well, 56a, 56b, 56c ... Power supply line, 71 ... Display sense amplifier, 72 ... Memory cell for one line, 73 ... CPU sense amplifier, 74 ... CPU write driver, 81a, 81b ... Memory cell, 82
… Word driver, 83a, 83b… Write driver,
84a, 84b ... Column decoder, 85 ... Read data latch, 86 ... Pixel address latch, 87 ... Write data latch, 88a, 88b, 88c, 88d ... Bit line, 89 ... Word line, 91 ... Line latch circuit, 9
2 ... Selector circuit, 93 ... Data bus, 94 ... Display memory, 121 ... Data bus, 122 ... Line latch circuit,
123 ... Data bus, 124 ... Display memory, 125 ... Data bus, 131 ... Display memory, 132 ... Line latch, 133 ... Pixel, 134 ... Write flag, 14
1 ... Display memory, 142 ... Data latch circuit, 143 ...
Selector circuit, 144 ... DAC, 145 ... Data bus, 1
50 ... Display screen, 151 ... RGB selector, 15
2 ... Line latch circuit, 153 ... Data bus, 154 ...
Data bus, 155 ... Display memory, 156 ... Data bus, 157 ... DAC, 158 ... Selector circuit, 159 ... Pixel, RC1, RC2 ... Read control, RD1, RD2 ... Read data, WC ... Write control, WD ... Write data, Tr1 , Tr
2, Tr31 ... Power supply switching transistor, VCTR1, VCT
R2, VCTR3 ... VDD controller, WRT ... Write signal.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G02F 1/133 520 G02F 1/133 520 G09G 3/36 G09G 3/36 G11C 11/41 G11C 11/34 Z 11/413 J (72) Inventor Daishi Mizuta 2-3-2, Momochihama, Sawara-ku, Fukuoka-shi, F-term, Sony Semiconductor Kyushu Co., Ltd. (reference) 2H093 NA06 NA13 NA33 NC02 NC15 NC16 NC24 NC26 NC50 ND39 5B015 JJ03 JJ36 KA09 KA38 KB09 KB33 KB36 KB74 NN01 5C006 AA22 AF82 BB15 BC20 BF02 BF04 BF05 BF24 EB05 FA13 FA47 5C080 AA10 BB05 CC03 DD25 DD26 EE29 EE30 JJ02 JJ03 JJ04

Claims (43)

[Claims] 1. A display memory for storing pixel data to be supplied to pixels of a display, comprising: at least a pair of bit lines; and a first memory capable of holding complementary first level and second level states. At least one column of memory cells having one storage node and a second storage node; and the first output to one bit line of the bit line pair.
A first read circuit for reading the storage data of the storage node of the second storage node, and the second read circuit output to the other bit line of the bit line pair.
And a second read circuit for reading the storage data of the storage node. 2. The display memory according to claim 1, wherein the second read circuit inverts and outputs the level of the storage data of the second storage node output to the other bit line. 3. A write circuit for outputting the data of the first level and the second level to each of the bit line pairs to write to the display memory to the first and second storage nodes of the memory cell. The display memory according to claim 2, further comprising: 4. A control means for controlling the operation of the display memory, a write port including at least one of the write circuits, a first read port including at least one of the first read circuits, and at least one of: A second read port including the second read circuit, wherein the first read port supplies data stored in the display memory to the display, and the second read port includes the second read port. The data is read from the display memory and output to the control means, and the write port receives the data from the control means.
The display memory according to claim 3, wherein writing is performed in the display memory. 5. The first read port outputs the data read via the first read circuit to the display during a first level period of a clock signal of the display memory. Access, during the second level period of the clock signal of the display memory,
The second read port outputs the data read via the second read circuit to the control means,
5. The display memory according to claim 4, wherein the write port performs a second access for inputting write data to be written in the display memory from the control means. 6. The display memory has a bit selection unit that receives a write control signal and selects a memory cell to be written, and the write circuit has the first of the memory cells selected by the bit selection unit. 4. The display memory according to claim 3, wherein the data of the first level and the data of the second level are output to each of the bit line pairs of the memory cell to be written to the second storage node. 7. The display memory includes a driving power supply voltage source for the display memory, and a switching element for selectively connecting a power supply voltage supply terminal of at least one memory cell and the driving power supply voltage source. The display memory according to claim 3. 8. The first access signal terminal is arranged on one side of the display memory, and the second access signal terminal is arranged on another side different from the one side. An access first interface and a second access second interface sandwiching the display memory, the first access signal terminal of the display memory and the second access, respectively. The display memory according to claim 5, which is connected to the signal terminal for use. 9. The first interface has a first line latch for storing one line of image data in the horizontal direction of the pixels arranged in a matrix, and via the first line latch. The write port outputs the data for one line to a selected bit line, and the second read port outputs the data for one line from the display memory to the control means. 8. The display memory according to item 8. 10. The second interface has a second line latch for storing one line of image data in the horizontal direction of the pixels arranged in a matrix, and via the second line latch. The display memory according to claim 8, wherein the first read port outputs the data for one line from the display memory to the display. 11. The display has a plurality of pixels arranged in a matrix, and the display memory has a plurality of memory cells arranged in a matrix corresponding to a matrix arrangement of the plurality of pixels. Pixel data for driving the pixels of the corresponding matrix of the display is stored in each memory cell by the write port, and the first read port latches the image data in the second line latch on a line-by-line basis. 9. The display memory according to claim 8, wherein the display memory supplies the pixels to corresponding lines of the display. 12. A driver circuit for driving pixels arranged in a matrix of a display by a signal corresponding to image data stored in a display memory, wherein the display memory comprises at least one pair of bit lines and a complementary circuit. A memory cell of at least one column having a first memory node and a second memory node capable of holding the first level and second level states, and output to one bit line of the bit line pair. Said first
A first read circuit for reading the storage data of the storage node of the second storage node, and the second read circuit output to the other bit line of the bit line pair.
Driver circuit having a second read circuit for reading the storage data of the storage node. 13. The driver circuit according to claim 12, wherein the second read circuit inverts and outputs the level of the storage data of the second storage node output to the other bit line. 14. The memory is the first memory cell of the memory cell.
14. The driver circuit according to claim 13, further comprising a write circuit that outputs the data of the first level and the data of the second level to each of the bit line pairs and writes the data in the display memory to the first and second storage nodes. 15. The display memory includes control means for controlling an operation of the display memory, a write port including at least one write circuit, and a first read port including at least one first read circuit. And a second read port including at least one of the second read circuits, wherein the first read port supplies data stored in the display memory to the display, The read port reads data from the display memory and outputs it to the control means, and the write port writes data from the control means.
15. The driver circuit according to claim 14, wherein writing is performed in the display memory. 16. The first read port is connected to the first read port during a first level period of a clock signal of the display memory.
Performing a first access to output the data read out through the readout circuit to the display, and during a second level period of the clock signal of the display memory,
The second read port outputs the data read via the second read circuit to the control means,
16. The driver circuit according to claim 15, wherein the write port performs a second access for inputting write data to be written in the display memory from the control means. 17. The display memory has a bit selection means for receiving a write control signal and selecting a memory cell to be written, and the write circuit has the first of the memory cells selected by the bit selection means. 15. The driver circuit according to claim 14, wherein the data of the first level and the data of the second level are output to each of the bit line pairs of the memory cell to be written to the second storage node. 18. The display memory includes a drive power supply voltage source for the display memory, and a switching element for selectively connecting a power supply voltage supply terminal of at least one memory cell and the drive power supply voltage source. The driver circuit according to claim 14. 19. The first access signal terminal is arranged on one side of the display memory, and the second access signal terminal is arranged on another side different from the one side. An access first interface and a second access second interface sandwiching the display memory, the first access signal terminal of the display memory and the second access, respectively. The driver circuit according to claim 16, which is connected to the signal terminal for use. 20. The first interface has a first line latch for storing one line of image data in the horizontal direction of the pixels arranged in a matrix, and via the first line latch. The write port outputs the data for one line to a selected bit line, and the second read port outputs the data for one line from the display memory to the control means. 19. The driver circuit described in 19. 21. The first line latch is provided with the first
Write control data designating pixel data to be written to the display memory is stored for each pixel in the pixel data latched by the line latch, and the write port has the first port designated by the write control data. 20. The driver circuit according to claim 19, wherein the pixel data latched by the line latch is written in the display memory. 22. The display has a plurality of pixels arranged in a matrix, and the display memory has a plurality of memory cells arranged in a matrix corresponding to a matrix arrangement of the plurality of pixels. Pixel data for driving the pixels of the corresponding matrix of the display is stored in each memory cell by the write port, and the first read port latches the image data in the second line latch on a line-by-line basis. 20. The driver circuit according to claim 19, wherein the driver circuit supplies the pixels of a corresponding line of the display. 23. Pixel data in one line of pixel data of the display latched by the first line latch is converted to corresponding pixels in one line of pixels of the display by the write port. The driver circuit according to claim 22, which is stored in the display memory as pixel data to be driven. 24. The second interface has a second line latch for storing one line of image data in the horizontal direction of the pixels arranged in the matrix, and via the second line latch. The first read port outputs the data for one line from the display memory to the display. The driver circuit according to claim 19. 25. The driver circuit according to claim 24, wherein the bit width of the second line latch is the same as the bit width of image data for one line in the horizontal direction of the pixels arranged in the matrix. 26. The second interface sequentially selects R, G, B data included in the image data held in the second line latch and converts the image data into a time division signal. Circuit and digital that converts digital signals into analog signals
The selection circuit further comprises an analog conversion means, and the selection circuit outputs a time division signal obtained by time division of R, G, B data included in the image data, to the digital-analog conversion means, and the digital-analog conversion means. 25. The driver circuit according to claim 24, wherein the time-division signal is converted into an analog signal and supplied to the display. 27. The selection circuit selects R, G, B data included in the pixel data held in the second line latch asynchronously with a clock signal of the display memory,
The driver circuit according to claim 26, wherein the driver circuit converts into a time division signal. 28. A display screen in which pixels are arranged in a matrix, a scanning circuit for scanning the pixel matrix row by row and applying a voltage to a selected row, and a signal corresponding to image data is output to the pixels. A driver circuit; and a display memory for storing the image data, wherein the display memory has at least one pair of bit lines and a first first and second levels capable of holding complementary first level and second level states. At least one column of memory cells having a storage node and a second storage node, and the first output to one bit line of the bit line pair
A first read circuit for reading the storage data of the storage node of the second storage node, and the second read circuit output to the other bit line of the bit line pair.
A second readout circuit for reading out the storage data of the storage node of. 29. The display according to claim 28, wherein the second read circuit inverts and outputs the level of the storage data of the second storage node output to the other bit line. 30. The memory is the first of the memory cells.
30. The display according to claim 29, further comprising a write circuit that outputs the data of the first level and the data of the second level to the first and second storage nodes, and writes the data in the display memory. 31. The display memory includes: a control means for controlling an operation of the display memory; a write port including at least one of the write circuits; and at least one of the first read circuits. A first read port, and a second read port including at least one of the second read circuits, the first read port supplying data stored in the display memory to the display. The second read port reads data from the display memory and outputs the data to the control means, and the write port writes data from the control means,
The display according to claim 29, wherein writing is performed in the display memory. 32. During the first level period of the clock signal of the display memory, the first read port is set to the first level.
Performing a first access to output the data read out through the readout circuit to the display, and during a second level period of the clock signal of the display memory,
The second read port outputs the data read via the second read circuit to the control means,
The display according to claim 31, wherein the write port performs a second access for inputting write data to be written in the display memory from the control means. 33. The display memory has a bit selection means for receiving a write control signal and selecting a memory cell to be written, and the write circuit has the first of the memory cells selected by the bit selection means. 31. The display according to claim 30, wherein the first level data and the second level data are output to each of the bit line pairs of the memory cell to be written to a second storage node. 34. The display memory includes a drive power supply voltage source for the display memory, and a switching element for selectively connecting a power supply voltage supply terminal of at least one memory cell and the drive power supply voltage source. The display according to claim 30. 35. The first access signal terminal is arranged on one side of the display memory, and the second access signal terminal is arranged on another side different from the one side. An access first interface and a second access second interface sandwiching the display memory, the first access signal terminal of the display memory and the second access, respectively. 33. The display according to claim 32, which is connected to a signal terminal for use. 36. The first interface has a first line latch for storing one line of image data in the horizontal direction of the pixels arranged in a matrix, and via the first line latch. The write port outputs the data for one line to a selected bit line, and the second read port outputs the data for one line from the display memory to the control means. The display according to 35. 37. The first line latch stores, for each pixel, write control data designating pixel data latched by the first line latch to be written in a display memory, and the write port is 36. Pixel data designated as write control data is written in the display memory.
Display described in. 38. The display has a plurality of pixels arranged in a matrix, and the display memory has a plurality of memory cells arranged in a matrix corresponding to a matrix arrangement of the plurality of pixels. Pixel data for driving the pixels of the corresponding matrix of the display is stored in each memory cell by the write port, and the first read port latches the image data in the second line latch on a line-by-line basis. 36. A display as claimed in claim 35 in which the pixels of a corresponding line of the display are supplied. 39. Each pixel data for one line of the display latched by the first line latch corresponds to the corresponding one of the display by the write port.
As pixel data for driving each pixel in the line,
39. The display of claim 38 stored in the display memory. 40. The second interface has a second line latch for storing one line of image data in the horizontal direction of the pixels arranged in a matrix, and via the second line latch. The display according to claim 35, wherein the first read port supplies the one line of data from the display memory to the display. 41. The display according to claim 40, wherein the bit width of the second line latch is the same as the bit width of image data for one line in the horizontal direction of the pixels arranged in the matrix. 42. The second interface includes R including the image data held in the second line latch,
A selection circuit for sequentially selecting G and B data and converting the image data into a time division signal, and a digital circuit for converting a digital signal into an analog signal.
Further comprising an analog conversion means, the selection circuit outputs to the digital-analog conversion means a time division signal obtained by time division of R, G, B data included in the image data, the digital-analog conversion means The display according to claim 41, wherein the time division signal is converted into an analog signal and supplied to the display. 43. The selection circuit selects R, G, B data included in the pixel data held in the second line latch asynchronously with a clock signal of the display memory,
The display according to claim 42, wherein the display is converted into a time division signal.