JP2008112537A - Semiconductor memory circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory circuit device constituted as a dual port RAM, which surely operates, with reduced chip area, and suppressed delay in reading data. <P>SOLUTION: Each of memory cells is provided with: a storing and holding circuit part 10 storing and holding a data signal; a word switch 20 controlling the storing and holding circuit part 10 to store and hold a data signal input to a BIT1 line 41 or output the data signal stored and held in the storing and holding circuit 10 through the BIT1 line 41; and a word switch 30 controlling the storing and holding circuit part 10 to store and hold a data signal input to a second bit line or output the data signal stored and held in the storing and holding circuit 10 through the second bit line. Then respective word switches 20, 30 are constituted by combining Nch type transistors 21, 31 and Pch type transistors 22, 32, respectively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory circuit device, and more particularly to a dual port RAM.

  Conventionally, a dual port RAM as a storage medium for storing data has been proposed in Patent Document 1, for example. Specifically, in Patent Document 1, a memory holding circuit that holds data, an NMOS transistor connected between the first input / output node of the memory holding circuit and the bit line BIT1, and a first input / output of the memory holding circuit. A PMOS transistor connected between the node and the bit line BIT2, an NMOS transistor connected between the second input / output node of the memory holding circuit and the bit line / BIT1, and a second input / output node of the memory holding circuit And a dual-port RAM including a memory cell circuit having a PMOS transistor connected between the bit line / BIT2 and the bit line / BIT2.

Each of these transistors serves as a switch for inputting / outputting data to / from the memory holding circuit. In such a memory cell circuit of a dual port RAM, data held in the memory holding circuit is turned on by turning on each transistor by inputting a signal to a word line for turning on / off each transistor. A potential difference based on the data stored in the memory holding circuit is generated between BIT1 and bit line / BIT1, and the potential difference is amplified and read. The data read in this way is input to a logic circuit or the like via a port.
JP-A-5-299261

  However, in the above conventional technique, there is a possibility that the precharge circuit for fixing the state of the bit line is not connected when the bit line is not used, and it does not operate as a RAM. That is, when an NMOS transistor is connected between the memory holding circuit and the bit line, a PMOS transistor must be connected to the bit line as a precharge circuit. Similarly, when a PMOS transistor is connected between the memory holding circuit and the bit line, an NMOS transistor must be connected as a precharge circuit.

  Therefore, it is conceivable to add a precharge circuit. However, since a circuit area for this purpose is required, the circuit area of the precharge circuit is required. For example, when a gate array is used, a gate cell for that purpose is used, so that the RAM chip area increases as the area of the precharge circuit corresponding to each memory cell increases.

  Further, when a PMOS transistor is connected between the memory holding circuit and the bit line, the PMOS transistor has a response speed slower than that of the NMOS transistor.

  In view of the above, the present invention has as its first object to provide a semiconductor memory circuit device that operates reliably when providing a semiconductor memory circuit device configured as a dual-port RAM, and a semiconductor capable of reducing the chip area. A second object is to provide a memory circuit device, and a third object is to reduce a delay in reading data.

  In order to achieve the above object, according to a first feature of the present invention, in a semiconductor memory circuit device constituting a dual port RAM, first, the second bit line (42) is inputted to the first bit line (41). So that the inverted data signal is input, and the data signal input to the second bit line is output to the port via the output inverting circuit section (90) for inverting the data signal. To do.

  Each of the plurality of memory cells constituting the dual port RAM receives a data signal from the outside, and stores a memory holding circuit unit (10) for storing and holding the data signal, a memory holding circuit unit, a first bit line, and the like. And the data signal input to the first bit line is stored and held in the memory holding circuit unit based on the permission signal input via the first word line (51) or via the first bit line. The first word switch (20) for outputting the data signal stored and held in the memory holding circuit unit to the outside is connected to the memory holding circuit unit and the second bit line via the second word line (52). Based on the input enable signal, the data signal input to the second bit line is stored in the memory holding circuit unit, or the data signal stored in the memory holding circuit unit is removed via the second bit line. A second word switch (30) to be output to, a configuration having a.

  Each word switch is configured by combining an Nch type transistor (21, 31) and a Pch type transistor (22, 32).

  Thereby, when inputting / outputting the data signal stored and held in the memory holding circuit unit via each bit line, each word switch as the word SW is configured by a combination of an Nch type and a Pch type. Thus, a precharge circuit for fixing each state of each bit line can be eliminated.

  As described above, even if the circuit configuration without the precharge circuit is used, each word switch is driven by the permission signal, so that the data signal can be input / output in each memory cell reliably. It is possible to realize a dual port RAM that can reliably read the held data.

  Furthermore, when data is output to each bit line, the word switch is configured to combine an Nch type MOS transistor and a Pch type MOS transistor. As a result, it is possible to reduce the delay in reading data as compared with the case where the word SW is composed of only Pch type MOS transistors.

  In addition, since the precharge circuit can be eliminated in configuring the memory cell, the chip area of the semiconductor chip forming the semiconductor memory circuit device can be reduced.

  When the memory cell is configured as described above, when each memory cell stores data in the memory holding circuit unit, the data input of the data to be stored in the memory holding circuit unit is input to the first bit line. The circuit section (71, 72) is connected to the first bit line and the second bit line, and is turned on when the data input circuit section inputs a data signal to the first bit line. In addition, a writing inversion circuit portion (73) for inputting an inverted signal of the data signal input to the first bit line to the second bit line may be provided.

  Thereby, a data signal can be input to each bit line, and the data signal can be stored and held in the memory holding circuit unit.

  Furthermore, a simultaneous reading circuit unit that outputs a signal for simultaneous reading when each memory cell simultaneously reads out a data signal stored and held in the memory holding circuit unit through the first bit line and the second bit line. (81) is connected to the first bit line and the second bit line, and is turned on when a simultaneous reading signal is input from the simultaneous reading circuit unit, whereby the data signal input to the first bit line And a state holding inverting circuit section (82) for inputting the inverted signal of the above to the second bit line.

  As a result, when data signals are simultaneously input to the bit lines, the state of each bit line can be reliably reversed.

  In addition, the code | symbol in the bracket | parenthesis of each said means shows the correspondence with the specific means as described in embodiment mentioned later.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In the present embodiment, a dual port RAM is employed as the semiconductor memory circuit device.

  FIG. 1 is a circuit diagram of one memory cell constituting a semiconductor memory circuit device according to an embodiment of the present invention. As shown in this figure, the semiconductor memory circuit device includes a memory holding circuit unit 10 and two word switches 20 and 30 (first and second of the present invention) arranged so as to sandwich the memory holding circuit unit 10. Equivalent to a word switch).

  The memory holding circuit unit 10 has a function of storing and holding data signals of data, and includes two inverters 11 and 12. These inverters 11 and 12 invert input digital signals and output them, and are configured by connecting NMOS transistors 11a and 12a and PMOS transistors 11b and 12b in series, respectively. Each inverter 11 and 12 constitutes a loop circuit, and data is held in the loop circuit.

  The word switches 20 and 30 serve as switches for inputting / outputting data signals (data writing or reading) to the memory holding circuit unit 10 and are so-called word switches. Each of these word switches 20 and 30 includes NMOS transistors 21 and 31 and PMOS transistors 22 and 32, respectively.

  The word switch 20 is connected between the BIT1 line 41 (corresponding to the first bit line of the present invention) and the memory holding circuit unit 10, and the word switch 30 is connected to the memory holding circuit unit 10 and the BIT2-line 42 (the present invention). Corresponding to the second bit line). The BIT1 line 41 and the BIT2-line 42 are wirings for writing data or reading data, respectively.

  Note that the “−” symbol indicated by the BIT2-line 42 means inverted data of a signal transmitted through the BIT2-line. In the following, “-” is used as a symbol indicating inverted data. In the present embodiment, each of the BIT1 line 41 and the BIT2-line 42 corresponds to one port. Accordingly, one of the two bit lines is inverted data, and in the present embodiment, the BIT2-line 42 is a wiring that handles the inverted data.

  The WL1 line 51 (corresponding to the first word line of the present invention) is connected to the gate of the NMOS transistor 21 of the word switch 20, and the WL1 line 51 is connected to the gate of the PMOS transistor 22 via the inverter 61. That is, the word switch 20 connects or disconnects the BIT1 line 41 and the memory holding circuit unit 10 in accordance with a signal input to the WL1 line 51.

  Further, the WL2 line 52 (corresponding to the second word line of the present invention) is connected to the gate of the NMOS transistor 31 of the word switch 30, and the WL2 line 52 is connected to the gate of the PMOS transistor 32 via the inverter 62. Thereby, the word switch 30 connects or disconnects the BIT2-line 42 and the memory holding circuit unit 10 in accordance with a signal input to the WL2 line 52.

  The WL1 line 51 and the WL2 line 52 are wirings for operating the word switches 20 and 30 when data is written to the memory holding circuit unit 10, and a permission signal for turning on / off the word switch 20 for the WL1 line 51. The WL1 signal is input, and the WL2 signal is input to the WL2 line 52 as an enabling signal for turning on / off the word switch 30.

  A NAND circuit 71 for writing data to the memory holding circuit unit 10 is connected to the BIT 1 line 41 via an inverter 72. A data signal (WDATA signal) to be written and a WE signal indicating permission of writing are input to the NAND circuit 71. When both are input to the NAND circuit 71, a Lo signal is output. Data is input to the BIT 1 line 41 via the inverter 72. The NAND circuit 71 and the inverter 72 correspond to a data input circuit unit.

  Further, an inverter 73 (corresponding to the inverting circuit portion for writing of the present invention) is connected between the BIT1 line 41 and the BIT2-line. The inverter 73 ensures that the states of the BIT1 line 41 and the BIT2-line 42 are set when data is written to the memory holding circuit unit 10 so as not to destroy the data when reading data from the memory holding circuit unit 10. It is provided for fixing. The inverters 72 and 73 are turned on when a WE signal is input to the NAND circuit 71.

  The AND circuit 81 (corresponding to the simultaneous reading circuit portion of the present invention) is used when simultaneously reading the data held in the memory holding circuit portion 10. The AND circuit 81 is supplied with a signal (WL1 & WL2 signal) indicating simultaneous reading of data and an RE signal that permits reading. When both these signals are input to the AND circuit 81, the AND circuit 81 A Hi signal (simultaneous reading signal) is output from the circuit 81.

  Further, an inverter 82 (corresponding to the state holding inverting circuit portion of the present invention) is connected between the BIT1 line 41 and the BIT2-line 42. The inverter 82 is turned on when a Hi signal is input from the AND circuit 81, and serves to fix the state of each signal of the BIT1 line 41 and the BIT2-line 42 when reading data simultaneously. To fulfill.

  When simultaneously reading data held in the memory holding circuit unit 10, the word switches 20 and 30 are turned on. In this case, data retention is weakened in the loop circuit of the memory retention circuit unit 10 (potential cannot be retained). In order to prevent this, each state is maintained by the inverter 82 so that the state of the BIT1 line 41 and the state of the BIT2-line 42 are always inverted.

  The BIT2-line 42 is connected to an inverter 90 (corresponding to the output inverting circuit portion of the present invention) for returning the signal state to non-inverted. This inverter 90 is connected to the downstream side of the inverter 73 connected to the BIT 2-line 42.

  The above is the circuit configuration of one memory cell. That is, a large number of memory cells shown in FIG. 1 are provided between the BIT1 line 41 and the BIT2-line 42, and signals are input to the WL1 line 51, the WL2 line 52, the NAND circuit 71, and the AND circuit 81, respectively. Data is stored in the dual port RAM. Such a dual port RAM is formed on a semiconductor chip by a known semiconductor process.

  Next, an operation for writing data in the memory cell or reading data from the memory cell will be described. Hereinafter, writing and reading of data with respect to one memory cell will be described.

  First, when data is written to a memory cell, a WDATA signal indicating data to be written is input to the NAND circuit 71. Then, by inputting the WE signal indicating Hi to the NAND circuit 71, the inverters 72 and 73 are turned on. Thus, the WDATA signal is input to the BIT1 line 41 and the BIT2-line 42 via the inverter 72, respectively. The inverted data of the WDATA signal is written into the BIT2-line 42.

  Further, by inputting a signal for turning on the word switches 20 and 30 (each word SW) to the WL1 line 51 and the WL2 line 52, the BIT1 line 41 and the BIT2-line 42 and the memory holding circuit unit 10 are made conductive. Thus, the WDATA signal input to the BIT1 line 41 and the BIT2-line 42 is input to the memory holding circuit unit 10. Thereafter, each word switch 20, 30 is turned off to store data in the memory holding circuit unit 10.

  After the data is stored in the memory holding circuit unit 10 in this way, the WE signal indicating Lo is input to the NAND circuit 71 so as not to compete with the case where the BIT1 line 41 and the BIT2-line 42 are used for reading data. To do. Data is written into the memory cell as described above.

  In this embodiment, each of the word switches 20 and 30 is configured by combining an Nch type and a Pch type, thereby eliminating the difficulty of passing charges due to only the Pch type and writing data. Can be reduced. Further, by combining the Nch type and the Pch type, a precharge circuit for the word SW can be made unnecessary. As a result, the area for the precharge circuit in the semiconductor chip having the dual port RAM can be reduced, and the chip area can be reduced.

  On the other hand, when data is read from the memory cell and it is desired to output data from the port corresponding to the BIT1 line 41, the WL1 signal for turning on the word switch 20 is input to the WL1 line 51, and the memory holding circuit unit 10 The BIT1 line 41 is made conductive. As a result, the data held in the memory holding circuit unit 10 is read out via the BIT1 line 41.

  Similarly, when data is read from the memory cell, if it is desired to output data from the port corresponding to the BIT 2-line 42, a WL 2 signal for turning on the word switch 30 is input to the WL 2 line 52, and the memory holding circuit unit 10 is input. The held data is read out via the BIT2-line 42. As described above, when the port of the BIT 2 -line 42 is selected, the data stored in the memory holding circuit unit 10 is inverted and output, so that the inverter 90 provided in the subsequent stage of the BIT 2 -line 42 is used. Will be output.

  As shown in FIG. 1, in this embodiment, since the bit lines can be composed of two bits, ie, BIT1 line 41 and BIT2-line 42, a large number of wirings are not required as in the prior art, and the semiconductor memory is reduced in number of wirings. A circuit device can be configured.

  When data is to be output simultaneously from the ports corresponding to the BIT1 line 41 and the BIT2-line 42, the WL1 signal and the WL2 signal are input to the WL1 line 51 and the WL2 line 52, respectively. Turn on. As a result, the data stored in the memory holding circuit unit 10 is output to the BIT1 line 41 and the BIT2-line 42, respectively.

  Further, a signal (WL1 & WL2 signal) indicating simultaneous data reading and an RE signal indicating Hi are input to the AND circuit 81, Hi is output from the AND circuit 81, and the inverter 82 is turned on. This ensures that the states of the BIT1 line 41 and the BIT2-line 42 are reversed. In this way, the data stored in the memory holding circuit unit 10 is read out via the BIT1 line 41 and the BIT2-line 42, respectively.

  The above is the operation of writing and reading data in one memory cell. An actual dual port RAM is composed of a large number of memory cells, and data is written to and read from each memory cell as described above.

  A dual port RAM including the memory cells as described above can be provided in the CPU. FIG. 2 is a block diagram of the CPU. As shown in this figure, the dual port RAM 110 composed of the plurality of memory cells shown in FIG. 1 can be applied to the register file 100 constituting the CPU.

  That is, data can be written to the dual port RAM 110 of the register file 100 with one port via the data bus, and data can be read from the dual port RAM 110 with two ports and input to the ALU 200 that performs four arithmetic operations and logical operations. be able to.

  Thus, by applying the memory cell to the register file 100 of the CPU, the precharge circuit becomes unnecessary as described above, so that the total number of gates of the CPU can be greatly reduced. As described above, the memory cell can be used as data storage means of the register file 100 of the CPU.

  As described above, in this embodiment, the word switches 20 and 30 serving as the word SW for writing data to the memory holding circuit unit 10 or reading data from the memory holding circuit unit 10 are connected to the Nch type MOS transistors 21 and 31. It is characterized by comprising Pch type MOS transistors 22 and 32.

  Thus, by combining the Nch type and the Pch type, it is possible to eliminate the need for a precharge circuit for fixing the states of the BIT1 line 41 and the BIT2-line 42. Therefore, even if a precharge circuit is not required, a dual port RAM that functions as a memory cell and operates reliably can be realized.

  Further, since the precharge circuit can be eliminated, the chip area of the semiconductor chip in which the dual port RAM is formed can be reduced. At this time, when the dual-port RAM is configured by the gate array, a circuit layout that effectively uses the gate array can be configured, and the chip area can be further reduced.

  Further, when data is output to the BIT1 line 41 and the BIT2-line 42, the Nch transistors 21 and 31 as shown in FIG. 1 are used without the configuration of outputting data only through the Pch MOS transistors. And Pch type transistors 22 and 32 are combined to form a word SW. As a result, it is possible to reduce delays in data writing and reading when the word SW is composed only of the Pch type.

(Other embodiments)
When the data stored in the memory holding circuit unit 10 is read simultaneously at the BIT1 line 41 and the BIT2-line 42, only the word switch 20 may be turned on without turning on the word switch 30. In this case, signals (WL1 & WL2 signals) indicating simultaneous data reading are input to the WL1 line 51 and the AND circuit 81, respectively. As a result, the AND circuit 81 is turned on and the inverter 82 functions to invert the data on the BIT1 line 41 and input it to the BIT2-line 42.

  The dual port RAM 110 is not limited to the CPU, and may be used as other storage means. For example, a circuit using a large number of flip-flops can be replaced with a circuit including the memory cells. In a circuit using flip-flops, a selection circuit for selecting each flip-flop is required, and a corresponding chip area is also required. However, the selection circuit is not necessary in a circuit constituted by the memory cells. Also, the memory cell can be employed in, for example, a CAN controller.

  In the case of using a memory cell as a storage means in another circuit configuration, when a circuit layout is configured using a gate array, it is effective from the viewpoint of chip area.

1 is a circuit diagram of one memory cell constituting a semiconductor memory circuit device according to an embodiment of the present invention. FIG. 2 is a block diagram of a CPU to which a dual port RAM configured with the memory cells shown in FIG. 1 is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Memory holding circuit part, 20, 30 ... Word switch, 21, 31 ... Nch type transistor, 22, 32 ... Pch type transistor, 41 ... BIT1 line, 42 ... BIT2- line, 51 ... WL1 line, 52 ... WL2 line, 71 ... NAND circuit, 81 ... AND circuit, 72, 73, 82, 90 ... inverter.

Claims (3)

Data writing to the plurality of memory cells via a first bit line (41) and a second bit line (42) each having a plurality of memory cells and connected to two ports, or the plurality of memory cells A semiconductor memory circuit device constituting a dual port RAM in which data is read from
A data signal obtained by inverting the data signal input to the first bit line is input to the second bit line, and the data signal input to the second bit line is used for output to invert the data signal. It is designed to be output to the port via the inverting circuit section (90),
Each of the memory cells
A memory holding circuit section (10) for receiving a data signal from outside and storing the data signal;
The memory holding circuit unit and the first bit line are connected, and a data signal input to the first bit line based on a permission signal input via a first word line (51) is stored in the memory holding circuit. A first word switch (20) that outputs the data signal stored in the memory holding circuit unit to the outside via the first bit line,
The memory holding circuit unit and the second bit line are connected, and a data signal input to the second bit line is input to the memory holding circuit based on a permission signal input via a second word line (52). A second word switch (30) that outputs the data signal stored in and held in the storage holding circuit unit via the second bit line.
Each of the word switches is configured by combining an Nch type transistor (21, 31) and a Pch type transistor (22, 32), respectively. Each of the memory cells
A data input circuit unit (71, 72) for inputting a data signal of data to be stored and held in the storage holding circuit unit to the first bit line when storing and holding data in the storage holding circuit unit;
The first bit line is connected to the second bit line and is turned on when the data input circuit unit inputs the data signal to the first bit line. 2. The semiconductor memory circuit device according to claim 1, further comprising: a write inversion circuit unit (73) for inputting an inverted signal of a data signal input to the line to the second bit line. Each of the memory cells
A simultaneous readout circuit section (81) for outputting a simultaneous readout signal when simultaneously reading out the data signals stored and held in the storage holding circuit section to the outside via the first bit line and the second bit line respectively; ,
A data signal input to the first bit line by connecting the first bit line and the second bit line and turning on when the simultaneous read signal is input from the simultaneous read circuit unit. The semiconductor memory circuit device according to claim 1, further comprising: a state holding inversion circuit unit (82) for inputting an inversion signal of the signal to the second bit line.

Images