JP2003099395A - Bus arbiter device and bus-arbiting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a device and a method for arbiter in which fair arbitration can be carried out for all bus masters connected to the bus, in a simple circuit configuration and arbitration latency is reduced. SOLUTION: A bus usage right imparting device 108, sequentially imparting bus use rights to a plurality of bus masters 104 based on a sequence set beforehand and a bus state monitor 106 monitoring the state of use of the bus 102, are provided in the bus arbiter device 100. In this case, the bus usage right imparting device permits the transition of bus usage right to the next bus master, when a determining is made that the bus is in an idle state by the bus state monitor, and when the bus is judge to be in a used state by the bus monitor, the transision of the bus use right to the next bus maser is inhibited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbiter device and a bus arbiter method, and more particularly to a bus arbiter device and a bus arbiter method for arbitrating bus usage rights in a system in which a plurality of devices are connected to one bus.

[0002]

2. Description of the Related Art Generally, a bus is shared by a plurality of modules that require the bus. When the module wants to use the bus, it requests the bus arbiter device to use the bus. The bus arbiter device arbitrates which module is given the bus use right and assigns the bus use right to each module.
A module that is connected to a bus and operates using the bus is called a bus master.

A bus master who wants to use the bus notifies the bus use request signal to the bus arbiter device via an individual line. The bus arbiter device that has received the bus use request signal determines whether there is a bus use request from another bus master, and when there is a request, determines which of a plurality of use requests should be given the bus use right. The bus use right is given to the bus master requesting the bus use by the bus use permission signal via the line.

A bus arbiter device provided with a mechanism for arbitrating so that a specific bus master does not occupy the bus and a method thereof have been proposed by Japanese Patent Laid-Open No. 2000-40061.

[0005]

However, when the bus use right is transferred by the bus use request signal or the bus use permission signal, the bus use request signal is issued from each bus master to the bus arbiter device. A time lag (arbitration latency) occurs until the bus master is granted a bus master signal by the bus master signal.

Further, when the bus right is given to a certain bus master and then the next bus right is given to another bus master, an arbitration latency occurs to transfer the bus use right from one bus master to the next bus master.

As another problem, when a specific bus master continuously outputs a bus right request, it may be difficult for another bus master to acquire the bus right.

When a bus use request signal is issued from a plurality of bus masters, it takes time to determine which bus master is to be given the bus use permission signal, so that the timing of bus arbitration within a limited time becomes strict. In addition, the circuit inside the bus arbiter becomes complicated.

The present invention has been made in view of the above problems of the conventional bus arbiter device and method, and an object of the present invention is to provide all bus masters connected on the bus with a simple circuit configuration. To provide a new and improved bus arbiter device and method capable of performing fair arbitration.

Further, another object of the present invention is to provide a new and improved bus arbiter device and method capable of reducing the arbitration latency with a simple circuit configuration.

Further, the bus arbiter device and the method thereof according to the present invention can reduce the number of signal lines connected to the conventional bus arbiter device, and the present arbiter method can be applied to a device using the conventional arbiter method. Becomes

[0012]

In order to solve the above problems, according to one aspect of the present invention, in a bus arbiter device that arbitrates the bus right of a plurality of bus masters connected to one bus, the bus masters of the plurality of bus masters An arbiter device provided with a bus right granting device for sequentially granting rights according to a preset order.

With such a configuration, the bus arbiter device automatically gives the bus right to each bus master without waiting for the use request from each bus master, and each bus master connected to the bus has its use frequency and use priority order. Regardless of the right to use the bus, fair arbitration can be achieved.

Further, the bus arbiter device is provided with a bus state monitoring device for monitoring the bus use state, and the bus right granting device sends the next bus master to the next bus master when the bus state monitoring device determines that the bus is in the idle state. An arbiter device is provided which is characterized by permitting the transfer of the bus right and prohibiting the transfer of the bus right to the next bus master when the bus status monitor determines that the bus is in use.

With this configuration, it is possible to reduce the arbitration latency required for permitting the bus use of each bus master to the bus arbiter device and permitting each bus master of the bus arbiter device to use the bus arbiter device individually. By eliminating the lines, the circuit configuration of the bus arbiter device can be simplified.

Another aspect of the present invention is characterized in that the bus right granting device grants the bus right to each bus master and the bus status monitoring device monitors the bus usage status at different timings. An arbiter device is provided.

With this configuration, it is possible to reduce the arbitration latency between the bus use permission signals in each bus master.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to the accompanying drawings,
A preferred embodiment of the present invention will be described in detail. In the present specification and the drawings, components having substantially the same functional configuration are designated by the same reference numerals, and duplicate description will be omitted.

FIG. 1 shows an overall connection diagram in the case of connecting a plurality of bus masters 104 to a bus arbiter device 100 of this embodiment of the present invention. First, a plurality of bus masters 104 are connected to one bus 102. In this embodiment, the bus master A 104a and the bus master B10
4b, bus master C104c, a total of three bus masters 10
4 are connected, but may be connected to any number of bus masters 104.

In this embodiment of the present invention, the bus arbiter device 10 for arbitrating the bus right of the plurality of bus masters 104.
Within 0, a bus status monitoring device 106 for monitoring the usage status of the bus 102 is provided.

The bus status monitoring device 106 includes the bus 102
Bus idle monitor signal is input from. here,
The bus idle monitor signal means a signal indicating whether or not the bus 102 is in an idle state, and may be a bus idle signal that directly informs that the bus 102 is in an idle state. It is also possible to use a logic within the monitoring device 106 to determine that the bus 102 is in the idle state.

The bus right granting device 108 gives permission to use the bus right to each bus master 104 by the bus use permission signals GNT-A to GNT-C based on the determination of the bus use condition of the bus state monitoring device 106.

In the present embodiment, since the number of bus masters 104 connected is three, that is, A to C, the number of bus use permission signals GNT-A to GNT-C is also three. It goes without saying that the number of bus use permission signals increases or decreases depending on the number of.

The operation of this embodiment will be described below with reference to the state transition diagram of the bus arbiter device 100 of this embodiment shown in FIG.

In the state transition diagram of the bus arbiter device 100 shown in FIG. 2, the state in which the bus right granting device 108 grants the bus right to the bus master A 104a is determined in step S202.
a, monitor the bus usage status of the bus master A 104a,
The state in which the bus granting device 108 waits for the bus 102 to be released until the bus idle monitoring signal is notified to the bus state monitoring device 106 is referred to as step S204a.

Similarly, the state of giving the bus right to the bus master B 104b by the bus right granting device 108 is step S2.
02b, the bus use status of the bus master B 104b is monitored, and a state in which the bus right granting device 108 waits until the bus 102 is released until the bus idle monitoring signal is notified to the bus status monitoring device 106 is set as step S204b. .

Further, the state in which the bus right is given to the bus master C104c by the bus right granting device 108 is step S2.
02c, the bus use state of the bus master C104c is monitored, and the state in which the bus right granting device 108 waits until the bus 102 is released until the bus idle monitoring signal is notified to the bus state monitoring device 106 is set as step S204c. .

First, in step S202a, the bus right is given from the bus right granting device 108 to the bus master A 104a by the bus use permission signal GNT-A.

When the bus master A 104a is connected to the bus 102, the bus master A 104a can use the bus 102 by obtaining the bus right. At this time, step S2
At 04a, the bus right granting device 108 waits for the bus 102 to be released until the bus idle monitoring signal is notified to the bus status monitoring device 106.

Next, after the bus 102 is released, the bus right grant device 108 gives the bus right to the bus master B 104b by the bus use permission signal GNT-B in step S202b.

When the bus master B 104b is connected to the bus 102, as in the case of the previous bus master A 104a,
The bus master B 104b acquires the bus right, and thus the bus 1
02 can be used. At this time, in step S204b, the bus right granting device 108 waits for the bus 102 to be released until the bus idle monitoring signal is notified to the bus state monitoring device 106.

Next, after the bus 102 is released, the bus right grant device 108 gives the bus right to the bus master C104c by the bus use permission signal GNT-C in step S202c.

When the bus master C104c is connected to the bus 102, the preceding bus master A104a and bus master B1
As in the case of 04b, the bus master C104c obtains the bus right and can use the bus 102. At this time, step S2
In 04c, the bus right granting device 108 waits for the bus 102 to be released until the bus idle monitoring signal is notified to the bus status monitoring device 106.

In the same manner, the bus arbiter device 100 will be described below.
Within, the cycle of steps S202a to S204c is sequentially repeated.

Referring now to FIG. 2, the bus right granting device 10
The bus use permission signal issued from 8 to each bus master 104 is not simultaneously given to a plurality of bus masters 104. That is, when the bus use permission signal GNT-A for the bus master A 104a is valid, the bus master B 104a
The bus use permission signals GNT-B and GNT-C for 104b and the bus master C104c are disabled.

On the other hand, until the bus idle monitoring signal is sent to the bus status monitoring device 106, the bus right granting device 108
Waits for bus 102 to be released in step S204
In the states of a, S204b, and S204c, the bus use permission signal for all the bus masters 104 is in the invalid state.

However, one step before, that is, step 20 which is the state one step before the step S204a is performed.
In 2a, the bus right is given to the bus master A 104a, and the bus master A 104a to which the bus right is given can activate the bus 102 until this step S204a, and becomes the bus right acquisition state.

Similarly, in step S202b, which is one state before step S204b, the bus right is given to the bus master B104b, and the bus master B104b given the bus right activates the bus 102 until step S204b. It is possible to obtain the bus right.

In step S202c, which is one state before step S204c, the bus right is assigned to the bus master C.
The bus master C104c which has been given the bus right can activate the bus 102 up to step S204c, and the bus right is acquired.

That is, each bus master 104 can use the bus 102 by connecting to the bus 102 when the bus right is obtained by the bus use permission signal, and the other bus masters 104 cannot use the bus 102. unacceptable.

If the bus master 10 is given the bus right
4 does not connect to the bus, the bus state monitoring device 106
Detects that the bus master 104 given the bus right by the bus idle monitoring signal does not use the bus 102, and notifies the bus right granting device 108 of the result.

The bus right granting device 108, which has been notified from the bus state monitoring device 106 of the bus non-use detection result, permits the next bus master 104 to use the bus right.

If the bus 102 has been used, the next bus master 1 is used until the bus 102 becomes idle.
Do not transfer the bus right to 04.

That is, even if there is no bus use request, the bus granting device 108 sequentially gives the bus right to each bus master 104, and if the bus 102 is not used, the next bus master 1
The bus right moves to 04.

Bus master 104 wishing to use bus 102
Uses the bus 102 as soon as the bus right is obtained.
Then, the bus right granting device 108 transfers the bus right to the next bus master 104 when the bus 102 becomes idle.

FIG. 3 and FIG. 4 show the state of transfer of the bus right,
The timing chart shows the state of the bus arbiter device 100 at that time.

FIG. 3 shows each bus master 104 to the bus 10
2 shows the state of the bus arbiter device 100 when there is no usage request of No. 2 and the states of the bus request signals GNT-A to C at that time. The timing of each cycle of a clock signal (referred to as CLK in the figure) for synchronizing the operation of the bus arbiter device 100 according to the present embodiment is sequentially timing T1, timing T2, ..., Timing Tn (n: Natural number).

When the clock signal is at timing T1,
The bus arbiter device 100 gives the bus right from the bus right granting device 108 to the bus master A 104a in step S202.
Since the state is a, the bus use permission signal GNT-A is input to the bus master A 104a, and the bus master A 104a
Is in a state where he has the bus right.

When the clock signal is at timing T2,
The bus right granting device 108 gives the bus right to the bus master A 104a.
Therefore, the bus right granting device 108 waits until the bus 102 is released until the bus idle monitoring signal is notified to the bus state monitoring device 106, and shifts to the bus monitoring state of step S204a.

In step S204a, the bus master A
Since the bus 102 was not activated because there was no request for use of the bus from 104a, the state of the bus arbiter device 100 is that the bus use permission signal GNT-B is input to the bus master B 104b when the clock signal is timing T3. The process proceeds to step S202b where the bus master B 104b has acquired the bus right.

When the clock signal is timing T4,
The bus right granting device 108 gives the bus right to the bus master B 104b.
Therefore, the bus right granting device 108 waits until the bus 102 is released until the bus idle monitoring signal is notified to the bus state monitoring device 106, and shifts to the bus monitoring state of step S204b.

In step S204b, the bus master B
Since the bus 102 was not activated because there was no request for bus use from 104b, when the clock signal is timing T5, the state of the bus arbiter device 100 is that the bus use permission signal GNT-C is input to the bus master C104c. The bus master C104c moves to step S202c where the bus mastership is obtained.

Next, when the clock signal is at timing T6, the bus right granting device 108 transfers the bus right to the bus master C10.
4c, the bus right granting device 108 continues until the bus idle monitoring signal is notified to the bus status monitoring device 106.
Waits for bus 102 to be released Step S204c
Transition to the bus monitoring state of.

Thereafter, the same operation is performed, the bus right sequentially moves, and since there is no request from the bus masters 104 to use the bus, the bus right further moves to the next bus master 104.

FIG. 4 shows the states of the bus arbiter device 100 when the bus master A 104a makes a bus use request and the bus use permission signals GNT at that time.

Similar to FIG. 3, first, at the timing T1, the state of the bus arbiter device 100 is step S202a in which the bus right is given to the bus master A 104a by the bus use permission signal GNT-A. By the way, in the present embodiment, the bus master A 104a uses the bus 102 until the clock signal is at the timing T4.

The state of the bus arbiter device 100 is such that when the clock signal is at timing T2, the bus state monitoring device 1
Until the bus idle monitoring signal is notified to 06, the bus right granting device 108 shifts to the bus monitoring state of step S204a which waits for the bus 102 to be released.

When the clock signal is timing T2,
Since the bus master A 104a is using the bus 102, the state of the bus arbiter device 100 continues to be in the bus release waiting state of the bus master A 104a in step S2 until timing T5 when the bus 102 enters the idle state.
04a.

When the clock signal is timing T5,
Since the bus 102 is in the idle state, the bus arbiter device 100 is the next bus master 104, which is the bus master B1.
The state of step S202b for activating the bus use permission signal GNT-B for 04b is set.

When the clock signal is timing T6,
The bus use permission signal GNT-B is input to the bus master B 104b, and the step S202b is in a state where the bus master B 104b has acquired the bus right.

Next, when the clock signal is at timing T7, the bus arbiter unit 100 grants the bus right to the bus master B1.
No. 04b is given to the bus right granting device 10 until the bus idle monitoring signal is notified to the bus status monitoring device 106.
8 waits for the bus 102 to be released Step S204
Transition to the bus monitoring state of b.

In step S204b, the bus master B
Since the bus 102 was not activated because there was no request for bus use from 104b, when the clock signal is timing T8, the state of the bus arbiter device 100 is that the bus use permission signal GNT-C is input to the bus master C104c, The process moves to step S202c where the C104c acquires the bus right.

Next, when the clock signal is at timing T9, the bus arbiter device 100 acquires the bus right at timing T9.
Since it is given to the bus master C 104c at 8, until the bus idle monitoring signal is notified to the bus state monitoring device 106,
The bus right granting device 108 shifts to the bus monitoring state of step S204c which waits for the bus 102 to be released.

The bus right grant device 108 permits the bus master 104 to use the bus only during the period when the clock signal is output, and the bus 102 by the bus state monitoring device 106 is in the idle state while the clock signal is zero. The latency between the bus use permission signals can be reduced by setting the period for determining whether or not to use.

FIG. 5 shows each bus master 104 shown in FIG.
If there is no request for use of the bus 102 from the bus right granting device 108, the bus use grant from the bus right granting device 108 to each bus master 104 is performed only during the period when the clock signal is output, and during the period when the clock signal is zero, the bus state monitoring device 106 2 shows the states of the bus arbiter device 100 and the states of the bus request signals GNT-A to GNT at that time when the method of setting the period for determining whether or not the bus 102 is in the idle state is applied.

As shown in FIG. 5, during the timing T1 of the clock signal, the bus arbiter device 100 sends a bus use permission signal GNT-A from the bus right grant device 108 to the bus master A 104a during the period in which the clock signal is output. After step S202a in which the bus right is given, the bus right granting device 108 releases the bus 102 until the bus idle monitoring signal is notified to the bus state monitoring device 106 during the period when the clock signal is also the output zero at the timing T1. The step S204a of waiting for is passed.

Next, during the timing T2 of the clock signal, the bus arbiter device 100 outputs the clock signal from the bus right grant device 108 to the bus master B10.
4b is given the bus right by the bus use permission signal GNT-B, and the bus right is notified to the bus state monitoring device 106 until the bus idle monitoring signal is notified to the bus state monitoring device 106 during the period when the output of the clock signal is also zero at the timing T2. The application device 108 goes through step S204b of waiting for the bus 102 to be released.

Further, during the timing T3 when the clock signal is output, the bus arbiter device 100 outputs the clock signal from the bus right grant device 108 to the bus master C10.
4c is given a bus right by the bus use permission signal GNT-C, the bus right is given to the bus state monitoring device 106 until the bus idle monitoring signal is notified to the bus state monitoring device 106 during the period when the clock signal is also output zero at the timing T3. The granting device 108 goes through step S204c of waiting for the bus 102 to be released.

After that, the same operation is performed, the bus right is sequentially moved, and since there is no request from each bus master 104 to use the bus, the bus right is sequentially moved to the next bus master 104.

With this configuration, each bus master 1
It is possible to reduce the arbitration latency between the bus use permission signals in 04.

The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to such examples. It is obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and naturally, these are also within the technical scope of the present invention. It is understood that it belongs.

For example, in this embodiment of the present invention, three bus masters 104 are connected to one bus 102. However, even if the number of connected bus masters 104 is arbitrary, the same as in this embodiment. Similar effects can be obtained by using different configurations and functions.

[0073]

As described above, according to the present invention,
Each bus master can evenly obtain the bus use right regardless of the bus use frequency of other bus masters. The arbitration latency required for the request can be reduced, and the fairness of the bus use right of each bus master and the access time can be improved.

Further, according to the present invention, since the bus use request signal is not required as in the conventional case, the use signal can be reduced.

[Brief description of drawings]

FIG. 1 is an overall connection diagram for connecting a plurality of bus masters to a bus arbiter device of the present invention.

FIG. 2 is a state transition diagram of the bus arbiter device according to the embodiment of the present invention.

FIG. 3 is a timing chart showing a bus right-giving state and a state of the bus arbiter device at that time.

FIG. 4 is a timing chart showing a bus right-giving state and a state of the bus arbiter device at that time.

FIG. 5 is a timing chart showing a bus right-giving state and a state of the bus arbiter device at that time.

[Explanation of symbols]

100 bus arbiter device 102 bus 104 bus master 104a Bus master A 104b Bus master B 104c Bus master C 106 Bus status monitoring device 108 bus right granting device

Claims (8)

[Claims] 1. A bus arbiter device for arbitrating the bus right of a plurality of bus masters connected to one bus, comprising: a bus right granting device for sequentially granting the bus right to the plurality of bus masters in a preset order. Bus arbiter device characterized by. 2. A bus status monitoring device for monitoring the usage status of the bus is further provided, and the bus right granting device, when the bus status monitoring device determines that the bus is in an idle state, The bus arbiter device according to claim 1, wherein the bus master is permitted to transfer the bus right. 3. A bus status monitoring device for monitoring the usage status of the bus, wherein the bus right granting device, when the bus status monitoring device determines that the bus is in use, The bus arbiter device according to claim 1, wherein transfer of the bus right to the bus master is prohibited. 4. The method according to claim 1, wherein the granting of the bus right to each of the bus masters by the bus granting device and the monitoring of the usage status of the bus by the bus status monitoring device are performed at different timings. Bus arbiter device. 5. A bus arbiter method for arbitrating bus rights of a plurality of bus masters connected to one bus: a bus arbiter method, wherein bus rights are sequentially given to the plurality of bus masters in a preset order. 6. The bus arbiter according to claim 5, wherein the bus usage state is monitored, and when it is determined that the bus is in an idle state, the bus right transfer to the next bus master is permitted. Method. 7. The bus arbiter according to claim 5, wherein the bus arbiter is forbidden to transfer the bus right to the next bus master when it is determined that the bus is in the in-use state by monitoring the in-use state of the bus. Method. 8. The method according to claim 5, wherein the granting of the bus right to each of the bus masters by the bus granting device and the monitoring of the bus usage status by the bus status monitoring device are performed at different timings. Bus arbiter method.