JP3699529B2 - Bus control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bus control device, and more particularly, in an arithmetic processing system having a microcomputer, various peripheral circuits connected to a processor (MPU or CPU), peripheral devices, or interfaces thereof are under the control of the bus control device. Control in which the priority order of processors such as MPU or CPU is high and the allocation of usage time of the right to use buses of peripheral devices and peripheral circuits can be efficiently performed when the bus is used in common Relates to the device.
[0002]
[Prior art]
In a computer system in which a processor and various peripheral circuits and devices are connected by a bus and data is exchanged using the bus, a processor such as an MPU or CPU is connected to various circuits and devices via the bus. .
Usually, since the data transmission frequency is high between the processor and the memory, they are connected by a dedicated bus. However, peripheral circuits such as peripheral devices and interface circuits (in this specification, these are referred to as peripheral devices). ) Adopts a configuration in which they are connected to each other or to processors via a bus control device.
[0003]
In such a case, when each peripheral device generates a bus use request (bus request), a right to use the bus for a predetermined time (bus right) is allocated accordingly, but the time from bus request to bus use is assigned. There are limitations. For example, a communication control device or the like cannot receive the next data unless it receives the received data and transfers it to the buffer memory via the bus. Therefore, the bus right must be acquired within a certain time. Therefore, the processor and peripheral devices use the bus under time restrictions.
When a processor tries to access a bus on the peripheral device side, it assigns a bus to the processor preferentially and waits for the peripheral device, and assigns a bus to the peripheral device side preferentially and the peripheral device assigns the bus. When used, there is a method of making the processor wait.
[0004]
[Problems to be solved by the invention]
However, in such a computer apparatus, when the bus right is given to the processor preferentially, all peripheral devices request the bus right based on the use of the processor bus. Therefore, when the processor frequently accesses the bus used by the peripheral device, the time until the bus right is given to each peripheral device cannot be maintained depending on the processing contents of the processor, which is a problem.
[0005]
On the other hand, when a bus right is preferentially given to the peripheral device side, when multiple peripheral devices request the bus right simultaneously or continuously, the bus right is routed to the processor until the bus use of all the peripheral devices is completed. There is a problem that does not come. In such a case, the use of the bus in a certain peripheral device is completed, and the processor waits for the next peripheral device to wait for even though the bus is not used. In this case, as long as the peripheral device makes a bus request, the processor does not have the right to use the bus, so that the processing capacity of the processor is reduced.
An object of the present invention is to solve such a problem of the prior art, and even when all peripheral devices make a bus request, it guarantees the time until each peripheral device acquires the bus right, It is another object of the present invention to provide a bus control device that allows a processor to use a bus even when there is a bus use request from each peripheral device.
[0006]
[Means for Solving the Problems]
A feature of the bus control device of the present invention for achieving such an object is that it accepts a bus use request from a processor and a bus use request of a peripheral device at each request timing, and n processors (however, n Is a computer device in which the processor and the peripheral device exchange data with the peripheral device sharing the bus via the bus control device and using the bus after the peripheral device requests the use of the bus. Period T / {(n + 1) k} by dividing period T into (n + 1) k pieces (where k is a positive number greater than or equal to 2) with period T corresponding to the minimum allowable time until start of the period as a period. corresponds to a unit period of allocation of k min the unit period of k as a bus period of use of the processor as the unit period duration T / (n + 1) of n around Device respectively Period T / a {(n + 1) k} as a unit in each of the periods T by assigning the bus use period of the scan
When there is a processor bus use request, a unit period is assigned to the use period of the period T / (n + 1) assigned according to the bus use request of the peripheral device, with the end of this use period as the processor bus use period. ensuring the k component with minimal, peripheral devices T / assigned to the peripheral device without bus request Nico when there is no bus request (n + 1) of the processor assigns a unit period as a bus usage period of the processor for The use of the bus is allowed and the unit period is increased by k in the period T.
[0007]
As a more specific configuration of the present invention, a means for detecting a bus request from a peripheral device and a time that each peripheral device must start after requesting a bus right is set as a reference time T, and the reference time T is within the reference time T. Is assigned the time T / {(n + 1) k} at which the processor can use the bus on the peripheral device side, and k is the number of times the processor can access the bus from the bus use time T / (n + 1) when the processor accesses the bus. By forcibly setting it, for example, by setting it as an initial value in the counter, when the peripheral device does not use the bus, the count value of this counter is counted up by k for that time, and the processor The number of times the bus can be accessed is subtracted until the counter reaches zero each time the processor accesses the bus. Then, when the count value becomes zero, the processor access during the period T is prohibited.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
According to the present invention, in the computer device, when there are many accesses from all peripheral devices to the peripheral device side bus within the reference time, the number of times the processor can access the bus is reduced, and accordingly, the peripheral device Can be accessed in the period T / (n + 1), respectively, and the processor can access at least the number of times k with the set time T / {(n + 1) k} as a unit. In this case, the waiting time increases, but the reference time T can be maintained, so that the operation of the peripheral device is not hindered. Further, when there are few bus requests from each peripheral device to the bus, the number of times the processor can access the bus increases by k according to the period T / {(n + 1) k}. Processor latency can be reduced.
As a result, even when all peripheral devices make a bus request, the time until each peripheral device acquires the bus right can be guaranteed, and the processor uses the bus even if there is a bus request from each peripheral device. can do. Furthermore, when there is free time on the bus, the waiting time of the processor can be shortened as much as possible.
[0009]
【Example】
FIG. 1 is a block diagram of an embodiment to which the bus control device of the present invention is applied, and FIG. 2 is a block diagram of a computer system having this bus control device.
FIG. 2 shows a bus controller 107 (which is shown as a bus controller 107 as a part of the entire system in the drawing), by connecting a processor and a plurality of peripheral devices that use the bus irregularly to a common bus. This will be described as the bus control device 107.) The use of this bus is adjusted.
In FIG. 2, the processor 101 and the main memory 102 are connected by a processor side bus 109. Peripheral device (1) 103, peripheral device (2) 104, peripheral device (3) 105, peripheral device (4) 106, and buffer memory 108 are connected to each other via peripheral device side bus 110.
The processor-side bus 109 and the peripheral device-side bus 110 are connected via a bus control device 107, and the bus control device 107 assigns the bus 110 and controls bus arbitration. When the processor 101 accesses the main memory 102, only the processor side bus 109 is used, and the bus control device 107 does nothing. In this case, the peripheral device side bus 110 is not affected.
[0010]
The processor 101 accesses the peripheral device side bus 110 via the bus control device 107 when accessing each peripheral device (103, 104, 105, 106) and the buffer memory 108.
FIG. 1 is a block diagram of a bus control device 107 that manages the use of the bus 110 and controls arbitration for this access and the like.
In FIG. 1, the bus control device 107 includes a counter 301, a comparator 302, a monitoring timing generation circuit 303, a peripheral device bus request detection circuit 304, a processor bus request detection circuit 305, a bus arbitration control circuit 306, and the like. Thus, the processor bus request detection circuit 305 and the comparator 302 constitute a detection circuit of the present invention. In addition, the bus arbitration control circuit 306 may be configured mainly with a processor and a program executed by the processor.
[0011]
The bus arbitration control circuit 306 is a peripheral device having a minimum allowable time from the request for use of the bus to the start of use of the peripheral device (103, 104, 105, 106), for example, the peripheral device (1) 103. The period T is substantially divided into (n + 1) × k (n = 4, k = 2), and the unit of the period of each peripheral device and the bus use period of the processor 101 is T. / 10, a period T / 10 is assigned to the processor 101, and a period T / 5 is assigned to each peripheral device (103, 104, 105, 106). When a bus request is issued from the processor 101, a period T / 10 is inserted after the period of each peripheral device. Insertion of up to k periods T / 10 of the processor 101, up to two (k = 2) in this embodiment is permitted. If there is no bus right request in each peripheral device period, the bus right is given to the processor 101 at the beginning of the period, and the next peripheral device period starts.
[0012]
3A and 3B show the processor 101 and the peripheral device (1) 103, the peripheral device (2) 104, the peripheral device (3) 105, and the peripheral device (4) 106 in the bus arbitration control circuit 306, respectively. It is a figure showing the allocation time of the bus. Referring to FIG. 3A, this is because the bus request from the processor 101 is in the period of the peripheral device 103 and the peripheral device 104, and the bus use request of the processor 101 is made twice, once after these periods. Is an example of accepting.
Accordingly, a period T / 10 (= period T / {(n + 1) k}) is inserted as the processor access period (CPU) 202 after the periods 204 and 206 of the peripheral device 103 and the peripheral device 104, respectively.
[0013]
As a result, the right to use the bus of the processor 101 can be secured. Therefore, the bus usage period of the peripheral device 103 and the peripheral device 104 and the bus usage period of the processor 101 are 2: 1. The period T / 10 is secured as the bus use period 202 of the processor 101, and the period 2T / 10 is set for each of the period 204 of the peripheral device 103, the period 206 of the peripheral device 104, the period 208 of the peripheral device 105, and the period 210 of the peripheral device 106. In order to allocate (= T / 5), the bus arbitration control circuit 306 manages the use of the bus 110 with a pulse PT having a period corresponding to the reference period T from the monitoring timing generation circuit 303 (see FIG. 4A). In response to the timing pulse Pc (period T / 10 = period T / {(n + 1) k}, see FIG. 4B), the bus use adjustment control is performed in accordance with these timing pulses.
[0014]
FIG. 4 is an explanatory diagram of timing pulses of the monitoring timing generation circuit 303.
(B) is the timing pulse Pc. The period TC of this pulse corresponds to the period T / 10 (= period T / {(n + 1) k}). In (a), a pulse having a period T indicating a reference period is a reference pulse PT.
By the way, there is a time limit between the peripheral device (1) 103, the peripheral device (2), the 104 peripheral device (3) 105, and the peripheral device (4) 106 requesting the bus and acquiring the bus. During this time, the bus usage time of the processor 101 and all peripheral devices (1) 103, peripheral device (2) 104, peripheral device (3) 105, and peripheral device (4) 106 must be allocated. Therefore, a reference time T is set corresponding to the shortest time limit among these peripheral devices.
[0015]
For example, when frame communication protocol processing is performed in the communication control apparatus, the reference time T is within a time related to the FIFO (first-in first-out) buffer size in the device until reception ends when frame reception is started. It is necessary to transfer the received data stored in the buffer memory 108. In such a case, usually, a bus request is generated when the data is received until one-half of the reception buffer of the FIFO. Therefore, if the bus request is not accepted before the remaining half is received, the reception fails.
This period is the time limit for bus allocation. If this is the minimum time with respect to the time limit of other peripheral devices, it is used as the reference time T. In this embodiment, for example, the peripheral device 103 corresponds to the device having the minimum time T.
[0016]
Here, the access time when the processor 101 uses the peripheral device side bus 110 is the bus use time TP (= period T / 10) of the processor 101. In this embodiment, the bus use time (203, 205, 207, 209) when each peripheral device T (103, 104, 105, 106) uses the bus 110 is the bus use time TP of the processor 101. It is supposed to take exactly twice.
Bus request monitoring time 203 of peripheral device (1) 103, bus request monitoring time 205 of peripheral device (2) 104, bus request monitoring time 207 of peripheral device (3) 105, bus request monitoring time of peripheral device (4) 106 For convenience of explanation, 209 has a range in the figure, but since it is actually a minute time, it is assigned at the beginning of the timing of occurrence of each bus use period and can be ignored. A monitoring pulse PD for this purpose is shown in FIG.
[0017]
In this embodiment, even when the processor 101 and all peripheral devices (103, 104, 105, 106) use the bus 110 within the reference time T, the bus allocation is performed as shown in FIG. The time TP can be allocated up to twice (k = 2) within the reference time T. Therefore, the initial value of the access count counter 301 of the processor 101 is set to 2. This is set in the counter 301 in accordance with the generation of the reference pulse PT shown in FIG.
[0018]
The bus control device 107 monitors the bus right requests of the processor 101 and all peripheral devices (103, 104, 105, 106) in synchronization with the reference time T or less by the monitoring timing generation circuit 303. For example, if four peripheral devices are monitored, the monitoring timing generation circuit 303 generated from the monitoring timing generation circuit 303 sends a monitoring pulse PD having a narrow width to the peripheral device bus request detection circuit 304 in the period TD. Thus, the bus request of each peripheral device is monitored and the usage period of the processor is managed by the cant value of the counter 301.
Here, the period T / 5 divided into five reference times T is divided into two, and T / 10 is allocated to the bus usage period (CPU) of the processor 101. Therefore, each peripheral device 103, 104 is If the process does not end in the period T / 5 allocated as described above, a process of saving the data being processed to the buffer memory or the like and waiting until the next bus use period is performed. The same applies to the processor 101.
[0019]
The peripheral device bus request detection circuit 304 includes AND gates 304a, 304b, 304c, and 304d and an OR gate 304e that receives the outputs of these AND gates.
The AND gate 304 a receives a bus request from the peripheral device 103 and receives a monitoring pulse PD generated at the initial timing 203 of the period 204. The AND gate 304 b receives a bus request from the peripheral device 104 and receives a monitoring pulse PD generated at the initial timing 205 of the period 204. The AND gate 304 c receives a bus request from the peripheral device 104 and receives a monitoring pulse PD generated at the initial timing 207 of the period 208. The AND gate 304d receives a bus request from the peripheral device 105 and receives a monitoring pulse PD generated at the initial timing 209 of the period 210.
[0020]
The bus request signal is a LOW level (hereinafter, “L”) significant signal. When there is a bus request to each peripheral device, the output of each AND gate is “ L ”. As a result, the output of the OR gate 304e becomes “L” when there is a bus request, and the counter 301 is not added with the count value. On the other hand, if there is no bus request in any of the monitoring periods, the output of the OR gate 304e becomes HIGH level (hereinafter “H”), the numerical value 2 is added to the counter 301, and the count value is incremented by 2. .
Thus, the peripheral device bus request detection circuit 304 detects whether or not there is a bus request during the bus usage time of the peripheral device (103, 104, 105, 106). The right to use the bus is released to the processor 101.
The output of the OR gate 304e is applied to the bus arbitration control circuit 306. When this output is "L", it is determined that there is a bus request, and a signal that gives the bus right to the peripheral device corresponding to the generated timing is bus arbitrated. The control circuit 306 sends out.
[0021]
The monitoring timing generation circuit 303 sends a timing pulse Pc to the processor bus request detection circuit 305 to monitor the bus request of the processor 101. The processor bus request detection circuit 305 includes an AND gate 305a and an inverter 305b. The AND gate 305a receiving the timing pulse Pc receives a bus request from the processor 101 via the inverter 305b. As a result, the bus request is set to “H”. The AND gate 305a also receives the output of the comparator 302. As a result, the bus request from the processor 101 is accepted by the bus arbitration control circuit 306 via the AND gate 305a unless the count value becomes zero. The output of the AND gate 305a is input to the subtraction output of the counter 301, and the count value is decremented by 1 for each access. As a result, the access can be performed only twice in the initial setting, in other words, only during the period 202.
The outputs of the AND gate 305a and the OR gate 304e are input to the monitoring timing generation circuit 303. When there is no bus request from the peripheral device during the period of any peripheral device and there is a bus request of the processor 101, the monitoring timing generation circuit As shown in (d) of FIG. 4, 303 generates the next generation of the monitoring pulse Pd by shifting it forward by the period T / 10. (D) shows a case where the peripheral device (1) 103 has no bus right request. When there is no bus request in the peripheral device corresponding to the monitoring pulse Pd, the right to use the bus is given to the processor 101 for a period of T / 10. This is an example shown in FIG.
[0022]
The output of the counter 301 is input to the comparator 302, and whether or not the value is equal to or less than zero is compared. When the value is equal to or less than zero, a LOW level detection output is sent to the AND gate 305b. Bus requests are blocked.
When the bus arbitration control circuit 306 receives a bus request from the processor 101 when the output of the OR gate 304e is "L", the bus arbitration control circuit 306 limits the bus use period of the peripheral device to T / 6 and the remaining period T / At the first timing of 12, a signal for giving the bus right to the processor 101 is sent to the processor 101, and the bus 110 is released to the processor 101.
When the output of the OR gate 304e is "H", that is, when a bus request is received from a peripheral device, the bus arbitration control circuit 306 receives the bus request from the processor 101 and uses the bus of the peripheral device. A signal for giving the bus right for the period T / 10 out of the period T / 5 to the processor 101 is sent to the processor 101 to release the bus 110 to the processor 101. In this case, without performing the control as shown in FIG. 4 (d), a signal for generating the bus right for the period T / 10 out of the bus use period T / 5 is generated twice to generate the period. The bus may be used by a T / 10 processor.
[0023]
3A, the operation of the bus control apparatus will be described. The peripheral device (1) 103 is within the bus request monitoring time 203, and the peripheral device (2) 104 is within the bus request monitoring time 205. The device (3) 105 requests the use of the bus within the bus request monitoring time 207 while the peripheral device (4) 106 requests the use of the bus within the bus request monitoring time 209, and each of the peripheral devices (103, 104, 105, 106). At the time of bus request monitoring (203, 205, 207, 209), the counter 301 is not added and the value of the counter 301 is decremented by 1 only when the processor 101 uses the peripheral device side bus 110.
When the processor 101 uses the bus for the second time, the value of the counter 301 is 0. Therefore, the bus controller 107 determines that the peripheral device (4) 106 after the bus use time 208 of the peripheral device (3) 105. Even if there is a bus right request of the processor 101 after the bus use time 210, as long as the output result of the comparator 302 is “L” (= false), the bus right is not given to the processor 101.
When the bus usage time 210 of the peripheral device (4) 106 is completed, since all the reference time T is used, the head 215 of the monitoring cycle is issued to the counter 301, and the 301 value of the counter is set to the initial value 2. return.
[0024]
The operation of the bus control apparatus will be described with respect to the example of FIG. 3B. The peripheral device (1) 103 has no bus right request within the bus request monitoring time 203, and the initial value 2 of the counter 301 is 2 is added to the counter 301 after the bus request monitoring time 203 of the peripheral device (1) 103 for which no bus right request has been made, and the value is set to 4. Thereafter, when the processor 101 uses the peripheral device side bus 110, even if the value of the counter 301 is decremented by one, the value of the counter 301 shows a value larger than 0 at the timing of the bus right request of all the processors 101. Access to the peripheral device bus 110 of the processor 101 becomes possible.
[0025]
As described above, the time that each peripheral device (103, 104, 105, 106) did not use the bus can be used, and the time during which the processor 101 can use the bus within the reference time T can be increased without bias. The waiting time of the peripheral device side bus 110 of 101 can be reduced.
[0026]
【The invention's effect】
As described above, according to the present invention, a processor and a plurality of peripheral devices connected to different buses are provided, and there is a limit in time until a bus right is assigned to each peripheral device. In the apparatus, the processor can guarantee the time from when the peripheral device requests the bus to using the bus by varying the bus allocation time of the processor according to the bus usage status from the peripheral device within the time limit of the peripheral device. Can preferentially and effectively use the bus and reduce processor latency.
[Brief description of the drawings]
FIG. 1 is a block diagram of an embodiment to which a bus control device of the present invention is applied.
FIG. 2 is a configuration diagram of a computer system having the bus control device.
FIGS. 3A and 3B are explanatory diagrams of the period management of the bus right of the bus arbitration control circuit, wherein FIG. 3A is an explanatory diagram when a peripheral device has a bus request, and FIG. It is explanatory drawing in case there is no bus request in one of the devices.
FIG. 4 is an explanatory diagram of timing pulses of the monitoring timing generation circuit of FIG. 1;
[Explanation of symbols]
101 ... Processor, 102 ... Main memory,
103: Peripheral device (1), 1104: Peripheral device (2)
105 ... Peripheral device (3), 106 ... Peripheral device (4),
107: Bus control device, 108: Buffer memory,
109 ... processor side bus,
110: Peripheral device side bus,
111 ... Access count counter,
301 ... Counter,
302 ... Comparator,
303 ... monitoring timing generation circuit,
T: Reference time, TP: Processor bus usage time.

Claims (4)

Accepted at each request timing and bus use request of a bus use request and the peripheral devices from the processor to each of the processor and the n (where n is 2 or more positive) and the said peripheral device via the bus control unit In the computer apparatus in which the processor and the peripheral device exchange data by sharing the bus, a period corresponding to the minimum allowable time from when the peripheral device requests to use the bus until the use of the bus can be started is a period T as substantially the period T (n + 1) k number (where k is 2 or more positive) the period is divided into T / {(n + 1) k} this unit period k pieces as a unit period of the processor allocation period corresponding to the unit period of allocation of k min as a bus usage period T / a (n + 1) to the bus use period of each of the n-number of peripheral devices The period T / a {(n + 1) k} as a unit in each of the periods T in Rukoto,
When there is a bus use request of the processor, the use period after the use period is set as the bus use period of the processor with respect to the use period of the period T / (n + 1) allocated according to the bus use request of the peripheral device. securing said k pieces minute with minimum assigns the unit period, the bus of the processor for said assigned to the peripheral device without bus request Nico when no bus request of the peripheral device the T / (n + 1) A bus control device that allocates the unit period as a use period to allow the processor to use the bus and increases the unit period by k in the period T. A bus use request of the peripheral device to which this period is assigned at least at the start time of the period T / (n + 1) assigned to each peripheral device in response to a timing pulse in units of the period T / {(n + 1) k} The bus control device according to claim 1, wherein the bus control apparatus allocates the bus use of the processor in the unit period to the bus use request of the processor according to a detection result . Accepted at each request timing and bus use request of a bus use request and the peripheral devices from the processor to each of the processor and the n (where n is 2 or more positive) and the said peripheral device via the bus control unit In the computer apparatus in which the processor and the peripheral device exchange data by sharing the bus, the period T corresponds to the allowable minimum time from when the peripheral device requests the use of the bus until the use of the bus can be started. A timing pulse generating circuit for generating a timing pulse having a period substantially equal to the period T / {(n + 1) k} (where k is a positive number of 2 or more);
In response to the timing pulse, the period T / {(n + 1) k} is assigned as the bus use period of the processor, the period T / (n + 1) is assigned to the bus use period of the n peripheral devices, and the processor When there is a bus use request, in response to a control signal corresponding thereto, the use period after the use period is compared with the use period of the period T / (n + 1) assigned according to the bus use request of the peripheral device. securing said k pieces minute with minimum assigns the unit period as a bus period of use of the processor, the when there is no bus request of the peripheral device in response to said control signal, to the peripheral device without bus request this the allocated the T / (n + 1) assigns said unit period as a bus use period of the processor allows the bus use of the processor And a bus arbitration control unit for the control of increasing the k partial unit period in a period of the period T,
In the period T / (n + 1) allocated to each peripheral device, it detects whether or not the peripheral device to which this period is allocated has a bus use request at the start time and responds to the bus use request from the processor. And a detection circuit for generating the control signal. Wherein the detection circuit includes a counter for storing the k at the start of the T period, the n each said period from the peripheral device assigned to each said peripheral device receiving said bus request T / (n + 1) A count value generating circuit for detecting whether or not there is a bus use request in the peripheral device to which this period is assigned at the start of the counter, and counting up the counter by k when there is no bus use request, and the processor When using the bus, the counter is decremented by 1 every period T / {(n + 1) k} as a unit, and when the count value of the counter is 1 or more, a bus use request from the processor The bus control device according to claim 3, further comprising: a gate circuit that generates a signal as the control signal.

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