JP2003099324A - マルチメディアプロセッサ用のストリーミングデータキャッシュ - Google Patents
マルチメディアプロセッサ用のストリーミングデータキャッシュInfo
- Publication number
- JP2003099324A JP2003099324A JP2002201010A JP2002201010A JP2003099324A JP 2003099324 A JP2003099324 A JP 2003099324A JP 2002201010 A JP2002201010 A JP 2002201010A JP 2002201010 A JP2002201010 A JP 2002201010A JP 2003099324 A JP2003099324 A JP 2003099324A
- Authority
- JP
- Japan
- Prior art keywords
- data
- bus
- memory
- cache memory
- external
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/60—Details of cache memory
- G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/903,008 US20030014596A1 (en) | 2001-07-10 | 2001-07-10 | Streaming data cache for multimedia processor |
| US09/903008 | 2001-07-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2003099324A true JP2003099324A (ja) | 2003-04-04 |
| JP2003099324A5 JP2003099324A5 (enExample) | 2005-10-20 |
Family
ID=25416776
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002201010A Pending JP2003099324A (ja) | 2001-07-10 | 2002-07-10 | マルチメディアプロセッサ用のストリーミングデータキャッシュ |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US20030014596A1 (enExample) |
| JP (1) | JP2003099324A (enExample) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006513510A (ja) * | 2003-01-27 | 2006-04-20 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 書き込みデータをキャッシュにインジェクトする方法及び装置 |
| JP2006134324A (ja) * | 2004-10-28 | 2006-05-25 | Internatl Business Mach Corp <Ibm> | ロッキング・キャッシュを用いる直接的保存 |
| JP2008503003A (ja) * | 2004-06-30 | 2008-01-31 | インテル・コーポレーション | コヒーレント・マルチプロセッサ・プロトコルを有するシステムにおけるダイレクト・プロセッサ・キャッシュ・アクセス |
| JP2008503807A (ja) * | 2004-06-29 | 2008-02-07 | インテル・コーポレーション | コヒーレンシ・プロトコルを有するシステム内の1またはそれ以上のプロセッサに対応する1またはそれ以上のキャッシュへのクリーン・データのプッシング |
| KR100847066B1 (ko) | 2006-09-29 | 2008-07-17 | 에스케이건설 주식회사 | 홈 멀티미디어 센터를 이용한 웹 스토리지 서비스 시스템및 서비스 방법 |
| JP2008204292A (ja) * | 2007-02-21 | 2008-09-04 | Toshiba Corp | メモリ管理システム |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2004102971A1 (en) * | 2003-05-19 | 2004-11-25 | Koninklijke Philips Electronics N.V. | Video processing device with low memory bandwidth requirements |
| US9785545B2 (en) * | 2013-07-15 | 2017-10-10 | Cnex Labs, Inc. | Method and apparatus for providing dual memory access to non-volatile memory |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5787472A (en) * | 1995-07-31 | 1998-07-28 | Ibm Corporation | Disk caching system for selectively providing interval caching or segment caching of vided data |
| US5898892A (en) * | 1996-05-17 | 1999-04-27 | Advanced Micro Devices, Inc. | Computer system with a data cache for providing real-time multimedia data to a multimedia engine |
| US6438652B1 (en) * | 1998-10-09 | 2002-08-20 | International Business Machines Corporation | Load balancing cooperating cache servers by shifting forwarded request |
-
2001
- 2001-07-10 US US09/903,008 patent/US20030014596A1/en not_active Abandoned
-
2002
- 2002-07-10 JP JP2002201010A patent/JP2003099324A/ja active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006513510A (ja) * | 2003-01-27 | 2006-04-20 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | 書き込みデータをキャッシュにインジェクトする方法及び装置 |
| JP2008503807A (ja) * | 2004-06-29 | 2008-02-07 | インテル・コーポレーション | コヒーレンシ・プロトコルを有するシステム内の1またはそれ以上のプロセッサに対応する1またはそれ以上のキャッシュへのクリーン・データのプッシング |
| JP2008503003A (ja) * | 2004-06-30 | 2008-01-31 | インテル・コーポレーション | コヒーレント・マルチプロセッサ・プロトコルを有するシステムにおけるダイレクト・プロセッサ・キャッシュ・アクセス |
| JP2006134324A (ja) * | 2004-10-28 | 2006-05-25 | Internatl Business Mach Corp <Ibm> | ロッキング・キャッシュを用いる直接的保存 |
| KR100847066B1 (ko) | 2006-09-29 | 2008-07-17 | 에스케이건설 주식회사 | 홈 멀티미디어 센터를 이용한 웹 스토리지 서비스 시스템및 서비스 방법 |
| JP2008204292A (ja) * | 2007-02-21 | 2008-09-04 | Toshiba Corp | メモリ管理システム |
Also Published As
| Publication number | Publication date |
|---|---|
| US20030014596A1 (en) | 2003-01-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11822786B2 (en) | Delayed snoop for improved multi-process false sharing parallel thread performance | |
| US5572703A (en) | Method and apparatus for snoop stretching using signals that convey snoop results | |
| US6115761A (en) | First-In-First-Out (FIFO) memories having dual descriptors and credit passing for efficient access in a multi-processor system environment | |
| JP3289661B2 (ja) | キャッシュメモリシステム | |
| US7620749B2 (en) | Descriptor prefetch mechanism for high latency and out of order DMA device | |
| US8549231B2 (en) | Performing high granularity prefetch from remote memory into a cache on a device without change in address | |
| US5388247A (en) | History buffer control to reduce unnecessary allocations in a memory stream buffer | |
| CN100549992C (zh) | 可减少延迟的数据传送与接收方法与系统 | |
| JP3365433B2 (ja) | キャッシュメモリ構成体とその使用方法 | |
| US6453388B1 (en) | Computer system having a bus interface unit for prefetching data from system memory | |
| US7228389B2 (en) | System and method for maintaining cache coherency in a shared memory system | |
| TW542958B (en) | A method and apparatus for pipelining ordered input/output transactions to coherent memory in a distributed memory, cache coherent, multi-processor system | |
| JP2012009048A (ja) | バス上のメモリプリフェッチコマンドを送信するための方法および装置 | |
| JP2695017B2 (ja) | データ転送方式 | |
| US6412047B2 (en) | Coherency protocol | |
| US6615296B2 (en) | Efficient implementation of first-in-first-out memories for multi-processor systems | |
| US6425071B1 (en) | Subsystem bridge of AMBA's ASB bus to peripheral component interconnect (PCI) bus | |
| JP2003099324A (ja) | マルチメディアプロセッサ用のストリーミングデータキャッシュ | |
| US6976130B2 (en) | Cache controller unit architecture and applied method | |
| US6836823B2 (en) | Bandwidth enhancement for uncached devices | |
| CN100557584C (zh) | 用于对网络和存储器进行耦合的存储器控制器和方法 | |
| US7035981B1 (en) | Asynchronous input/output cache having reduced latency | |
| US20090089468A1 (en) | Coherent input output device | |
| US6266741B1 (en) | Method and apparatus to reduce system bus latency on a cache miss with address acknowledgments | |
| JP2001229074A (ja) | メモリ制御装置と情報処理装置及びメモリ制御チップ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050621 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20050621 |
|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20081001 |
|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081014 |
|
| A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20090407 |