JP2003095733A - Package for housing semiconductor device - Google Patents

Package for housing semiconductor device

Info

Publication number
JP2003095733A
JP2003095733A JP2001287702A JP2001287702A JP2003095733A JP 2003095733 A JP2003095733 A JP 2003095733A JP 2001287702 A JP2001287702 A JP 2001287702A JP 2001287702 A JP2001287702 A JP 2001287702A JP 2003095733 A JP2003095733 A JP 2003095733A
Authority
JP
Japan
Prior art keywords
semiconductor element
weight
copper
frame
shaped insulator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001287702A
Other languages
Japanese (ja)
Inventor
Shin Matsuda
伸 松田
Masaaki Iguchi
公明 井口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2001287702A priority Critical patent/JP2003095733A/en
Publication of JP2003095733A publication Critical patent/JP2003095733A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PROBLEM TO BE SOLVED: To solve the problem wherein heat generated during working of a semiconductor device can not be released, and thermal cracking occurs on the semiconductor device. SOLUTION: The package for housing a semiconductor device consists of a substrate 1 with a three layer structure. The upper and lower sides of an intermediate layer 1c consisting of, by weight, 40 to 70% tungsten and 30 to 60% copper are provided with the upper and lower layers 1b and 1d consisting of 25 to 35% tungsten and 65 to 75% copper, a frame-shaped insulator 2 consisting of a sintered compact obtained by sintering a formed body containing 20 to 80 vol.% of lithium silicate glass containing 5 to 30 wt.% Li2 O3 , and having a point of 40 to 800 deg.C, and 20 to 80 vol.% of a filler component consisting of at least one kind selected from quartz, cristobalite, tridymite, enstatite and forsterite, and containing at least one kind of crystal phase selected from quartz, cristobalite, tridymite, enstatite and forsterite, and a cover body 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明はLSI(大規模集積
回路素子)や光半導体素子等の半導体素子を収容するた
めの半導体素子収納用パッケージに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element housing package for housing a semiconductor element such as an LSI (Large Scale Integrated Circuit Element) or an optical semiconductor element.

【0002】[0002]

【従来の技術】従来、半導体素子を収容するための半導
体素子収納用パッケージは、上面に半導体素子が載置さ
れる載置部を有する銅−タングステン合金や銅−モリブ
デン合金等の金属材料からなる基体と、該基体の上面に
前記載置部を囲繞するようにして取着された酸化アルミ
ニウム質焼結体等の電気絶縁材料からなる枠状絶縁体
と、該枠状絶縁体の内周部から外周部にかけて被着導出
されているタングステン、モリブデン、マンガン等の高
融点金属からなる複数個の配線層と、前記枠状絶縁体の
上面に取着され、絶縁体の内側の穴を塞ぐ蓋体とから構
成されており、基体の半導体素子載置部に半導体素子を
接着剤を介して接着固定するとともに該半導体素子の各
電極をボンディングワイヤを介して枠状絶縁体に形成し
た配線層に電気的に接続し、しかる後、枠状絶縁体に蓋
体を該枠状絶縁体の内側の穴を塞ぐようにしてガラス、
樹脂、ロウ材等から成る封止材を介して接合させ、基体
と枠状絶縁体と蓋体とからなる容器内部に半導体素子を
気密に収容することによって製品としての半導体装置と
なる。
2. Description of the Related Art Conventionally, a semiconductor element accommodating package for accommodating a semiconductor element is made of a metal material such as a copper-tungsten alloy or a copper-molybdenum alloy having a mounting portion on which the semiconductor element is mounted. A base body, a frame-shaped insulator made of an electrically insulating material such as an aluminum oxide sintered body attached to the upper surface of the base body so as to surround the mounting portion, and an inner peripheral portion of the frame-shaped insulator A plurality of wiring layers made of refractory metal such as tungsten, molybdenum, manganese, etc., which are adhered and led from the outer periphery to the outer peripheral portion, and a lid which is attached to the upper surface of the frame-shaped insulator and closes the hole inside the insulator. The semiconductor element is bonded and fixed to the semiconductor element mounting portion of the base body with an adhesive, and each electrode of the semiconductor element is formed on the wiring layer formed on the frame-shaped insulator through the bonding wire. Electrically Continued, and thereafter, the glass and the lid to the frame-shaped insulating member so as to close the inner hole of the frame-shaped insulator,
A semiconductor device as a product is obtained by joining them through a sealing material made of resin, a brazing material, etc., and hermetically housing the semiconductor element in a container made of a base, a frame-shaped insulator, and a lid.

【0003】なお、上述の半導体素子収納用パッケージ
においては、半導体素子が載置される基体が銅−タング
ステン合金や銅−モリブデン合金等の金属材料で形成さ
れており、該銅−タングステン合金や銅−モリブデン合
金等は熱伝導率が約180W/m・Kと高く熱伝導性に
優れていることから基体は半導体素子の作動時に発する
熱を良好に吸収するとともに大気中に良好に放散させる
ことができ、これによって半導体素子を常に適温とし半
導体素子に熱破壊が発生したり、特性に熱劣化が発生し
たりするのを有効に防止している。
In the above-mentioned package for accommodating semiconductor elements, the substrate on which the semiconductor elements are mounted is made of a metal material such as copper-tungsten alloy or copper-molybdenum alloy, and the copper-tungsten alloy or copper is used. -Molybdenum alloys and the like have a high thermal conductivity of about 180 W / mK and are excellent in thermal conductivity. Therefore, the base body can well absorb the heat generated during the operation of the semiconductor element and dissipate it into the atmosphere. By doing so, the semiconductor element is always kept at an appropriate temperature, and it is possible to effectively prevent the semiconductor element from being thermally destroyed or the characteristics from being thermally deteriorated.

【0004】また上述の半導体素子収納用パッケージの
基体として使用されている銅−タングステン合金や銅−
モリブデン合金はタングステン粉末やモリブデン粉末を
焼成して焼結多孔体を得、次に前記焼結多孔体の空孔内
に溶融させることによって製作されており、例えば、タ
ングステンから成る焼結多孔体に銅を含浸させる場合は
焼結多孔体が75乃至90重量%、銅が10乃至25重
量%の範囲に、モリブデンから成る焼結多孔体に銅を含
浸させる場合は焼結多孔体が80乃至90重量%、銅が
10乃至20重量%の範囲となっている。
Further, copper-tungsten alloys and copper-based materials used as the base body of the above-mentioned package for accommodating semiconductor elements.
The molybdenum alloy is manufactured by firing tungsten powder or molybdenum powder to obtain a sintered porous body, and then melting the sintered porous body in the pores of the sintered porous body. When impregnated with copper, the sintered porous body has a range of 75 to 90% by weight and copper has a range of 10 to 25% by weight. When the sintered porous body made of molybdenum has been impregnated with copper, the sintered porous body has a range of 80 to 90% by weight. % By weight, and copper is in the range of 10 to 20% by weight.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、この従
来の半導体素子収納用パッケージにおいては、枠状絶縁
体を形成する酸化アルミニウム質焼結体の比誘電率が9
〜10(室温、1MHz)と高いことから枠状絶縁体に
設けた配線層を伝わる電気信号の伝搬速度が遅く、その
ため信号の高速伝搬を要求する半導体素子は収容が不可
となる欠点を有していた。
However, in this conventional package for accommodating semiconductor elements, the relative permittivity of the aluminum oxide sintered body forming the frame-shaped insulator is 9%.
Since it is as high as 10 to 10 (room temperature, 1 MHz), the propagation speed of the electric signal transmitted through the wiring layer provided in the frame-shaped insulator is slow, so that there is a drawback that a semiconductor element that requires high-speed signal propagation cannot be accommodated. Was there.

【0006】またこの従来の半導体素子収納用パッケー
ジにおいては、枠状絶縁体に形成されている配線層はタ
ングステンやモリブデン、マンガン等の高融点金属材料
により形成されており、該タングステン等はその比電気
抵抗が5.4μΩ・cm(20℃)以上と高いことから
配線層に電気信号を伝搬させた場合、電気信号に大きな
減衰が生じ、電気信号を正確、かつ確実に伝搬させるこ
とができないという欠点も有していた。
Further, in this conventional package for accommodating a semiconductor element, the wiring layer formed on the frame-shaped insulator is formed of a refractory metal material such as tungsten, molybdenum, or manganese, and the tungsten or the like has a ratio thereof. Since the electric resistance is as high as 5.4 μΩ · cm (20 ° C.) or more, when the electric signal is propagated to the wiring layer, the electric signal is greatly attenuated, and the electric signal cannot be accurately and reliably propagated. It also had drawbacks.

【0007】更にこの従来の半導体素子収納用パッケー
ジにおいては、銅−タングステン合金あるいは銅−モリ
ブデン合金から成る基体の熱伝導率は最大でも約180
W/m・K程度であり、近時の高密度化、高集積化が大
きく進み、作動時に多量の熱を発する半導体素子を収容
した場合、半導体素子が作動時に発する熱は基体を介し
て外部に完全に放散させることができなくなり、その結
果、半導体素子が該素子自身の発する熱によって高温と
なり、半導体素子に熱破壊を招来させたり、特性にばら
つきを生じ安定に作動させることができないという欠点
も有していた。
Further, in this conventional package for accommodating semiconductor elements, the thermal conductivity of the substrate made of copper-tungsten alloy or copper-molybdenum alloy is about 180 at maximum.
W / mK, which is highly integrated and highly integrated in recent years, and when a semiconductor element that generates a large amount of heat during operation is housed, the heat generated by the semiconductor element is externally transmitted through the substrate. Cannot be completely dissipated into the semiconductor element, and as a result, the semiconductor element becomes high temperature due to the heat generated by the element itself, causing thermal damage to the semiconductor element or causing a variation in characteristics, which makes it impossible to operate stably. Also had.

【0008】本発明は上記欠点に鑑み案出されたもの
で、その目的は内部に高速駆動を行う半導体素子を収容
することができ、かつ収容する半導体素子を長期間にわ
たり正常、かつ安定に作動させることができる半導体素
子収納用パッケージを提供することにある。
The present invention has been devised in view of the above-mentioned drawbacks, and an object thereof is to accommodate therein a semiconductor element which is driven at high speed, and to operate the accommodated semiconductor element normally and stably for a long period of time. Another object of the present invention is to provide a package for accommodating a semiconductor element.

【0009】[0009]

【課題を解決するための手段】本発明は、上面に半導体
素子が載置される載置部を有する基体と、前記基体上に
半導体素子載置部を囲繞するようにして取着され、半導
体素子の各電極が接続される配線層を有する枠状絶縁体
と、前記枠状絶縁体上に取着され、枠状絶縁体の内側を
気密に封止する蓋体とから成る半導体素子収納用パッケ
ージであって、前記枠状絶縁体はLi23を5〜30重
量%含有する屈服点が40〜800℃のリチウム珪酸ガ
ラスを20〜80体積%と、クオーツ、クリストバライ
ト、トリジマイト、エンスタタイト、フォルステライト
の少なくとも1種から成るフィラー成分を20〜80体
積%の割合で含む形成体を焼成して得られたクオーツ、
クリストバライト、トリジマイト、エンスタタイト、フ
ォルステライトの少なくとも1種の結晶相を含有する焼
結体から成り、かつ前記基体はタングステンと銅とから
成り、タングステンが40乃至70重量%、銅が30乃
至60重量%から成る中間層の上下両面にタングステン
が25乃至35重量%、銅が65乃至75重量%から成
る上下層を配した3層構造を有していることを特徴とす
るものである。
SUMMARY OF THE INVENTION According to the present invention, a base having a mounting portion on which a semiconductor element is mounted, and a semiconductor element mounting portion mounted on the base so as to surround the semiconductor element are mounted. A semiconductor element housing comprising a frame-shaped insulator having a wiring layer to which each electrode of the element is connected, and a lid attached to the frame-shaped insulator to hermetically seal the inside of the frame-shaped insulator In the package, the frame-shaped insulator contains 20 to 80% by volume of lithium silicate glass containing 5 to 30% by weight of Li 2 O 3 and having a yield point of 40 to 800 ° C., quartz, cristobalite, tridymite and enstatite. Quartz obtained by firing a formed body containing a filler component comprising at least one type of forsterite in a proportion of 20 to 80% by volume,
It is made of a sintered body containing at least one crystal phase of cristobalite, tridymite, enstatite, and forsterite, and the base body is made of tungsten and copper, and tungsten is 40 to 70% by weight and copper is 30 to 60% by weight. % Of tungsten and upper and lower layers of 65 to 75% by weight of copper are provided on both upper and lower surfaces of the intermediate layer.

【0010】また本発明は、上面に半導体素子が載置さ
れる載置部を有する基体と、前記基体上に半導体素子載
置部を囲繞するようにして取着され、半導体素子の各電
極が接続される配線層を有する枠状絶縁体と、前記枠状
絶縁体上に取着され、枠状絶縁体の内側を気密に封止す
る蓋体とから成る半導体素子収納用パッケージであっ
て、前記枠状絶縁体はLi23を5〜30重量%含有す
る屈服点が40〜800℃のリチウム珪酸ガラスを20
〜80体積%と、クオーツ、クリストバライト、トリジ
マイト、エンスタタイト、フォルステライトの少なくと
も1種から成るフィラー成分を20〜80体積%の割合
で含む形成体を焼成して得られたクオーツ、クリストバ
ライト、トリジマイト、エンスタタイト、フォルステラ
イトの少なくとも1種の結晶相を含有する焼結体から成
り、かつ前記基体はモリブデンと銅とから成り、モリブ
デンが35乃至70重量%、銅が30乃至65重量%か
ら成る中間層の上下両面にモリブデンが20乃至30重
量%、銅が70乃至80重量%から成る上下層を配した
3層構造を有していることを特徴とするものである。
Further, according to the present invention, a base having a mounting portion on which a semiconductor element is mounted is mounted on the upper surface, and the semiconductor element mounting portion is mounted on the base so as to surround each of the electrodes of the semiconductor element. A semiconductor element storage package comprising a frame-shaped insulator having a wiring layer to be connected, and a lid body attached to the frame-shaped insulator and hermetically sealing the inside of the frame-shaped insulator, The frame-shaped insulator is made of lithium silicate glass containing 5 to 30% by weight of Li 2 O 3 and having a yield point of 40 to 800 ° C.
~ 80% by volume, quartz, cristobalite, tridymite, enstatite, quartz obtained by firing a formed body containing a filler component consisting of at least one of 20-80% by volume, cristobalite, tridymite, A sintered body containing at least one crystal phase of enstatite or forsterite, and the base body is composed of molybdenum and copper, wherein the molybdenum is 35 to 70% by weight and the copper is 30 to 65% by weight. It is characterized by having a three-layer structure in which upper and lower layers of molybdenum of 20 to 30% by weight and copper of 70 to 80% by weight are arranged on both upper and lower surfaces of the layer.

【0011】本発明の半導体素子収納用パッケージによ
れば、枠状絶縁体をLi23を5〜30重量%含有する
屈服点が40〜800℃のリチウム珪酸ガラスを20〜
80体積%と、クオーツ、クリストバライト、トリジマ
イト、エンスタタイト、フォルステライトの少なくとも
1種から成るフィラー成分を20〜80体積%の割合で
含む形成体を焼成して得られたクオーツ、クリストバラ
イト、トリジマイト、エンスタタイト、フォルステライ
トの少なくとも1種の結晶相を含有する焼結体で形成
し、かかる焼結体の比誘電率が約5(室温、1MHz)
と低いことから枠状絶縁体に設けた配線層を伝わる電気
信号の伝搬速度を速いものとして信号の高速伝搬を要求
する半導体素子の収容が可能となる。
According to the package for accommodating semiconductor elements of the present invention, 20 to 20 lithium silicate glass containing 5 to 30% by weight of Li 2 O 3 as a frame-shaped insulator and having a yield point of 40 to 800 ° C. is used.
Quartz, cristobalite, tridymite, ensta obtained by firing a molded body containing 80% by volume and a filler component consisting of at least one of quartz, cristobalite, tridymite, enstatite and forsterite in a proportion of 20 to 80% by volume. It is formed of a sintered body containing at least one crystal phase of tight and forsterite, and the relative permittivity of the sintered body is about 5 (room temperature, 1 MHz).
Since it is low, it is possible to accommodate a semiconductor element which requires high-speed signal propagation by increasing the propagation speed of the electric signal transmitted through the wiring layer provided in the frame-shaped insulator.

【0012】また本発明の半導体素子収納用パッケージ
によれば、枠状絶縁体を構成する焼結体の焼成温度が8
50℃〜1100℃と低いことから枠状絶縁体と同時焼
成により形成される配線層を比電気抵抗が2.5μΩ・
cm(20℃)以下と低い銅や銀、金で形成することが
でき、その結果、配線層に電気信号を伝搬させた場合、
電気信号に大きな減衰が生じることはなく、電気信号を
正確、かつ確実に伝搬させることが可能となる。
Further, according to the package for accommodating semiconductor elements of the present invention, the firing temperature of the sintered body constituting the frame-shaped insulator is 8
Since the temperature is as low as 50 ° C to 1100 ° C, the wiring layer formed by co-firing with the frame-shaped insulator has a specific electric resistance of 2.5 μΩ.
It can be formed of copper, silver or gold as low as cm (20 ° C.) or lower, and as a result, when an electric signal is propagated to the wiring layer,
The electric signal will not be greatly attenuated, and the electric signal can be accurately and reliably propagated.

【0013】更に本発明の半導体素子収納用パッケージ
によれば、基体をタングステンが40乃至70重量%、
銅が30乃至60重量%から成る中間層の上下両面にタ
ングステンが25乃至35重量%、銅が65乃至75重
量%から成る上下層を配した3層構造、またはモリブデ
ンが35乃至70重量%、銅が30乃至65重量%から
成る中間層の上下両面にモリブデンが20乃至30重量
%、銅が70乃至80重量%から成る上下層を配した3
層構造となしたことから基体の半導体素子載置部である
上層の熱伝導率を300W/m・K以上の高いものと
し、基体上に載置される半導体素子が作動時に多量の熱
を発したとしてもその熱は基体の半導体素子載置部平面
方向に素早く広がらせるとともに基体の上層、中間層、
下層を順次介して外部に効率よく確実に放散させること
ができ、これによって半導体素子は常に適温となり、半
導体素子を長期間にわたり安定かつ正常に作動させるこ
とが可能となる。
Further, according to the package for accommodating a semiconductor device of the present invention, the base is 40 to 70% by weight of tungsten,
A three-layer structure in which an upper layer and a lower layer each containing 25 to 35% by weight of tungsten and 65 to 75% by weight of copper are arranged on the upper and lower surfaces of an intermediate layer of 30 to 60% by weight of copper, or 35 to 70% by weight of molybdenum, The upper and lower layers of molybdenum of 20 to 30% by weight and copper of 70 to 80% by weight are arranged on the upper and lower surfaces of the intermediate layer of copper of 30 to 65% by weight.
Due to the layered structure, the thermal conductivity of the upper layer, which is the semiconductor element mounting portion of the base, is set to a high value of 300 W / m · K or more, and the semiconductor element mounted on the base emits a large amount of heat during operation. Even so, the heat is quickly spread in the plane direction of the semiconductor element mounting portion of the base, and the upper layer, intermediate layer,
It is possible to efficiently and reliably dissipate the light to the outside through the lower layer in order, whereby the semiconductor element is always kept at an appropriate temperature, and the semiconductor element can be stably and normally operated for a long period of time.

【0014】また更に本発明の半導体素子収納用パッケ
ージによれば、基体をタングステンが40乃至70重量
%、銅が30乃至60重量%から成る中間層の上下両面
にタングステンが25乃至35重量%、銅が65乃至7
5重量%から成る上下層を配した3層構造、またはモリ
ブデンが35乃至70重量%、銅が30乃至65重量%
から成る中間層の上下両面にモリブデンが20乃至30
重量%、銅が70乃至80重量%から成る上下層を配し
た3層構造となし、線熱膨張係数が小さい中間層を線熱
膨張係数の大きい上下層で挟み込むことにより基体全体
の線熱膨張係数を枠状絶縁体の線熱膨張係数(8〜12
ppm/℃)に近似させることができ、その結果、基体
上に枠状絶縁体を取着させる際や半導体素子が作動した
際等において基体と枠状絶縁体の両者に熱が作用したと
しても基体と枠状絶縁体との間には両者の線熱膨張係数
の相違に起因する大きな熱応力が発生することはなく、
これによって半導体素子を収納する空所の気密封止が常
に完全となり、半導体素子を安定かつ正常に作動させる
ことが可能となる。
Further, according to the package for accommodating a semiconductor element of the present invention, the substrate has an intermediate layer of 40 to 70% by weight of tungsten and 30 to 60% by weight of copper, and 25 to 35% by weight of tungsten on the upper and lower surfaces of the intermediate layer. 65 to 7 copper
Three-layer structure consisting of upper and lower layers consisting of 5% by weight, or 35 to 70% by weight of molybdenum and 30 to 65% by weight of copper
20 to 30 molybdenum is formed on the upper and lower surfaces of the intermediate layer composed of
It has a three-layer structure in which upper and lower layers composed of 70% by weight of copper and 70 to 80% by weight of copper are arranged. An intermediate layer having a small coefficient of linear thermal expansion is sandwiched by upper and lower layers having a large coefficient of linear thermal expansion to linearly expand the entire substrate. The coefficient is the coefficient of linear thermal expansion of the frame-shaped insulator (8-12
ppm / ° C), and as a result, even when heat is applied to both the base and the frame-shaped insulator when the frame-shaped insulator is attached to the base or when the semiconductor element is activated, etc. Large thermal stress due to the difference in linear thermal expansion coefficient between the base and the frame-shaped insulator does not occur,
As a result, the airtight sealing of the space for accommodating the semiconductor element is always perfect, and the semiconductor element can be operated stably and normally.

【0015】[0015]

【発明の実施の形態】次に、本発明を添付図面に示す実
施例に基づき詳細に説明する。図1は本発明の半導体素
子収納用パッケージの一実施例を示す断面図であり、図
1において、1は基体、2は枠状絶縁体、3は蓋体であ
る。この基体1と枠状絶縁体2と蓋体3とにより内部に
半導体素子4を気密に収容する容器5が構成される。
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will now be described in detail with reference to the embodiments shown in the accompanying drawings. FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention. In FIG. 1, 1 is a base, 2 is a frame-shaped insulator, and 3 is a lid. The base 1, the frame-shaped insulator 2 and the lid 3 constitute a container 5 that hermetically houses the semiconductor element 4 therein.

【0016】前記基体1はその上面に半導体素子4が載
置される載置部1aを有するとともに上面外周部に該基
体1の上面に設けた半導体素子4が載置される載置部1
aを囲繞するようにして枠状絶縁体2がロウ材やガラ
ス、樹脂等の接着剤を介して取着されている。
The base 1 has a mounting portion 1a on which the semiconductor element 4 is mounted, and the mounting portion 1 on which the semiconductor element 4 provided on the upper surface of the base 1 is mounted on the outer peripheral portion of the upper surface.
The frame-shaped insulator 2 is attached so as to surround a through an adhesive such as a brazing material, glass, or resin.

【0017】前記基体1は半導体素子4を支持する支持
部材として作用するとともに半導体素子4が作動時に発
する熱を良好に吸収するとともに大気中に効率よく放散
させ、半導体素子4を常に適温とする作用をなし、枠状
絶縁体2に囲まれた基体1の載置部1a上に半導体素子
4がガラス、樹脂、ロウ材等の接着剤を介して固定され
る。
The base 1 acts as a supporting member for supporting the semiconductor element 4, and also absorbs heat generated by the semiconductor element 4 during operation and dissipates it efficiently into the atmosphere to keep the semiconductor element 4 at an appropriate temperature. The semiconductor element 4 is fixed on the mounting portion 1a of the base 1 surrounded by the frame-shaped insulator 2 with an adhesive such as glass, resin, or brazing material.

【0018】なお前記基体1はタングステンと銅とから
成り、タングステン粉末を焼成して得られる焼結多孔体
の空孔内に溶融させた銅を含浸させることによって製作
されている。
The substrate 1 is composed of tungsten and copper, and is manufactured by impregnating molten copper into the pores of a sintered porous body obtained by firing tungsten powder.

【0019】また前記基体1の上面外周部には該基体1
の上面に設けた半導体素子4が載置される載置部1aを
囲繞するようにして枠状絶縁体2がロウ材やガラス、樹
脂等の接着剤を介して取着されており、基体1と枠状絶
縁体2とで半導体素子4を収容するための空所が内部に
形成される。
Further, on the outer periphery of the upper surface of the base body 1, the base body 1 is provided.
The frame-shaped insulator 2 is attached via an adhesive such as a brazing material, glass, or resin so as to surround the mounting portion 1a on which the semiconductor element 4 mounted on the upper surface of the base 1 is mounted. With the frame-shaped insulator 2, a space for housing the semiconductor element 4 is formed inside.

【0020】前記基体1に取着される枠状絶縁体2はガ
ラス質の焼結体から成り、リチウム珪酸ガラスとクオー
ツ、クリストバライトなどのフィラー成分にアクリル樹
脂を主成分とするバインダー及び分散剤、可塑剤、有機
溶媒を加えて泥漿物を作るとともに該泥漿物をドクター
ブレード法やカレンダーロール法を採用することによっ
てグリーンシート(生シート)となし、しかる後、前記
グリーンシートに適当な打ち抜き加工を施すとともにこ
れを複数枚積層し、約850℃〜1100℃の温度で焼
成することによって製作される。
The frame-shaped insulator 2 attached to the substrate 1 is made of a glassy sintered body, and contains lithium silicate glass, a filler such as quartz and cristobalite, and a binder and a dispersant containing acrylic resin as a main component. A plastic sheet and an organic solvent are added to make a sludge, and the sludge is made into a green sheet (raw sheet) by adopting a doctor blade method or a calendar roll method, and then the green sheet is appropriately punched. It is manufactured by stacking a plurality of sheets and firing them at a temperature of about 850 ° C to 1100 ° C.

【0021】また前記枠状絶縁体2はその内周部から上
部にかけて導出する複数の配線層6が被着形成されてお
り、枠状絶縁体2の内周部に露出する配線層6の一端に
は半導体素子4の各電極がボンディングワイヤ7を介し
て電気的に接続され、また枠状絶縁体2の上面に導出さ
れた部位には外部電気回路と接続される外部リードピン
8が銀ロウ等のロウ材を介してロウ付け取着されてい
る。
A plurality of wiring layers 6 extending from the inner peripheral portion to the upper portion of the frame-shaped insulator 2 are adhered and formed, and one end of the wiring layer 6 exposed on the inner peripheral portion of the frame-shaped insulator 2 is attached. The electrodes of the semiconductor element 4 are electrically connected to each other via the bonding wires 7, and the external lead pins 8 connected to an external electric circuit are connected to an external electric circuit at a portion led out to the upper surface of the frame-shaped insulator 2. It is attached by brazing through the brazing material.

【0022】前記配線層6は半導体素子4の各電極を外
部電気回路に接続する際の導電路として作用し、銅、
銀、金等の金属粉末により形成されている。
The wiring layer 6 acts as a conductive path when connecting each electrode of the semiconductor element 4 to an external electric circuit, and copper,
It is formed of a metal powder such as silver or gold.

【0023】前記配線層6は銅、銀、金等の金属粉末に
適当な有機バインダー、溶剤等を添加混合して得られた
金属ペーストを枠状絶縁体2となるグリーンシートに予
め従来周知のスクリーン印刷法等の印刷法を用いること
により所定パターンに印刷塗布しておくことによって枠
状絶縁体2の内周部から上面にかけて被着形成される。
For the wiring layer 6, a metal paste obtained by adding and mixing an appropriate organic binder, a solvent, etc. to a metal powder such as copper, silver, gold or the like is formed on a green sheet which will be the frame-shaped insulator 2 in a conventionally well-known manner. By printing and applying a predetermined pattern by using a printing method such as a screen printing method, the frame-shaped insulator 2 is adhered and formed from the inner peripheral portion to the upper surface.

【0024】なお、前記配線層6は銅や銀からなる場
合、その露出表面に耐蝕性に優れる金属をメッキ法によ
り1μm〜20μmの厚みに被着させておくと、配線層
6の酸化腐蝕を有効に防止することができるとともに配
線層6とボンディングワイヤ7との接続及び配線層6へ
の外部リードピン8の取着を強固となすことができる。
従って、前記配線層6は銅や銀からなる場合、配線層6
の酸化腐蝕を防止し、配線層6とボンディングワイヤ7
及び外部リードピン8との取着を強固とするには配線層
6の露出表面に金等の耐蝕性に優れる金属を1μm〜2
0μmの厚みに被着させておくことが好ましい。
When the wiring layer 6 is made of copper or silver, if a metal having excellent corrosion resistance is deposited on the exposed surface to a thickness of 1 μm to 20 μm by a plating method, the wiring layer 6 will be oxidized and corroded. This can be effectively prevented, and the connection between the wiring layer 6 and the bonding wire 7 and the attachment of the external lead pin 8 to the wiring layer 6 can be strengthened.
Therefore, when the wiring layer 6 is made of copper or silver,
To prevent oxidative corrosion of the wiring layer 6 and the bonding wire 7
In order to strengthen the attachment to the external lead pin 8, a metal having excellent corrosion resistance such as gold is used on the exposed surface of the wiring layer 6 in a range of 1 μm to 2 μm.
It is preferable to deposit it to a thickness of 0 μm.

【0025】また前記枠状絶縁体2に被着した配線層6
にロウ付けされる外部リードピン8は鉄−ニッケル−コ
バルト合金や鉄−ニッケル合金等の金属材料から成り、
半導体素子4の各電極を外部電気回路に電気的に接続す
る作用をなす。
The wiring layer 6 attached to the frame-shaped insulator 2
The external lead pin 8 brazed to is made of a metal material such as an iron-nickel-cobalt alloy or an iron-nickel alloy,
It serves to electrically connect the respective electrodes of the semiconductor element 4 to an external electric circuit.

【0026】前記外部リードピン8は、例えば、鉄−ニ
ッケル−コバルト合金等の金属から成るインゴット
(塊)に圧延加工法や打ち抜き加工法等、従来周知の金
属加工法を施すことによって所定形状に形成される。
The external lead pin 8 is formed in a predetermined shape by subjecting an ingot (lump) made of a metal such as an iron-nickel-cobalt alloy to a conventionally known metal working method such as a rolling working method or a punching working method. To be done.

【0027】本発明においては、枠状絶縁体2をLi2
3を5〜30重量%含有する屈服点が40〜800℃
のリチウム珪酸ガラスを20〜80体積%と、クオー
ツ、クリストバライト、トリジマイト、エンスタタイ
ト、フォルステライトの少なくとも1種から成るフィラ
ー成分を20〜80体積%の割合で含む形成体を焼成し
て得られたクオーツ、クリストバライト、トリジマイ
ト、エンスタタイト、フォルステライトの少なくとも1
種の結晶相を含有する焼結体で形成しておくことが重要
である。
In the present invention, the frame-shaped insulator 2 is replaced with Li 2
Yield point of O 3 and containing 5 to 30 wt% is 40 to 800 ° C.
Obtained by firing a formed body containing 20 to 80% by volume of the lithium silicate glass of 20 to 80% by volume and a filler component containing at least one of quartz, cristobalite, tridymite, enstatite and forsterite in a proportion of 20 to 80% by volume. At least one of quartz, cristobalite, tridymite, enstatite and forsterite
It is important to form the sintered body containing the seed crystal phase.

【0028】前記枠状絶縁体2をLi23を5〜30重
量%含有する屈服点が40〜800℃のリチウム珪酸ガ
ラスを20〜80体積%と、クオーツ、クリストバライ
ト、トリジマイト、エンスタタイト、フォルステライト
の少なくとも1種から成るフィラー成分を20〜80体
積%の割合で含む形成体を焼成して得られたクオーツ、
クリストバライト、トリジマイト、エンスタタイト、フ
ォルステライトの少なくとも1種の結晶相を含有する焼
結体で形成しておくと、枠状絶縁体2の比誘電率が約5
(室温、1MHz)と低い値になり、その結果、枠状絶
縁体2に設けた配線層6を伝わる電気信号の伝搬速度を
速いものとして信号の高速伝搬を要求する半導体素子の
収容が可能となる。
20 to 80% by volume of lithium silicate glass containing 5 to 30% by weight of Li 2 O 3 and having a yield point of 40 to 800 ° C., the frame-shaped insulator 2, quartz, cristobalite, tridymite, enstatite, Quartz obtained by firing a formed body containing a filler component consisting of at least one kind of forsterite in a proportion of 20 to 80% by volume,
When the sintered body containing at least one crystal phase of cristobalite, tridymite, enstatite, and forsterite is formed, the frame-shaped insulator 2 has a relative dielectric constant of about 5
The value is as low as (room temperature, 1 MHz), and as a result, it is possible to accommodate a semiconductor element that requires high-speed signal propagation, assuming that the electrical signal propagating through the wiring layer 6 provided in the frame-shaped insulator 2 is fast. Become.

【0029】また上述の焼結体はその焼成温度が850
〜1100℃と低いことから枠状絶縁体2と同時焼成に
より形成される配線層6を比抵抗が2.5Ω・cm(2
0℃)以下と低い銅や銀、金で形成することができ、そ
の結果、配線層6に電気信号を伝搬させた場合、電気信
号に大きな減衰が生じることはなく、電気信号を正確か
つ確実に伝搬させることが可能となる。
The sintering temperature of the above-mentioned sintered body is 850.
Since it is as low as ˜1100 ° C., the specific resistance of the wiring layer 6 formed by co-firing with the frame-shaped insulator 2 is 2.5 Ω · cm (2
It can be formed of copper, silver, or gold that is as low as 0 ° C. or less, and as a result, when an electric signal is propagated to the wiring layer 6, the electric signal is not significantly attenuated, and the electric signal is accurate and reliable. Can be propagated to.

【0030】前記枠状絶縁体2はLi23を5〜30重
量%含有する屈服点が40〜800℃のリチウム珪酸ガ
ラスを20〜80体積%と、クオーツ、クリストバライ
ト、トリジマイト、エンスタタイト、フォルステライト
の少なくとも1種から成るフィラー成分を20〜80体
積%の割合で含む形成体を850〜1100℃の温度で
焼成し、フィラー成分であるクオーツ、クリストバライ
ト、トリジマイト、エンスタタイト、フォルステライト
の結晶相をそのまま生成させる、或いはリチウム珪酸ガ
ラスのシリカとフォルステライトとを反応させてエンス
タタイトの結晶相を生成させた焼結体となすことによっ
て製作される。
The frame-shaped insulator 2 contains 20 to 80% by volume of lithium silicate glass containing 5 to 30% by weight of Li 2 O 3 and having a yield point of 40 to 800 ° C., quartz, cristobalite, tridymite, enstatite, Crystals of quartz, cristobalite, tridymite, enstatite, and forsterite, which are filler components, by firing a formed body containing at least one filler component of forsterite in a proportion of 20 to 80% by volume at a temperature of 850 to 1100 ° C. It is manufactured by forming the phase as it is or by reacting silica of lithium silicate glass with forsterite to form a crystalline phase of enstatite.

【0031】なお、前記枠状絶縁体2を形成する焼結体
は、リチウム珪酸ガラスを20〜80体積%、フィラー
成分を20〜80体積%の割合とするのは、リチウム珪
酸ガラスの量が20体積%より少ない、言い換えればフ
ィラー成分が80体積%より多いと液相焼結することが
できずに高温で焼成する必要があり、その場合、配線層
6を銅や銀、金等の融点が低い金属材料で形成しようと
してもかかる金属材料は融点が低いことから焼成時に溶
融してしまって配線層6を枠状絶縁体2と同時焼成によ
り形成することができなくなり、またリチウム珪酸ガラ
スの量が80体積%を超える、言い換えればフィラー成
分が80体積%より少ないと焼結体の特性がリチウム珪
酸ガラスの特性に大きく依存し、材料特性の制御が困難
となるとともに焼結開始温度が低くなるため配線層6と
の同時焼成が困難となってしまうためである。
The proportion of the lithium silicate glass in the sintered body forming the frame-shaped insulator 2 is 20 to 80% by volume of the lithium silicate glass and 20 to 80% by volume of the filler component. If it is less than 20% by volume, in other words, if the filler component is more than 80% by volume, liquid phase sintering cannot be performed and it is necessary to fire at a high temperature. In that case, the wiring layer 6 has a melting point of copper, silver, gold or the like. However, even if an attempt is made to form a metal material having a low thermal conductivity, such a metal material has a low melting point and thus melts during firing, making it impossible to form the wiring layer 6 together with the frame-shaped insulator 2 at the same time. If the amount exceeds 80% by volume, in other words if the filler component is less than 80% by volume, the properties of the sintered body greatly depend on the properties of the lithium silicate glass, making it difficult to control the material properties and firing. Co-firing the wiring layer 6 for starting temperature is lower is because it becomes difficult.

【0032】また前記枠状絶縁体2に使用するLi23
を5〜30重量%、好適には5〜20重量%の割合で含
有するリチウム珪酸ガラスを用いることが重要であり、
このようなリチウム珪酸ガラスを用いることによりリチ
ウム珪酸を析出させることができる。なおLi23をの
含有量が5重量%より少ないと、焼結時にリチウム珪酸
の結晶の生成量が少なくなって高強度化が達成できず、
30重量%より多いと誘電正接が100×10-4を超え
るため配線基板用の枠状絶縁体2としての特性が劣化す
る。
Li 2 O 3 used for the frame-shaped insulator 2
It is important to use a lithium silicate glass containing 5 to 30% by weight, preferably 5 to 20% by weight,
Lithium silicic acid can be deposited by using such a lithium silicic acid glass. If the content of Li 2 O 3 is less than 5% by weight, the amount of lithium silicic acid crystals produced during sintering will be small and high strength cannot be achieved.
If the amount is more than 30% by weight, the dielectric loss tangent exceeds 100 × 10 −4, and the characteristics as the frame-shaped insulator 2 for the wiring board deteriorate.

【0033】また、この焼結体中にはPbを実質的に含
まないことが望ましい。これは、Pbが毒性を有するた
め、Pbを含有すると製造工程中での被毒を防止するた
めの格別な装置及び管理を必要とするために焼結体を安
価に製造することができないためである。なお、Pbが
不純物として不可避的に混入する場合を考慮すると、P
bの量は0.05重量%以下であることが望ましい。
It is desirable that the sintered body contains substantially no Pb. This is because Pb is toxic, and if Pb is contained, special equipment and management are required to prevent poisoning during the manufacturing process, and thus the sintered body cannot be manufactured at low cost. is there. Considering the case where Pb is inevitably mixed as an impurity, Pb
The amount of b is preferably 0.05% by weight or less.

【0034】更に前記焼結体の屈伏点が400〜800
℃、特に400〜650℃であることも、リチウム珪酸
ガラス及びフィラー成分から成る混合物を形成する場合
に添加する有機バインダー、溶剤の焼成時における効率
的な除去及び枠状絶縁体2と同時に焼成される配線層6
との焼成条件のマッチングを図るために重要である。屈
伏点が400℃より低いとリチウム珪酸ガラスが低い温
度で焼結を開始するために、例えば、銅や銀等の焼結開
始温度が600〜800℃の金属材料を用いた配線層6
との同時焼成ができず、また成形体の緻密化が低温で開
始するために有機バインダー、溶媒が分解揮散できなく
なって、焼結体中に残留し、焼結体の特性に悪影響を及
ぼす結果になるためである。一方、屈伏点が800℃よ
り高いと、リチウム珪酸ガラスを多くしないと焼結しに
くくなるためであり、高価なリチウム珪酸ガラスを大量
に必要とするために焼結体のコストを高めることにもな
るためである。上記特性を満足するリチウム珪酸ガラス
としては、例えば、SiO 2−Li2O−Al23、Si
2−Li2O−Al23−MgO−TiO2、SiO2
Li2O−Al23−MgO−Na2O−F、SiO2
Li2O−Al23−MgO−Na2O−ZnO、Si
2−Li2O−Al23−K2O−P25、SiO2−L
2O−Al23−K2O−P25−ZnO−Na23
SiO2−Li 2O−MgO、SiO2−Li2O−ZnO
等の組成物が挙げられ、このうち、SiO2はリチウム
珪酸を形成するために必須の成分であり、ガラス全量中
60〜85重量%の割合で存在し、SiO2とLi2Oと
の合量がガラス全量中65〜95重量%であることがリ
チウム珪酸結晶を析出させるうえで望ましい。
Further, the yield point of the sintered body is 400 to 800.
C., especially 400 to 650.degree. C., also indicates that lithium silicic acid
When forming a mixture of glass and filler components
Efficiency of organic binder and solvent added to
Layer 6 to be removed simultaneously and fired at the same time as the frame-shaped insulator 2
Is important for matching the firing conditions with. Bend
If the yield point is lower than 400 ° C, the temperature of the lithium silicate glass will be low.
In order to start sintering at
Wiring layer 6 using a metal material having an initial temperature of 600 to 800 ° C
Simultaneous baking with the
In order to start, the organic binder and solvent cannot decompose and volatilize
And remain in the sintered body, adversely affecting the characteristics of the sintered body.
This is because it will result in a loss. On the other hand, the yield point is 800 ℃
If it is too high, it will sinter unless lithium silicate glass is added too much.
This is because it gets harder, and a large amount of expensive lithium silicate glass is used.
It also does not increase the cost of the sintered body because
This is because Lithium silicate glass satisfying the above characteristics
As, for example, SiO 2-Li2O-Al2O3, Si
O2-Li2O-Al2O3-MgO-TiO2, SiO2
Li2O-Al2O3-MgO-Na2OF, SiO2
Li2O-Al2O3-MgO-Na2O-ZnO, Si
O2-Li2O-Al2O3-K2OP2OFive, SiO2-L
i2O-Al2O3-K2OP2OFive-ZnO-Na2O3,
SiO2-Li 2O-MgO, SiO2-Li2O-ZnO
And the like, among which, SiO2Is lithium
It is an essential component for forming silicic acid,
It is present in the proportion of 60-85% by weight,2And Li2O and
The total content of 65% to 95% by weight of the total glass is
It is desirable for precipitating crystals of thiium silicate.

【0035】一方、フィラー成分としては、クオーツ、
クリストバライト、トリジマイト、エンスタタイト、フ
ォルステライトの少なくとも1種を20〜80体積%、
特に30〜70体積%の割合で配合することが望まし
い。このようなフィラー成分の組み合わせにより焼結体
の焼結を促進することができ、中でもクオーツ/フォル
ステライト比が0.427以上であれば、比誘電率が高
いフォルステライトを焼結中に比誘電率の低いエンスタ
タイトに変えることができる。
On the other hand, as the filler component, quartz,
20 to 80% by volume of at least one of cristobalite, tridymite, enstatite and forsterite,
In particular, it is desirable to mix it in a proportion of 30 to 70% by volume. The combination of such filler components can promote the sintering of the sintered body. Above all, if the quartz / forsterite ratio is 0.427 or more, the relative permittivity during sintering of the forsterite having a high relative permittivity is increased. Can be changed to low enstatite.

【0036】上記のリチウム珪酸ガラス及びフィラー成
分は、リチウム珪酸ガラスの屈伏点に応じ、その量を適
宜調整することが望ましい。即ち、リチウム珪酸ガラス
の屈伏点が400〜600℃と低い場合、低温での焼結
性が高まるためフィラー成分の含有量は50〜80体積
%と比較的多く配合できる。これに対して、リチウム珪
酸ガラスの屈伏点が650〜800℃と高い場合、焼結
性が低下するためフィラー成分の含有量は20〜50体
積%と比較的少なく配合することが望ましい。このリチ
ウム珪酸ガラスの屈伏点は配線層6の焼成条件に合わせ
て制御することが望ましい。
The amounts of the above lithium silicate glass and the filler component are preferably adjusted appropriately according to the yield point of the lithium silicate glass. That is, when the deformation point of the lithium silicate glass is as low as 400 to 600 ° C., the sinterability at low temperature is enhanced, so that the content of the filler component can be relatively large, 50 to 80% by volume. On the other hand, when the deformation point of the lithium silicate glass is as high as 650 to 800 ° C., the sinterability is lowered, so that the content of the filler component is preferably relatively small at 20 to 50% by volume. It is desirable to control the sag point of this lithium silicate glass according to the firing conditions of the wiring layer 6.

【0037】更にリチウム珪酸ガラスは、フィラー成分
が無添加では収縮開始温度は700℃以下で、850℃
以上では溶融してしまい、配線層6を枠状絶縁体2に同
時焼成により被着形成することができない。しかし、フ
ィラー成分を20〜80体積%の割合で混合しておく
と、焼成温度を上昇させ、結晶の析出とフィラー成分を
液相焼結させるための液相を形成させることができる。
このフィラー成分の含有量の調整により枠状絶縁体2と
配線層6との同時焼成条件をマッチングさせることがで
きる。更に、原料コストを下げるために高価なリチウム
珪酸ガラスの含有量を減少させることができる。
Further, the lithium silicate glass has a shrinkage initiation temperature of 700 ° C. or lower at 850 ° C. without addition of a filler component.
In the above case, the wiring layer 6 is melted, and the wiring layer 6 cannot be adhered to the frame-shaped insulator 2 by simultaneous firing. However, if the filler component is mixed in a proportion of 20 to 80% by volume, the firing temperature can be increased and a liquid phase for crystal precipitation and liquid phase sintering of the filler component can be formed.
By adjusting the content of the filler component, the simultaneous firing conditions of the frame-shaped insulator 2 and the wiring layer 6 can be matched. Further, the content of expensive lithium silicate glass can be reduced in order to reduce the raw material cost.

【0038】例えば、配線層6として銅を主成分とする
金属材料により構成する場合、配線層6の焼成は600
〜1100℃で行われるため、同時焼成を行うには、リ
チウム珪酸ガラスの屈伏点は400〜650℃で、フィ
ラー成分の含有量は50〜80体積%であるのが好まし
い。また、このように高価なリチウム珪酸ガラスの配合
量を低減することにより焼結体のコストも低減できる。
For example, when the wiring layer 6 is made of a metal material containing copper as a main component, the wiring layer 6 is fired at 600.
Since it is performed at ˜1100 ° C., in order to perform the co-firing, it is preferable that the yield point of the lithium silicate glass is 400 to 650 ° C. and the content of the filler component is 50 to 80% by volume. Further, the cost of the sintered body can be reduced by reducing the compounding amount of the expensive lithium silicate glass.

【0039】このリチウム珪酸ガラスとフィラー成分と
の混合物は、適当な成形用の有機バインダー、溶剤等を
添加した後、所望の成形手段、例えばドクターブレード
法、圧延法、金型プレス法等によりシート状等の任意の
形状に成形後、焼成する。
The mixture of the lithium silicate glass and the filler component is added to a suitable molding organic binder, solvent, etc., and then formed into a sheet by a desired molding means such as a doctor blade method, a rolling method or a die pressing method. After forming into an arbitrary shape such as a shape, it is fired.

【0040】焼成に当たっては、まず、成形のために添
加した有機バインダー、溶剤成分を除去する。有機バイ
ンダー、溶剤成分の除去は通常700℃前後の大気雰囲
気中で行われるが、配線層6として銅を用いる場合に
は、水蒸気を含有する100〜700℃の窒素雰囲気中
で行われる。この時、成形体の収縮開始温度は700〜
850℃程度であることが望ましく、かかる収縮開始温
度がこれより低いと有機バインダー、溶剤成分の除去が
困難となるため、成形体中のリチウム珪酸ガラスの特
性、特に屈伏点を前述したように制御することが必要と
なる。
In firing, first, the organic binder and the solvent component added for molding are removed. The removal of the organic binder and the solvent component is usually performed in the atmosphere of about 700 ° C., but when copper is used for the wiring layer 6, it is performed in the nitrogen atmosphere of 100 to 700 ° C. containing water vapor. At this time, the shrinkage starting temperature of the molded body is 700 to
It is desirable that the temperature is about 850 ° C., and if the shrinkage initiation temperature is lower than this, it becomes difficult to remove the organic binder and the solvent component. Therefore, the characteristics of the lithium silicate glass in the molded body, especially the sag point are controlled as described above. Will be required.

【0041】焼成は850〜1100℃の酸化雰囲気中
で、あるいは配線層6と同時焼成する場合には非酸化性
雰囲気中で行われ、これにより相対密度90%以上まで
緻密化される。この時の焼成温度が850℃より低いと
緻密化することができず、一方1100℃を超えると配
線層6との同時焼成で配線層6が溶融してしまう。な
お、配線層6として銅を用いる場合には、850〜10
50℃の非酸化性雰囲気で行われる。
Firing is carried out in an oxidizing atmosphere at 850 to 1100 ° C., or in a non-oxidizing atmosphere when co-firing with the wiring layer 6, thereby densifying to a relative density of 90% or more. If the firing temperature at this time is lower than 850 ° C., the densification cannot be achieved. On the other hand, if the firing temperature is higher than 1100 ° C., the wiring layer 6 is melted by the simultaneous firing with the wiring layer 6. When copper is used as the wiring layer 6, 850 to 10
It is performed in a non-oxidizing atmosphere at 50 ° C.

【0042】また本発明においては、前記基体1をタン
グステンが40乃至70重量%、銅が30乃至60重量
%から成る中間層1cの上下両面にタングステンが25
乃至35重量%、銅が65乃至75重量%から成る上下
層1b、1dを配した3層構造としておくことが重要で
ある。
Further, in the present invention, the substrate 1 is made of tungsten 40 to 70% by weight and copper 30 to 60% by weight.
It is important to have a three-layer structure in which the upper and lower layers 1b and 1d composed of 35 to 35 wt% and 65 to 75 wt% of copper are arranged.

【0043】前記基体1をタングステンが40乃至70
重量%、銅が30乃至60重量%から成る中間層1cの
上下両面にタングステンが25乃至35重量%、銅が6
5乃至75重量%から成る上下層1b、1dを配した3
層構造としたことから基体1の半導体素子載置部1aで
ある上層1bの熱伝導率を300W/m・K以上の高い
ものとし、基体1上に載置される半導体素子4が作動時
に多量の熱を発したとしてもその熱は基体1の半導体素
子載置部1a平面方向に素早く広がらせるとともに基体
1の上層1b、中間層1c、下層1dを順次介して外部
に効率よく確実に放散させることができ、これによって
半導体素子4は常に適温となり、半導体素子4を長期間
にわたり安定かつ正常に作動させることが可能となる。
The substrate 1 is made of tungsten 40 to 70.
% Of tungsten and 25 to 35% by weight of tungsten and 6% of copper on the upper and lower surfaces of the intermediate layer 1c composed of 30 to 60% by weight of copper.
3 with upper and lower layers 1b, 1d consisting of 5 to 75% by weight
Due to the layered structure, the upper layer 1b, which is the semiconductor element mounting portion 1a of the base 1, has a high thermal conductivity of 300 W / m · K or more, and a large amount of semiconductor elements 4 mounted on the base 1 are activated during operation. Even if the heat is generated, the heat is quickly spread in the plane direction of the semiconductor element mounting portion 1a of the substrate 1 and efficiently and surely dissipated to the outside through the upper layer 1b, the intermediate layer 1c, and the lower layer 1d of the substrate 1 sequentially. As a result, the semiconductor element 4 is always kept at an appropriate temperature, and the semiconductor element 4 can be stably and normally operated for a long period of time.

【0044】また前記基体1はタングステンが40乃至
70重量%、銅が30乃至60重量%から成る中間層1
cの上下両面にタングステンが25乃至35重量%、銅
が65乃至75重量%から成る上下層1b、1dを配し
た3層構造となし、線熱膨張係数が小さい中間層1cを
線熱膨張係数の大きい上下層1b、1dで挟み込み基体
1全体の線熱膨張係数を枠状絶縁体2の線熱膨張係数
(8〜12ppm/℃)に近似させたことから、基体1
上に枠状絶縁体2を取着させる際や半導体素子4が作動
した際において基体1と枠状絶縁体2の両者に熱が作用
したとしても基体1と枠状絶縁体2との間には両者の線
熱膨張係数の相違に起因する大きな熱応力が発生するこ
とはなく、これによって半導体素子4を収納する空所の
気密封止が常に完全となり、半導体素子4を安定かつ正
常に作動させることが可能となる。
The substrate 1 is an intermediate layer 1 containing 40 to 70% by weight of tungsten and 30 to 60% by weight of copper.
It has a three-layer structure in which upper and lower layers 1b and 1d composed of 25 to 35% by weight of tungsten and 65 to 75% by weight of copper are arranged on both upper and lower sides of c, and the intermediate layer 1c having a small linear thermal expansion coefficient is formed. Since the linear thermal expansion coefficient of the entire substrate 1 sandwiched between the upper and lower layers 1b and 1d having a large size is approximated to the linear thermal expansion coefficient (8 to 12 ppm / ° C.) of the frame-shaped insulator 2, the substrate 1
Even if heat acts on both the base 1 and the frame-shaped insulator 2 when the frame-shaped insulator 2 is attached to the top or when the semiconductor element 4 is operated, the heat is applied between the base 1 and the frame-shaped insulator 2. Does not cause a large thermal stress due to the difference between the linear thermal expansion coefficients of the two, so that the space for housing the semiconductor element 4 is completely hermetically sealed, and the semiconductor element 4 operates stably and normally. It becomes possible.

【0045】なお前記基体1はその中間層1cのタング
ステンの量が40重量%未満の場合、或いは70重量%
を超えた場合、基体1の線熱膨張係数が枠状絶縁体2の
線熱膨張係数に対して大きく相違することとなり、その
結果、基体1に枠状絶縁体2を強固に取着させておくこ
とができなくなってしまう。従って、前記基体1の中間
層1cはそれを形成するタングステンの量は40乃至7
0重量%の範囲に特定される。
The substrate 1 has an intermediate layer 1c in which the amount of tungsten is less than 40% by weight, or 70% by weight.
If it exceeds, the coefficient of linear thermal expansion of the base body 1 greatly differs from the coefficient of linear thermal expansion of the frame-shaped insulator 2, and as a result, the frame-shaped insulator 2 is firmly attached to the base body 1. I can't keep it. Therefore, the amount of tungsten forming the intermediate layer 1c of the substrate 1 is 40 to 7.
It is specified in the range of 0% by weight.

【0046】また前記上下層1b、1dのタングステン
の量が25重量%未満となると、言い換えれば銅が75
重量%を超えると、基体1の線熱膨張係数が枠状絶縁体
2の線熱膨張係数に対して大きく相違して基体1に枠状
絶縁体2を強固に取着させておくことができなくなって
しまい、またタングステンの量が35重量%を超える
と、言い換えれば銅が65重量%未満となると上下層1
b、1dの熱伝導率を300W/m・K以上の高いもの
と成すことができず、半導体素子4が作動時に多量の熱
を発した場合、その熱を基体1を介して外部に完全に放
散させることができなくなり、その結果、半導体素子4
を高温として、半導体素子4に熱破壊を招来させたり、
特性にばらつきが生じ安定に作動させることができなく
なってしまう。従って、前記基体1の上下層1b、1d
はタングステンが25乃至35重量%、銅が65乃至7
5重量%に特定される。
If the amount of tungsten in the upper and lower layers 1b and 1d is less than 25% by weight, in other words, the amount of copper is 75%.
If it exceeds 5% by weight, the linear thermal expansion coefficient of the substrate 1 is greatly different from the linear thermal expansion coefficient of the frame-shaped insulator 2, so that the frame-shaped insulator 2 can be firmly attached to the substrate 1. When the amount of tungsten exceeds 35% by weight, in other words, when the amount of copper is less than 65% by weight, the upper and lower layers 1
When the thermal conductivity of b and 1d cannot be made as high as 300 W / m · K or more and the semiconductor element 4 generates a large amount of heat during operation, the heat is completely transmitted to the outside through the base body 1. Cannot be dissipated, and as a result, the semiconductor device 4
To a high temperature to cause thermal damage to the semiconductor element 4,
The characteristics vary, and it becomes impossible to operate stably. Therefore, the upper and lower layers 1b, 1d of the substrate 1
25 to 35% by weight of tungsten and 65 to 7 of copper
It is specified to be 5% by weight.

【0047】更に前記上下層1b、1dはその組成、厚
みを略同一に形成しておくと上層1bと中間層1cの間
に発生する応力と、下層1dと中間層1cとの間に発生
する応力が相殺されて基体1の平坦度が良好となり、そ
の結果、基体1に枠状絶縁体2を極めて強固に接合させ
ることができ、容器5の気密封止の信頼性をより確実な
ものとして、容器5内部に収納する半導体素子4の作動
信頼性を安定、確実なものと成すことができる。
Further, if the upper and lower layers 1b and 1d are formed to have substantially the same composition and thickness, the stress generated between the upper layer 1b and the intermediate layer 1c and the stress generated between the lower layer 1d and the intermediate layer 1c. The flatness of the substrate 1 is improved by offsetting the stress, and as a result, the frame-shaped insulator 2 can be bonded to the substrate 1 extremely firmly, and the reliability of the hermetic sealing of the container 5 is further ensured. The operation reliability of the semiconductor element 4 housed in the container 5 can be made stable and reliable.

【0048】また更に前記上下層1b、1dと中間層1
cの厚みは前記上下層1b、1dの厚みをX、中間層1
cの厚みをYとした場合、0.5Y≦X≦Yの範囲とし
ておくと基体1を介して半導体素子4の発する熱をより
良好に外部に放散することができる。前記上下層1b、
1dの厚みをX、中間層1cの厚みをYとした場合、
0.5Y>Xとなると300W/m・K以上の高熱伝導
率である上下層1b、1dが薄くなり半導体素子4の発
する熱を外部に効率よく放散することができなくなる危
険性があり、Y<Xとなると線熱膨張係数の大きな上下
層の基体1全体に及ぼす影響が大きくなり、基体1の線
熱膨張係数を前記枠状絶縁体2の線熱膨張係数と近似さ
せることが困難となる危険性があることから、前記上下
層1b、1dと中間層1cの厚みは前記上下層1b、1
dの厚みをX、中間層1cの厚みをYとした場合、0.
5Y≦X≦Yの範囲が望ましい。
Furthermore, the upper and lower layers 1b and 1d and the intermediate layer 1
c is the thickness of the upper and lower layers 1b and 1d, and X is the thickness of the intermediate layer 1.
When the thickness of c is Y, the heat generated by the semiconductor element 4 via the base 1 can be radiated to the outside better by setting the range of 0.5Y ≦ X ≦ Y. The upper and lower layers 1b,
When the thickness of 1d is X and the thickness of the intermediate layer 1c is Y,
When 0.5Y> X, the upper and lower layers 1b and 1d having a high thermal conductivity of 300 W / m · K or more become thin, and there is a risk that the heat generated by the semiconductor element 4 cannot be efficiently dissipated to the outside. When <X, the influence on the entire upper and lower base bodies 1 having a large linear thermal expansion coefficient becomes large, and it becomes difficult to approximate the linear thermal expansion coefficient of the base body 1 to the linear thermal expansion coefficient of the frame-shaped insulator 2. Since there is a risk, the thicknesses of the upper and lower layers 1b and 1d and the intermediate layer 1c are the same as the upper and lower layers 1b and 1d.
When the thickness of d is X and the thickness of the intermediate layer 1c is Y, 0.
The range of 5Y ≦ X ≦ Y is desirable.

【0049】なお前記3層構造の基体1は、中間層1c
となる所定量のタングステン焼結体に所定量の銅を含浸
させた所定厚みの板体と、上下層1b、1dとなる所定
量のタングステン焼結体に所定量の銅を含浸させた所定
厚みの板体とを準備し、前記中間層1cとなる板体の上
下を上下層となる板体で挟み込んだ後、銅の溶融温度
(1083℃)より20℃程度高い温度にて真空中もし
くは中性、還元雰囲気中で加圧しながら積層することに
よって製作される。
The substrate 1 having the three-layer structure is the intermediate layer 1c.
A plate body having a predetermined thickness obtained by impregnating a predetermined amount of tungsten sintered body with a predetermined amount of copper, and a predetermined thickness obtained by impregnating a predetermined amount of tungsten sintered body serving as the upper and lower layers 1b and 1d with a predetermined amount of copper. And the upper and lower plates of the intermediate layer 1c are sandwiched between the upper and lower plates, and then in a vacuum or in a medium at a temperature about 20 ° C. higher than the melting temperature of copper (1083 ° C.). It is manufactured by stacking under pressure in a reducing atmosphere.

【0050】かくして上述の半導体素子収納用パッケー
ジによれば、基体1の半導体素子載置部1a上に半導体
素子4をガラス、樹脂、ロウ材等の接着剤を介して接着
固定するとともに該半導体素子4の各電極をボンディン
グワイヤ7を介して所定の配線層6に接続させ、しかる
後、前記枠状絶縁体2の上面に蓋体3をガラス、樹脂、
ロウ材等から成る封止材を介して接合させ、基体1、枠
状絶縁体2及び蓋体3とから成る容器5内部に半導体素
子4を気密に収容することによって製品としての半導体
装置となる。
Thus, according to the above-mentioned package for accommodating semiconductor elements, the semiconductor element 4 is adhered and fixed on the semiconductor element mounting portion 1a of the base body 1 through an adhesive such as glass, resin, or brazing material, and the semiconductor element is mounted. Each electrode 4 is connected to a predetermined wiring layer 6 through a bonding wire 7, and then the lid 3 is attached to the upper surface of the frame-shaped insulator 2 with glass, resin,
A semiconductor device as a product is obtained by airtightly housing the semiconductor element 4 inside a container 5 made up of a base body 1, a frame-shaped insulator 2 and a lid body 3 by joining them through a sealing material made of a brazing material or the like. .

【0051】次に本発明の他の実施例について説明す
る。上述の半導体素子収納用パッケージでは基体1をタ
ングステンが40乃至70重量%、銅が30乃至60重
量%から成る中間層1bの上下両面にタングステンが2
5乃至35重量%、銅が65乃至75重量%から成る上
下層1b、1dを配した3層構造としたが、これをモリ
ブデンが35乃至70重量%、銅が30乃至65重量%
から成る中間層1cの上下両面にモリブデンが20乃至
30重量%、銅が70乃至80重量%から成る上下層1
b、1dを配した3層構造としてもよい。
Next, another embodiment of the present invention will be described. In the above-mentioned package for accommodating semiconductor elements, the base 1 is composed of 40 to 70% by weight of tungsten and 30 to 60% by weight of copper.
The upper and lower layers 1b and 1d are composed of 5 to 35% by weight and 65 to 75% by weight of copper, and have a three-layer structure.
An upper and lower layer 1 composed of 20 to 30% by weight of molybdenum and 70 to 80% by weight of copper on the upper and lower surfaces of the intermediate layer 1c.
A three-layer structure in which b and 1d are arranged may be used.

【0052】前記基体1をモリブデンが35乃至70重
量%、銅が30乃至65重量%から成る中間層1cの上
下両面にモリブデンが20乃至30重量%、銅が70乃
至80重量%から成る上下層1b、1dを配した3層構
造とした場合、基体1の半導体素子載置部1aである上
層1bの熱伝導率を300W/m・K以上の高いものと
し、基体1上に載置される半導体素子4が作動時に多量
の熱を発したとしてもその熱は基体1の半導体素子載置
部1a平面方向に素早く広がらせるとともに基体1の上
層1b、中間層1c、下層1dを順次介して外部に効率
よく確実に放散させることができ、これによって半導体
素子4は常に適温となり、半導体素子4を長期間にわた
り安定かつ正常に作動させることが可能となる。
The substrate 1 comprises an intermediate layer 1c composed of 35 to 70% by weight of molybdenum and 30 to 65% by weight of copper, and an upper and lower layer of 20 to 30% by weight of molybdenum and 70 to 80% by weight of copper on the upper and lower surfaces of the intermediate layer 1c. In the case of a three-layer structure in which 1b and 1d are arranged, the thermal conductivity of the upper layer 1b, which is the semiconductor element mounting portion 1a of the base 1, is set to a high value of 300 W / m · K or more, and the base 1 is mounted on the base 1. Even if the semiconductor element 4 generates a large amount of heat during operation, the heat is quickly spread in the plane direction of the semiconductor element mounting portion 1a of the base body 1 and the upper layer 1b, the intermediate layer 1c, and the lower layer 1d of the base body 1 are sequentially passed through the outside. Therefore, the semiconductor element 4 is always kept at an appropriate temperature, and the semiconductor element 4 can be stably and normally operated for a long period of time.

【0053】また前記モリブデンが35乃至70重量
%、銅が30乃至65重量%から成る中間層1cの上下
両面にモリブデンが20乃至30重量%、銅が70乃至
80重量%から成る上下層1b、1dを配した3層構造
の基体1は線熱膨張係数が小さい中間層1cを線熱膨張
係数の大きい上下層1b、1dで挟み込み基体1全体の
線熱膨張係数を枠状絶縁体2の線熱膨張係数(8〜12
ppm/℃)に近似させたことから基体1上に枠状絶縁
体2を取着させる際や半導体素子4が作動した際におい
て基体1と枠状絶縁体2の両者に熱が作用したとしても
基体1と枠状絶縁体2との間には両者の線熱膨張係数の
相違に起因する大きな熱応力が発生することはなく、こ
れによって半導体素子4を収納する空所の気密封止が常
に完全となり、半導体素子4を安定かつ正常に作動させ
ることが可能となる。
Further, the upper and lower layers 1b of molybdenum of 20 to 30% by weight and copper of 70 to 80% by weight are formed on the upper and lower surfaces of the intermediate layer 1c of 35 to 70% by weight of molybdenum and 30 to 65% by weight of copper. In the base 1 having a three-layer structure in which 1d is arranged, the intermediate layer 1c having a small linear thermal expansion coefficient is sandwiched by the upper and lower layers 1b and 1d having a large linear thermal expansion coefficient, and the linear thermal expansion coefficient of the entire base 1 is the line of the frame-shaped insulator 2. Coefficient of thermal expansion (8-12
Even if heat is applied to both the base body 1 and the frame-shaped insulator 2 when the frame-shaped insulator 2 is attached to the base body 1 or when the semiconductor element 4 is operated, it is approximated to (ppm / ° C.). No large thermal stress is generated between the base 1 and the frame-shaped insulator 2 due to the difference in linear thermal expansion coefficient between them, so that the space for accommodating the semiconductor element 4 is always hermetically sealed. It becomes complete, and the semiconductor element 4 can be stably and normally operated.

【0054】なお前記基体1はその中間層1cのモリブ
デンの量が35重量%未満の場合、或いは70重量%を
超えた場合、基体1の線熱膨張係数が枠状絶縁体2の線
熱膨張係数に対して大きく相違することとなり、その結
果、基体1に枠状絶縁体2を強固に取着させておくこと
ができなくなってしまう。従って、前記基体1の中間層
1cはそれを形成するモリブデンの量は35乃至70重
量%の範囲に特定される。
When the amount of molybdenum in the intermediate layer 1c of the substrate 1 is less than 35% by weight or exceeds 70% by weight, the coefficient of linear thermal expansion of the substrate 1 is the linear thermal expansion of the frame-shaped insulator 2. This greatly differs from the coefficient, and as a result, the frame-shaped insulator 2 cannot be firmly attached to the base body 1. Therefore, the amount of molybdenum forming the intermediate layer 1c of the substrate 1 is specified in the range of 35 to 70% by weight.

【0055】また前記上下層1b、1dのモリブデンの
量が20重量%未満となると、言い換えれば銅が80重
量%を超えると、基体1の線熱膨張係数が枠状絶縁体2
の線熱膨張係数に対して大きく相違して、基体1に枠状
絶縁体2を強固に取着させておくことができなくなって
しまい、またモリブデンの量が30重量%を超えると、
言い換えれば銅が70重量%未満となると上下層1b、
1dの熱伝導率を300W/m・K以上の高いものと成
すことができず、半導体素子4が作動時に多量の熱を発
した場合、その熱を基体1を介して外部に完全に放散さ
せることができなくなり、その結果、半導体素子4を高
温として、半導体素子4に熱破壊を招来させたり、特性
にばらつきが生じ安定に作動させることができなくなっ
てしまう。従って、前記基体1の上下層1b、1dはモ
リブデンが20乃至30重量%、銅が70乃至80重量
%に特定される。
When the amount of molybdenum in the upper and lower layers 1b and 1d is less than 20% by weight, in other words, when the amount of copper exceeds 80% by weight, the coefficient of linear thermal expansion of the substrate 1 is the frame-shaped insulator 2.
When the amount of molybdenum exceeds 30% by weight, the frame-shaped insulator 2 cannot be firmly attached to the base body 1 due to a large difference with respect to the linear thermal expansion coefficient.
In other words, when the copper content is less than 70% by weight, the upper and lower layers 1b,
When the thermal conductivity of 1d cannot be made as high as 300 W / m · K or more and the semiconductor element 4 emits a large amount of heat during operation, the heat is completely dissipated to the outside through the substrate 1. As a result, the semiconductor element 4 is heated to a high temperature, causing thermal damage to the semiconductor element 4 or variation in characteristics, which makes it impossible to operate the semiconductor element 4 stably. Therefore, the upper and lower layers 1b and 1d of the substrate 1 are specified to have molybdenum of 20 to 30% by weight and copper of 70 to 80% by weight.

【0056】更に前記上下層1b、1dはその組成、厚
みを略同一に形成しておくと上層1bと中間層1cの間
に発生する応力と、下層1dと中間層1cとの間に発生
する応力が相殺されて、基体1の平坦度が良好となり、
その結果、基体1に枠状絶縁体2を極めて強固に接合さ
せることができ、容器5の気密封止の信頼性をより確実
なものとして、容器5内部に収納する半導体素子4の作
動信頼性を安定、確実なものと成すことができる。
Further, if the upper and lower layers 1b and 1d are formed to have substantially the same composition and thickness, the stress generated between the upper layer 1b and the intermediate layer 1c and the stress generated between the lower layer 1d and the intermediate layer 1c. The stress is canceled out, and the flatness of the substrate 1 is improved,
As a result, the frame-shaped insulator 2 can be bonded to the base body 1 extremely firmly, and the reliability of the hermetic sealing of the container 5 is further ensured, and the operation reliability of the semiconductor element 4 housed inside the container 5 is improved. Can be stable and reliable.

【0057】また更に前記上下層1b、1dと中間層1
cの厚みは前記上下層1b、1dの厚みをX、中間層1
cの厚みをYとした場合、0.5Y≦X≦Yの範囲とし
ておくと基体1を介して半導体素子4の発する熱をより
良好に外部に放散することができる。前記上下層1b、
1dの厚みをX、中間層1cの厚みをYとした場合、
0.5Y>Xとなると300W/m・K以上の高熱伝導
率である上下層1b、1dが薄くなり半導体素子4の発
する熱を外部に効率よく放散することができなくなる危
険性があり、Y<Xとなると線熱膨張係数の大きな上下
層の基体1全体に及ぼす影響が大きくなり、基体1の線
熱膨張係数を前記枠状絶縁体2の線熱膨張係数と近似さ
せることが困難となる危険性があることから、前記上下
層1b、1dと中間層1cの厚みは前記上下層1b、1
dの厚みをX、中間層1cの厚みをYとした場合、0.
5Y≦X≦Yの範囲が望ましい。
Furthermore, the upper and lower layers 1b and 1d and the intermediate layer 1
c is the thickness of the upper and lower layers 1b and 1d, and X is the thickness of the intermediate layer 1.
When the thickness of c is Y, the heat generated by the semiconductor element 4 via the base 1 can be radiated to the outside better by setting the range of 0.5Y ≦ X ≦ Y. The upper and lower layers 1b,
When the thickness of 1d is X and the thickness of the intermediate layer 1c is Y,
When 0.5Y> X, the upper and lower layers 1b and 1d having a high thermal conductivity of 300 W / m · K or more become thin, and there is a risk that the heat generated by the semiconductor element 4 cannot be efficiently dissipated to the outside. When <X, the influence on the entire upper and lower base bodies 1 having a large linear thermal expansion coefficient becomes large, and it becomes difficult to approximate the linear thermal expansion coefficient of the base body 1 to the linear thermal expansion coefficient of the frame-shaped insulator 2. Since there is a risk, the thicknesses of the upper and lower layers 1b and 1d and the intermediate layer 1c are the same as the upper and lower layers 1b and 1d.
When the thickness of d is X and the thickness of the intermediate layer 1c is Y, 0.
The range of 5Y ≦ X ≦ Y is desirable.

【0058】なお前記3層構造の基体1は、中間層1c
となる所定量のモリブデン焼結体に所定量の銅を含浸さ
せた所定厚みの板体と、上下層1b、1dとなる所定量
のモリブデン焼結体に所定量の銅を含浸させた所定厚み
の板体とを準備し、前記中間層となる板体の上下を上下
層となる板体で挟み込んだ後、銅の溶融温度(1083
℃)より20℃程度高い温度にて真空中もしくは中性、
還元雰囲気中で加圧しながら積層することによって製作
される。
The substrate 1 having the three-layer structure is the intermediate layer 1c.
A plate body having a predetermined thickness obtained by impregnating a predetermined amount of molybdenum sintered body with a predetermined amount of copper and a predetermined thickness obtained by impregnating a predetermined amount of molybdenum sintered body serving as the upper and lower layers 1b and 1d with a predetermined amount of copper. And the upper and lower plates of the intermediate layer are sandwiched by the plate layers of the upper and lower layers, and then the melting temperature of copper (1083
In vacuum or at a temperature about 20 ° C higher than
It is manufactured by stacking under pressure in a reducing atmosphere.

【0059】また、本発明は上述の実施例に限定される
ものではなく、本発明の要旨を逸脱しない範囲であれば
種々の変更は可能である。
The present invention is not limited to the above-mentioned embodiments, but various modifications can be made without departing from the gist of the present invention.

【0060】[0060]

【発明の効果】本発明の半導体素子収納用パッケージに
よれば、枠状絶縁体をLi23を5〜30重量%含有す
る屈服点が40〜800℃のリチウム珪酸ガラスを20
〜80体積%と、クオーツ、クリストバライト、トリジ
マイト、エンスタタイト、フォルステライトの少なくと
も1種から成るフィラー成分を20〜80体積%の割合
で含む形成体を焼成して得られたクオーツ、クリストバ
ライト、トリジマイト、エンスタタイト、フォルステラ
イトの少なくとも1種の結晶相を含有する焼結体で形成
し、かかる焼結体の比誘電率が約5(室温、1MHz)
と低いことから枠状絶縁体に設けた配線層を伝わる電気
信号の伝搬速度を速いものとして信号の高速伝搬を要求
する半導体素子の収容が可能となる。
According to the package for accommodating a semiconductor element of the present invention, 20 lithium silicate glass containing a frame-shaped insulator in an amount of 5 to 30% by weight of Li 2 O 3 and having a yield point of 40 to 800 ° C. is used.
~ 80% by volume, quartz, cristobalite, tridymite, enstatite, quartz obtained by firing a formed body containing a filler component consisting of at least one of 20-80% by volume, cristobalite, tridymite, It is made of a sintered body containing at least one crystal phase of enstatite or forsterite, and the relative permittivity of the sintered body is about 5 (room temperature, 1 MHz).
Since it is low, it is possible to accommodate a semiconductor element which requires high-speed signal propagation by increasing the propagation speed of the electric signal transmitted through the wiring layer provided in the frame-shaped insulator.

【0061】また本発明の半導体素子収納用パッケージ
によれば、枠状絶縁体を構成する焼結体の焼成温度が8
50℃〜1100℃と低いことから枠状絶縁体と同時焼
成により形成される配線層を比電気抵抗が2.5μΩ・
cm(20℃)以下と低い銅や銀、金で形成することが
でき、その結果、配線層に電気信号を伝搬させた場合、
電気信号に大きな減衰が生じることはなく、電気信号を
正確、かつ確実に伝搬させることが可能となる。
Further, according to the package for housing a semiconductor element of the present invention, the firing temperature of the sintered body forming the frame-shaped insulator is 8
Since the temperature is as low as 50 ° C to 1100 ° C, the wiring layer formed by co-firing with the frame-shaped insulator has a specific electric resistance of 2.5 μΩ.
It can be formed of copper, silver or gold as low as cm (20 ° C.) or lower, and as a result, when an electric signal is propagated to the wiring layer,
The electric signal will not be greatly attenuated, and the electric signal can be accurately and reliably propagated.

【0062】更に本発明の半導体素子収納用パッケージ
によれば、基体をタングステンが40乃至70重量%、
銅が30乃至60重量%から成る中間層の上下両面にタ
ングステンが25乃至35重量%、銅が65乃至75重
量%から成る上下層を配した3層構造、またはモリブデ
ンが35乃至70重量%、銅が30乃至65重量%から
成る中間層の上下両面にモリブデンが20乃至30重量
%、銅が70乃至80重量%から成る上下層を配した3
層構造となしたことから基体の半導体素子載置部である
上層の熱伝導率を300W/m・K以上の高いものと
し、基体上に載置される半導体素子が作動時に多量の熱
を発したとしてもその熱は基体の半導体素子載置部平面
方向に素早く広がらせるとともに基体の上層、中間層、
下層を順次介して外部に効率よく確実に放散させること
ができ、これによって半導体素子は常に適温となり、半
導体素子を長期間にわたり安定かつ正常に作動させるこ
とが可能となる。
Further, according to the package for accommodating a semiconductor element of the present invention, the base is 40 to 70% by weight of tungsten,
A three-layer structure in which an upper layer and a lower layer each containing 25 to 35% by weight of tungsten and 65 to 75% by weight of copper are arranged on the upper and lower surfaces of an intermediate layer of 30 to 60% by weight of copper, or 35 to 70% by weight of molybdenum, The upper and lower layers of molybdenum of 20 to 30% by weight and copper of 70 to 80% by weight are arranged on the upper and lower surfaces of the intermediate layer of copper of 30 to 65% by weight.
Due to the layered structure, the thermal conductivity of the upper layer, which is the semiconductor element mounting portion of the base, is set to a high value of 300 W / m · K or more, and the semiconductor element mounted on the base emits a large amount of heat during operation. Even so, the heat is quickly spread in the plane direction of the semiconductor element mounting portion of the base, and the upper layer, intermediate layer,
It is possible to efficiently and reliably dissipate the light to the outside through the lower layer in order, whereby the semiconductor element is always kept at an appropriate temperature, and the semiconductor element can be stably and normally operated for a long period of time.

【0063】また更に本発明の半導体素子収納用パッケ
ージによれば、基体をタングステンが40乃至70重量
%、銅が30乃至60重量%から成る中間層の上下両面
にタングステンが25乃至35重量%、銅が65乃至7
5重量%から成る上下層を配した3層構造、またはモリ
ブデンが35乃至70重量%、銅が30乃至65重量%
から成る中間層の上下両面にモリブデンが20乃至30
重量%、銅が70乃至80重量%から成る上下層を配し
た3層構造となし、線熱膨張係数が小さい中間層を線熱
膨張係数の大きい上下層で挟み込むことにより基体全体
の線熱膨張係数を枠状絶縁体の線熱膨張係数(8ppm
/℃〜12ppm/℃)に近似させることができ、その
結果、基体上に枠状絶縁体を取着させる際や半導体素子
が作動した際等において基体と枠状絶縁体の両者に熱が
作用したとしても基体と枠状絶縁体との間には両者の線
熱膨張係数の相違に起因する大きな熱応力が発生するこ
とはなく、これによって半導体素子を収納する空所の気
密封止が常に完全となり、半導体素子を安定かつ正常に
作動させることが可能となる。
Further, according to the package for accommodating a semiconductor element of the present invention, the substrate has an intermediate layer consisting of 40 to 70% by weight of tungsten and 30 to 60% by weight of copper, and 25 to 35% by weight of tungsten on the upper and lower surfaces of the intermediate layer. 65 to 7 copper
Three-layer structure consisting of upper and lower layers consisting of 5% by weight, or 35 to 70% by weight of molybdenum and 30 to 65% by weight of copper
20 to 30 molybdenum is formed on the upper and lower surfaces of the intermediate layer composed of
It has a three-layer structure in which upper and lower layers composed of 70% by weight of copper and 70 to 80% by weight of copper are arranged. An intermediate layer having a small coefficient of linear thermal expansion is sandwiched by upper and lower layers having a large coefficient of linear thermal expansion to linearly expand the entire substrate. Coefficient of linear thermal expansion of frame-shaped insulator (8ppm
/ ° C to 12 ppm / ° C), and as a result, heat acts on both the substrate and the frame-shaped insulator when attaching the frame-shaped insulator to the substrate or when the semiconductor element is operated. Even in this case, a large thermal stress due to the difference in linear thermal expansion coefficient between the base body and the frame-shaped insulator does not occur, so that the space for housing the semiconductor element is always hermetically sealed. It becomes complete, and it becomes possible to operate the semiconductor element stably and normally.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体素子収納用パッケージの一実施
例を示す断面図である。
FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor element housing package of the present invention.

【符号の説明】[Explanation of symbols]

1・・・・・基体 1a・・・・載置部 1b・・・・上層 1c・・・・中間層 1d・・・・下層 2・・・・・枠状絶縁体 3・・・・・蓋体 4・・・・・半導体素子 5・・・・・容器 6・・・・・配線層 7・・・・・ボンディングワイヤ 8・・・・・外部リードピン 1 ... Base 1a ... ・ Mounting part 1b ... upper layer 1c ... Middle layer 1d ... Lower layer 2 ... Frame-shaped insulator 3 ... Lid 4 ... Semiconductor element 5 ... Container 6 ... Wiring layer 7 ... Bonding wire 8: External lead pin

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】上面に半導体素子が載置される載置部を有
する基体と、前記基体上に半導体素子載置部を囲繞する
ようにして取着され、半導体素子の各電極が接続される
配線層を有する枠状絶縁体と、前記枠状絶縁体上に取着
され、枠状絶縁体の内側を気密に封止する蓋体とから成
る半導体素子収納用パッケージであって、前記枠状絶縁
体はLi23を5〜30重量%含有する屈服点が40〜
800℃のリチウム珪酸ガラスを20〜80体積%と、
クオーツ、クリストバライト、トリジマイト、エンスタ
タイト、フォルステライトの少なくとも1種から成るフ
ィラー成分を20〜80体積%の割合で含む形成体を焼
成して得られたクオーツ、クリストバライト、トリジマ
イト、エンスタタイト、フォルステライトの少なくとも
1種の結晶相を含有する焼結体から成り、かつ前記基体
はタングステンと銅とから成り、タングステンが40乃
至70重量%、銅が30乃至60重量%から成る中間層
の上下両面にタングステンが25乃至35重量%、銅が
65乃至75重量%から成る上下層を配した3層構造を
有していることを特徴とする半導体素子収納用パッケー
ジ。
1. A base having a mounting portion on which a semiconductor element is mounted, and a semiconductor element mounting portion mounted on the base so as to surround the semiconductor element, and each electrode of the semiconductor element is connected. A package for accommodating a semiconductor element, comprising: a frame-shaped insulator having a wiring layer; and a lid attached to the frame-shaped insulator to hermetically seal the inside of the frame-shaped insulator. The insulator contains 5 to 30% by weight of Li 2 O 3 and has a yield point of 40 to
20-80% by volume of lithium silicate glass at 800 ° C,
Of quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing a filler component consisting of at least one of quartz, cristobalite, tridymite, enstatite and forsterite in a proportion of 20 to 80% by volume. A sintered body containing at least one crystal phase, wherein the substrate is made of tungsten and copper, and tungsten is formed on both upper and lower surfaces of an intermediate layer containing 40 to 70% by weight of tungsten and 30 to 60% by weight of copper. Is a 25 to 35 wt% copper and 65 to 75 wt% copper, and has a three-layer structure in which upper and lower layers are arranged.
【請求項2】上面に半導体素子が載置される載置部を有
する基体と、前記基体上に半導体素子載置部を囲繞する
ようにして取着され、半導体素子の各電極が接続される
配線層を有する枠状絶縁体と、前記枠状絶縁体上に取着
され、枠状絶縁体の内側を気密に封止する蓋体とから成
る半導体素子収納用パッケージであって、前記枠状絶縁
体はLi23を5〜30重量%含有する屈服点が40〜
800℃のリチウム珪酸ガラスを20〜80体積%と、
クオーツ、クリストバライト、トリジマイト、エンスタ
タイト、フォルステライトの少なくとも1種から成るフ
ィラー成分を20〜80体積%の割合で含む形成体を焼
成して得られたクオーツ、クリストバライト、トリジマ
イト、エンスタタイト、フォルステライトの少なくとも
1種の結晶相を含有する焼結体から成り、かつ前記基体
はモリブデンと銅とから成り、モリブデンが35乃至7
0重量%、銅が30乃至65重量%から成る中間層の上
下両面にモリブデンが20乃至30重量%、銅が70乃
至80重量%から成る上下層を配した3層構造を有して
いることを特徴とする半導体素子収納用パッケージ。
2. A base having a mounting portion on which a semiconductor element is mounted, and a semiconductor element mounting portion mounted on the base so as to surround the base, and each electrode of the semiconductor element is connected. A package for accommodating a semiconductor element, comprising: a frame-shaped insulator having a wiring layer; and a lid attached to the frame-shaped insulator to hermetically seal the inside of the frame-shaped insulator. The insulator contains 5 to 30% by weight of Li 2 O 3 and has a yield point of 40 to
20-80% by volume of lithium silicate glass at 800 ° C,
Of quartz, cristobalite, tridymite, enstatite, forsterite obtained by firing a formed body containing a filler component consisting of at least one of quartz, cristobalite, tridymite, enstatite and forsterite in a proportion of 20 to 80% by volume. A sintered body containing at least one crystal phase, and the base body contains molybdenum and copper;
It has a three-layer structure in which the upper and lower layers of molybdenum of 20 to 30% by weight and copper of 70 to 80% by weight are arranged on both upper and lower surfaces of the intermediate layer of 0% by weight and 30 to 65% by weight of copper. A package for semiconductor device storage characterized by.
JP2001287702A 2001-09-20 2001-09-20 Package for housing semiconductor device Pending JP2003095733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001287702A JP2003095733A (en) 2001-09-20 2001-09-20 Package for housing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001287702A JP2003095733A (en) 2001-09-20 2001-09-20 Package for housing semiconductor device

Publications (1)

Publication Number Publication Date
JP2003095733A true JP2003095733A (en) 2003-04-03

Family

ID=19110469

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001287702A Pending JP2003095733A (en) 2001-09-20 2001-09-20 Package for housing semiconductor device

Country Status (1)

Country Link
JP (1) JP2003095733A (en)

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