JP2003092388A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device including an MONOS non-volatile memory device. SOLUTION: This method for manufacturing a semiconductor device comprises a process for forming a first insulating layer, a first conductive layer, and a stopper layer on a semiconductor layer 10, a process for forming a mask insulating layer 150 on the first conductive layer in a logic circuit region 2000, a process for forming a conductive layer in the formation region of a word gate layer and a common contact part, and for forming the gate electrode, a process for carrying out the anisotropic etching of the second conductive layer, and for forming sidewall-like control gates 20 and 30 and a conductive layer 232 of a common contact part 200 in a memory region 1000, and a process for patterning the third conductive layer and the first conductive layer, and for forming a word gate 14 and a word line 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to manufacturing of a semiconductor device including a memory region in which a nonvolatile memory device having two charge storage regions for one word gate is arranged in an array, and a logic circuit region. Regarding the method.

[0002]

BACKGROUND ART As one type of non-volatile semiconductor memory device, a gate insulating layer between a channel region and a control gate is composed of a laminated body of a silicon oxide layer and a silicon nitride layer, MONOS (Metal Ox) in which charges are trapped in the silicon nitride layer
ide Nitride Oxide Semiconductor) type or SONO
There is a type called S (Silicon Oxide Nitride Oxide Silicon) type.

A device shown in FIG. 15 is known as a MONOS type nonvolatile semiconductor memory device (reference: Y.
Hayashi, et al, 2000 Symposium on VLSI Tech
nologyDigest of Technical Papers p. 122-
p. 123).

In this MONOS type memory cell 100, a word gate 14 is formed on a semiconductor substrate 10 via a first gate insulating layer 12. And the word gate 14
A sidewall-shaped first control gate 20 and a sidewall-shaped second control gate 30 are arranged on both sides of, respectively. A second gate insulating layer 22 exists between the bottom of the first control gate 20 and the semiconductor substrate 10, and an insulating layer 24 exists between the side surface of the first control gate 20 and the word gate 14. Similarly, the second gate insulating layer 22 exists between the bottom of the second control gate 30 and the semiconductor substrate 10, and the insulating layer 24 exists between the side surface of the second control gate 30 and the word gate 14. Exists. Then, the control gate 20 and the control gate 30 of the memory cells adjacent to each other face each other.
Impurity layers 16 and 18 which form a source region or a drain region are formed on the semiconductor substrate 10 between and.

As described above, one memory cell 100
Has two MONOS type memory elements on the side surface of the word gate 14. Further, these two MONOS type memory elements are controlled independently. Therefore, one memory cell 100 can store 2-bit information.

An object of the present invention is a method of manufacturing a semiconductor device including a MONOS type non-volatile memory device having two charge storage regions, such as a memory region including a MONOS type memory cell and a peripheral circuit of the memory. Another object of the present invention is to provide a method of forming a logic circuit region including a substrate on the same substrate.

[0007]

A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device including a memory region including a non-volatile memory device and a logic circuit region including peripheral circuits of the non-volatile memory device. The following steps are included in this order.

Forming a first insulating layer above the semiconductor layer; forming a first conductive layer above the first insulating layer; mask insulating above the first conductive layer in the logic circuit region. A step of forming a layer, a step of forming a stopper layer above the first conductive layer and the mask insulating layer, a step of selectively etching the stopper layer, the mask insulating layer and the first conductive layer, Forming a word gate layer in the memory region and forming a gate electrode of an insulated gate field effect transistor in the logic circuit region; forming an ONO film on the entire surface of the memory region and the logic circuit region A step of forming a second conductive layer above the ONO film, and anisotropically etching the second conductive layer to form at least both sides of the word gate layer in the memory region. A step of forming a sidewall-shaped control gate through the ONO film, a first impurity layer to be a source region or a drain region of the nonvolatile memory device, and a source region or a drain region of the insulated gate field effect transistor. Forming a second impurity layer to be a gate electrode, forming a sidewall insulating layer on at least both side surfaces of the gate electrode, and forming a silicide layer on the surface of the first impurity layer and the second impurity layer. A step of forming a second insulating layer on the entire surface of the memory area and the logic circuit area, a step of polishing the second insulating layer until the stopper layer is exposed, a step of removing the stopper layer, a memory area Patterning the word gate layer in to form a word gate of the non-volatile memory device in the memory region. Process.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. First, before describing the manufacturing method according to the embodiment of the present invention, first, a semiconductor device obtained by this manufacturing method will be described.

FIG. 1 is a plan view showing a layout of a memory area of a semiconductor device. FIG. 2 is a plan view showing a part of the semiconductor device according to the present embodiment. FIG. 3 shows FIG.
It is sectional drawing along the AA line of FIG.

The semiconductor device shown in FIGS. 1 to 3 is a MONOS type non-volatile memory device (hereinafter referred to as “memory cell”) 10.
It includes a memory area 1000 in which 0s are arranged in a plurality of rows and columns in a grid pattern to form a memory cell array, and a logic circuit area 2000 including a peripheral circuit of the memory.

(Device Structure) First, the layout of the memory area 1000 will be described with reference to FIG.

FIG. 1 shows a first block B1 which is a part of the memory area 1000 and a second block B2 which is adjacent to the first block B1. The element isolation region 30 is formed in a partial region between the first block B1 and the second block B2.
0 is formed. In each of the blocks B1 and B2, a plurality of word lines 50 (W
L) and a plurality of bit lines 60 extending in the Y direction (column direction)
(BL) and are provided. One word line 50 is
It is connected to a plurality of word gates 14 arranged in the X direction. The bit line 60 is composed of the impurity layers 16 and 18.

First and second control gates 20,
The conductive layer 40 that constitutes 30 is formed so as to surround the impurity layers 16 and 18. That is, the first and second control gates 20 and 30 extend in the Y direction, respectively, and a set of the first and second control gates 20 and 30 is provided.
One ends of the two are connected to each other by a conductive layer extending in the X direction. The other ends of the pair of first and second control gates 20 and 30 are both connected to one common contact portion 200. Therefore, each of the first and second control gates 20 and 30 has a function of a control gate of the memory cell and a function of a wiring connecting the control gates arranged in the Y direction.

The single memory cell 100 includes one word gate 14, first and second control gates 20 and 30 formed on both sides of the word gate 14, and outside the control gates 20 and 30. And includes the impurity layers 16 and 18 formed in the semiconductor substrate. The impurity layers 16 and 18 are shared by the memory cells 100 adjacent to each other.

Impurity layers 16 adjacent to each other in the Y direction, the impurity layer 16 formed in the block B1 and the impurity layer 16 formed in the block B2, are the impurity layers 400 for contact formed in the semiconductor substrate. Are electrically connected to each other by. This contact impurity layer 4
00 is formed on the side of the impurity layer 16 opposite to the common contact portion 200 of the control gate.

On the contact impurity layer 400,
A contact 350 is formed. The bit line 60 formed of the impurity layer 16 has the contact 350.
Are electrically connected to the upper wiring layer.

Similarly, the two impurity layers 18 adjacent to each other in the Y direction are electrically connected to each other by a contact impurity layer (not shown) on the side where the common contact portion 200 is not arranged.

As can be seen from FIG. 1, the planar layout of the plurality of common contact portions 200 in one block is such that the impurity layers 16 and the impurity layers 18 are alternately formed on different sides, and a zigzag arrangement is formed. Similarly, in one block, the planar layout of the plurality of contact impurity layers 400 is formed on the side where the impurity layers 16 and the impurity layers 18 are alternately different, and has a staggered arrangement.

Next, the planar structure and cross-sectional structure of the semiconductor device will be described with reference to FIGS.
At a position adjacent to the memory area 1000, for example, a logic circuit area 2000 forming a peripheral circuit of the memory is formed. Memory area 1000 and logic circuit area 20
00 is electrically isolated from the element isolation region 300. At least the memory cell 100 is formed in the memory region 1000. Logic circuit area 200
0 is an insulated gate field effect transistor (hereinafter, referred to as “MOS transistor”) that constitutes at least a logic circuit.
That is) 500 is formed.

First, the memory area 1000 will be described.

The memory cell 100 includes a word gate 14 formed above the semiconductor substrate 10 via a first gate insulating layer 12 and an impurity layer formed in the semiconductor substrate 10 to form a source region or a drain region. 16, 18
And side wall-shaped first and second control gates 20 and 30 formed along both sides of the word gate 14, respectively. In addition, the impurity layers 16 and 18
A silicide layer 92 is formed on the top.

The first control gate 20 is formed above the semiconductor substrate 10 via the second gate insulating layer 22 and is formed on one side surface of the word gate 14 via the side insulating layer 24. There is. Similarly, the second control gate 30 is provided above the semiconductor substrate 10 with the second control gate 30.
It is formed via the gate insulating layer 22 and is formed on the other side surface of the word gate 14 via the side insulating layer 24.

The second gate insulating layer 22 and the side insulating layer 24 are ONO films. Specifically, the second gate insulating layer 22 and the side insulating layer 24 are laminated films of a bottom silicon oxide layer (first silicon oxide layer), a silicon nitride layer, and a top silicon oxide layer (second silicon oxide layer). .

The first silicon oxide layer of the second gate insulating layer 22 forms a potential barrier between the channel region and the charge storage region. The silicon nitride layer of the second gate insulating layer 22 functions as a charge storage region that traps carriers (for example, electrons). The second silicon oxide layer of the second gate insulating layer 22 has a potential barrier between the control gate and the charge storage region.
er) is formed.

The side insulating layer 24 is the word gate 14.
And the control gates 20 and 30 are electrically separated from each other. In addition, the upper end of the side insulating layer 24 has the word gate 14 and the first and second control gates 20 and 3.
Control gate 2 to prevent short circuit with 0
It is located higher than the upper ends of 0 and 30 with respect to the semiconductor substrate 10.

Side insulating layer 24 and second gate insulating layer 22
And are formed in the same film forming process, and have the same layer structure.

Then, in the adjacent memory cells 100, a buried insulating layer 70 is formed between the adjacent first control gate 20 and second control gate 30. The embedded insulating layer 70 covers at least the control gates 20 and 30 so that they are not exposed. Specifically, the upper surface of the buried insulating layer 70 is
It is located above the upper end of the side insulating layer 24 with respect to the semiconductor substrate 10. By forming the buried insulating layer 70 in this way, the first and second control gates 20 and 30 are formed.
With this, the electrical isolation between the word gate 14 and the word line 50 can be performed more reliably.

In the common contact part 200, a conductive layer for supplying a predetermined potential to the control gates 20 and 30 is formed. The common contact part 200 includes a first contact insulating layer 212, a second contact insulating layer 210, a first contact conductive layer 214, and a second contact conductive layer 23.
2, a third contact insulating layer 252 and a third contact conductive layer 260.

The first contact insulating layer 212 is formed in the same process as the first gate insulating layer 12.

The second contact insulating layer 210 is formed in the same process as the second gate insulating layer 22 and the side insulating layer 24. Therefore, the second contact insulating layer 210 is composed of a laminated body of the first silicon oxide layer, the silicon nitride layer, and the second silicon oxide layer.

The first contact conductive layer 214 is formed in the same process as the word gate 14. The first contact conductive layer 214 is formed outside the second contact insulating layer 210.

The second contact conductive layer 232 is formed inside the second contact insulating layer 210. The second contact conductive layer 232 is formed so as to be continuous with the control gates 20 and 30 by the same process as the formation of the first and second control gates 20 and 30. Therefore, the second contact conductive layer 232 and the control gates 20 and 30 are made of the same material.

The third contact insulating layer 252 is formed inside the second contact conductive layer 232. The third contact insulating layer 252 is formed by the same process as the sidewall insulating layer 152.

The third contact conductive layer 260 is formed in the same process as the word line 50, and the first contact conductive layer 2 is formed.
14 and the second contact conductive layer 232.

In the logic circuit area 2000, M
The OS transistor 500 is formed. The MOS transistor 500 includes a gate electrode 142 formed above the semiconductor substrate 10 with a third gate insulating layer 122 interposed therebetween.
Impurity layers 162 and 182 forming a source region or a drain region formed in the semiconductor substrate 10 and sidewall insulating layers 152 formed along both side surfaces of the gate electrode 142 are included. Further, the impurity layer 16
A silicide layer 192 is formed on the upper surfaces of the layers 2 and 182. The mask insulating layer 1 is formed on the upper surface of the gate electrode 142.
50 are formed.

In the logic circuit area 2000, M
The OS transistor 500 is covered with the insulating layer 270. The insulating layer 270 is formed in the same process as the buried insulating layer 70.

Memory area 1000 and logic circuit area 2
2 and 3, a boundary portion 140c made of the same material as that of the word gate 14 and the gate electrode 142 is formed in the boundary region with the gate electrode 000. The boundary portion 140c is formed by the word gate 14 and the gate electrode 142.
It is formed in the same film forming process as that of. Also, the boundary portion 140c
Is formed above the element isolation region 300.

A sidewall-shaped conductive layer 20a made of the same material as that of the control gates 20 and 30 is formed on one side surface of the boundary portion 140c (on the side of the memory region 1000). The sidewall-shaped conductive layer 20a extends in the Y direction and is electrically connected to the adjacent control gate 30 via the common contact portion 200. The sidewall-shaped conductive layer 20a is not used as the control gate of the memory cell. However,
By electrically connecting the sidewall-shaped conductive layer 20a to the adjacent control gate 30, it is possible to make the electrical characteristics of the control gate 30 adjacent to the sidewall-shaped conductive layer 20a equal to the electrical characteristics of other control gates. it can.

On the other side surface of the boundary portion 140c (on the side of the logic circuit area 2000), the MOS transistor 50 is formed.
The sidewall-shaped insulating layer 152 formed by the same process as the formation of the sidewall insulating layer 152 of 0 is formed.

An interlayer insulating layer 72 is formed on the semiconductor substrate 10 on which the memory cell 100, the MOS transistor 500, etc. are formed. Then, the interlayer insulating layer 72
A contact hole that reaches the third contact conductive layer 260 of the common contact portion 200 is formed in, for example. A conductive layer 82 such as a tungsten plug or a copper plug is filled in the contact hole, and the conductive layer 82 is connected to the wiring layer 80 formed on the interlayer insulating layer 72.

(Method of Manufacturing Semiconductor Device) Next, a method of manufacturing the semiconductor device according to the present embodiment will be described with reference to FIGS. Each sectional view is taken along the line AA of FIG.
Corresponds to the part along the line. 4 to 14, parts that are substantially the same as the parts shown in FIGS. 1 to 3 are given the same reference numerals, and duplicate descriptions are omitted.

(1) As shown in FIG. 4, first, the element isolation region 300 is formed on the surface of the semiconductor substrate 10 by the trench isolation method. Then, a contact impurity layer 400 (see FIG. 1) is formed in the semiconductor substrate 10 by ion implantation.

Next, the insulating layer 1 is formed on the surface of the semiconductor substrate 10.
20, a gate layer 140 made of doped polysilicon is formed. Next, in the logic circuit region 2000, the mask insulating layer 150 is formed. Mask insulating layer 15
A known method can be used for forming and patterning 0. Then, in the memory region 1000 and the logic circuit region 2000, a stopper layer S100 in a later CMP process is formed.

As the stopper layer S100, for example, a silicon nitride layer can be used. Mask insulating layer 15
0 is a step of removing at least the stopper layer S100,
In addition, it is necessary to function as a mask for protecting the gate electrode of the logic circuit region 2000 in a later etching step of the conductive layer. Therefore, as the mask insulating layer 150, when a silicon nitride layer is used as the stopper layer S100, a material used for removing the silicon nitride layer, for example, a silicon oxide layer having resistance to hot phosphoric acid is used. You can

(2) Next, a resist layer (not shown) having a predetermined pattern is formed. Next, the stopper layer S100 is patterned using this resist layer as a mask. Then, the patterned stopper layer S10
The gate layer 140 is etched using 0 as a mask.
As shown in FIG. 5, in the memory region 1000, a word gate layer 140a to be a word gate is formed by later patterning, and in the logic circuit region 2000, the gate electrode 142 of the MOS transistor is formed.

That is, in this step, the memory area 10
00, the insulating layer 120 and the word gate layer 140
a and a stopper layer S100 are formed, and in the logic circuit region 2000, the insulating layer 120, the gate electrode 142, the mask insulating layer 150, and the stopper layer S are formed.
100 stacks are formed. Then, the memory area 10
00 and the logic circuit region 2000 form a boundary between the element isolation region 300 and the boundary portion 140c and the stopper layer S100.

FIG. 6 shows the memory region 10 after patterning.
00 shows a plan view of 00. In the memory region 1000, the opening 1 is formed in the stacked body of the gate layer 140 and the stopper layer S100.
60 and 180 are formed. Openings 160, 180
Substantially correspond to the regions where the impurity layers 16 and 18 are formed by the subsequent ion implantation. And in a later step,
A side insulating layer and a control gate are formed along the side surfaces of the openings 160 and 180.

(3) As shown in FIG. 7, the semiconductor substrate 10
An ONO film 220 is formed on the entire surface. ONO film 2
20 is formed by sequentially depositing a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer.
The first silicon oxide layer can be formed by using, for example, a thermal oxidation method or a CVD method. The silicon nitride layer can be formed by, for example, the CVD method. The second silicon oxide layer is formed by a CVD method such as a high temperature oxidation method (HT
O) can be used to form a film. It is preferable to densify each layer by performing an annealing treatment after forming each of these layers.

The ONO film 220 is formed on the control gates 20 and 3 by the subsequent patterning as shown in FIG.
Second gate insulating layer 22 and side insulating layer 2 for 0
4 and the second contact insulating layer 210.

(4) As shown in FIG. 8, a doped polysilicon layer 230 is entirely formed on the ONO film 220. Then, a resist layer R100 is formed in the region where the common contact portion is formed.

(5) As shown in FIG. 9, the doped polysilicon layer 230 (see FIG. 8) is wholly etched by anisotropic etching to form the first and second layers.
Conductive layer 40 constituting control gates 20 and 30
(See FIG. 1) and the second contact conductive layer 232 are formed. In this step, the sidewall-shaped conductive layers 20a and 30c are formed on the side surfaces of the boundary portion 140c on the memory region 1000 side and the logic circuit region 2000 side, respectively.
Is formed. Further, in this step, sidewall-shaped conductive layers 20c and 30c are formed on both side surfaces of the gate electrode 142 in the logic circuit region 2000, respectively.

That is, in this step, the memory area 10
Side wall-shaped control gates 20 and 30 are formed on the second gate insulating layer 22 along the side surfaces of the openings 160 and 180 (see FIG. 6) of No. 00 with the side insulating layer 24 interposed. . At this time, the upper ends of the control gates 20 and 30 are formed to be lower than the upper surface of the word gate layer 140a. Then, in the same step, a second contact conductive layer 232 that is continuous with the control gates 20 and 30 is formed in the portion masked with the resist layer R100 (see FIG. 8). Then, the resist layer R100 is removed.

(6) As shown in FIG. 9, an impurity layer 16 forming a source region or a drain region of the memory region 1000 is formed in the semiconductor substrate 10 by ion-implanting impurities such as N-type impurities over the entire surface. , 18 and the impurity layers 162 and 182 forming the source region or the drain region of the logic circuit region 2000 are formed.

(7) As shown in FIG. 10, the memory area 1
000 is masked by the resist layer R200, and the sidewall-shaped conductive layers 20c and 30c (see FIG. 9) in the logic circuit region 2000 are removed. Resist layer R
200 is the stopper layer S whose end is on the boundary 140c.
It is formed to be located on 100.

(8) As shown in FIG. 10, the resist layer R
In the logic circuit region 2000, extension layers 161 and 181 of the source region and the drain region are formed by doping N-type impurities with the memory region 1000 masked by 200. Then, the resist layer R200 is removed.

(9) As shown in FIG. 11, the memory area 1
000 and the logic circuit region 2000, an insulating layer 250 such as silicon oxide or silicon nitride oxide is entirely formed.

Next, as shown in FIG. 12, the insulating layer 25
0 (see FIG. 11) is entirely etched by anisotropic etching, so that the logic circuit region 2000
In, the sidewall insulating layers 152 are formed on both side surfaces of the gate electrode 142. Along with this, the boundary portion 140
The side wall insulating layer 152 is formed on the side surface of the logic circuit region 2000 side of the control gate 20,
The insulating layer 152a is formed on the conductive layer 20a and the conductive layer 20a, and the third contact insulating layer 252 is further formed.

(10) As shown in FIG. 12, the impurity layer 1
A silicide layer is formed on the upper surface of 6, 18, 162, 182. Then, a metal for forming a silicide is entirely deposited. The metal for forming the silicide is, for example, titanium or cobalt. After that, the impurity layers 16, 18, 16
The silicide layer 92 is formed on the upper surfaces of the impurity layers 16 and 18 and the silicide layer 192 is formed on the upper surfaces of the impurity layers 162 and 182 by performing a silicidation reaction on the metal formed on the impurity layers 162 and 182.

Therefore, the MOS transistor 500 in the logic circuit region 2000 is formed by this silicidation process.
The surface of the source region or the drain region is silicided in a self-aligned manner. Further, the surface of the source region or the drain region of the memory cell 100 in the memory region 1000 is silicided in a self-aligned manner by the same silicide process.

The MOS transistor 500 is formed through the above steps.

(11) Next, in the memory region 1000 and the logic circuit region 2000, an insulating layer 270 (see FIG. 13) of silicon oxide, silicon nitride oxide or the like is formed over the entire surface. The insulating layer 270 is formed so as to cover the stopper layer S100.

Next, as shown in FIG. 13, the insulating layer 27
0 is polished by CMP until the stopper layer S100 is exposed to flatten the insulating layer 270.

In the logic circuit area 2000, M
The OS transistor 500 is covered with the insulating layer 270. Then, the gate electrode 1 of the MOS transistor 500
A mask insulating layer 150 and a stopper layer S1 are formed on the layer 42.
00 are stacked.

Further, a buried insulating layer 70 is formed between the side insulating layers 24, 24 facing each other across the control gates 20, 30. By this step, the first and second control gates 20 and 30 are completely covered with the buried insulating layer 70, and the second contact conductive layer 232 is exposed.

(12) As shown in FIG. 14, the stopper layer S100 (see FIG. 13) is removed by, for example, hot phosphoric acid. Then, a conductive layer such as a doped polysilicon layer is formed in the memory region 1000 and the logic circuit region 2000. Then, a resist layer (not shown) is formed. By patterning the conductive layer using the resist layer as a mask, the word line 50 and the third contact conductive layer 260 are formed. Then, using the same resist layer as a mask, the gate layer 140a (see FIG. 13)
Etching is performed. By this etching, the gate layer 140a on which the word line 50 is not formed is removed. As a result, word gates 1 arranged in an array
4 can be formed. The removed region of the gate layer 140a corresponds to the region of the P-type impurity layer (element isolation impurity layer) 15 to be formed later (see FIG. 2).

In this etching process, the first and second
The conductive layer 40 forming the control gates 20 and 30 of
Since it is covered with the buried insulating layer 70, it remains without being etched. In addition, the MOS of the logic circuit area 2000
Since the transistor 500 is completely covered by the insulating layer 270, it is not affected by this etching.

Next, the semiconductor substrate 10 is entirely doped with P-type impurities. As a result, a P-type impurity layer (element isolation impurity layer) 15 (see FIG. 2) is formed in the region between the word gates 14 in the Y direction. The P-type impurity layer 15 ensures element isolation between the nonvolatile semiconductor memory devices 100.

(13) Next, after forming a first interlayer insulating layer, a contact hole is formed by a known method,
A conductive layer and a wiring layer in the contact hole can be formed. For example, as shown in FIG. 3, after forming a contact hole in the interlayer insulating layer 72, the conductive layer 82 and the wiring layer 80 connected to the common contact portion 200 are formed. In this step, the contact portion and the wiring layer can be formed in the logic circuit region 2000 as well.

Through the above steps, FIG. 1, FIG. 2 and FIG.
The semiconductor device shown in can be manufactured.

The advantages of this manufacturing method are as follows.

First, by the step (2), the word gate layer 140a which will later become the word gate 14 of the memory cell 100 and the gate electrode 142 of the MOS transistor 500 can be formed in the same step.

Second, the source or drain regions 16 and 1 of the memory cell 100 are processed by the process (6).
8 and the source region or drain region 162, 182 of the MOS transistor 500 can be formed in the same step.

Third, the source region or drain region 16 of the memory cell 100,
18 and the source or drain region 16 of the MOS transistor 500.
The silicide layer 192 formed on the layers 2, 182 can be formed in the same step.

Although one embodiment of the present invention has been described above, the present invention is not limited to this, and can take various forms within the scope of the gist of the present invention. For example, although a bulk semiconductor substrate is used as the semiconductor layer in the above embodiment, a semiconductor layer of an SOI substrate may be used.

[Brief description of drawings]

FIG. 1 is a plan view schematically showing a layout of a memory region of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a plan view schematically showing a main part of a semiconductor device according to an embodiment of the present invention.

3 is a cross-sectional view schematically showing a portion taken along the line AA of FIG.

FIG. 4 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3.

5 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3. FIG.

6 is a plan view showing a step of the method of manufacturing the semiconductor device shown in FIG.

FIG. 7 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3.

8 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3. FIG.

9 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3. FIG.

10 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3. FIG.

FIG. 11 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3.

FIG. 12 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3.

FIG. 13 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3.

FIG. 14 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device shown in FIGS. 1 to 3.

FIG. 15 is a cross-sectional view showing a known MONOS type memory cell.

[Explanation of symbols]

10 Semiconductor substrate 12 First gate insulating layer 14 word gate 16,18 Impurity layer 20 First control gate 22 Second gate insulating layer 24 Side insulation layer 30 Second control gate 50 word lines 60 bit line 70 Embedded insulation layer 72 Interlayer insulation layer 80 wiring layers 100 non-volatile memory device (memory cell) 120 insulating layer 122 third gate insulating layer 140 gate layer 140a word gate layer 142 gate electrode 150 mask insulation layer 160,180 openings 162,182 Impurity layer 200 Common contact part 210 Second contact insulating layer 212 First contact insulating layer 214 first contact conductive layer 220 ONO film 230 doped polysilicon layer 232 Second contact conductive layer 252 Third insulating layer 260 Third contact conductive layer 270 insulating layer 300 element isolation region 400 Contact impurity layer 500 MOS transistor S100 stopper layer R100, R200 resist layer 1000 memory area 2000 Logic circuit area

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Akihiko Ebina             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation (72) Inventor Shin Inoue             Seiko, 3-3-3 Yamato, Suwa City, Nagano Prefecture             -In Epson Corporation F term (reference) 5F083 EP18 EP22 EP28 EP30 EP44                       EP49 JA04 JA35 JA39 MA06                       MA16 PR40 PR42 PR43 PR45                       PR52 PR53 PR54 PR55 ZA05                       ZA06                 5F101 BA45 BB03 BB04 BB10 BD10                       BD22 BD27 BD35 BH14 BH19                       BH21

Claims (3)

[Claims] 1. A memory area including a non-volatile memory device,
A method of manufacturing a semiconductor device including a logic circuit region including a peripheral circuit of the nonvolatile memory device, the method including the following steps in this order. Forming a first insulating layer above the semiconductor layer; forming a first conductive layer above the first insulating layer; forming a mask insulating layer above the first conductive layer in the logic circuit region Forming a stopper layer above the first conductive layer and the mask insulating layer; selectively etching the stopper layer, the mask insulating layer, and the first conductive layer to form the memory region. Forming a word gate layer therein and forming a gate electrode of an insulated gate field effect transistor in the logic circuit region; turning on the entire surface of the memory region and the logic circuit region
Forming an O film, forming a second conductive layer above the ONO film, and anisotropically etching the second conductive layer so that at least both side surfaces of the word gate layer in the memory region are formed. Forming a sidewall-shaped control gate via the ONO film, a first impurity layer to be a source region or a drain region of the nonvolatile memory device, and a source region or a drain region of the insulated gate field effect transistor. A step of forming a second impurity layer that is formed of, a step of forming a sidewall insulating layer on at least both side surfaces of the gate electrode, a step of forming a silicide layer on a surface of the first impurity layer and the second impurity layer, A second surface is formed on the entire surface of the memory area and the logic circuit area.
Forming an insulating layer, polishing the second insulating layer until the stopper layer is exposed, removing the stopper layer, patterning the word gate layer in the memory region, and then in the memory region Forming a word gate of the non-volatile memory device. 2. A memory area including a non-volatile storage device,
A method of manufacturing a semiconductor device including a logic circuit region including a peripheral circuit of the nonvolatile memory device, the method including the following steps in this order. Forming a first insulating layer above the semiconductor layer; forming a first conductive layer above the first insulating layer; forming a mask insulating layer above the first conductive layer in the logic circuit region Forming a stopper layer above the first conductive layer and the mask insulating layer; selectively etching the stopper layer, the mask insulating layer, and the first conductive layer to form the memory region. Forming a word gate layer therein and forming a gate electrode of an insulated gate field effect transistor in the logic circuit region; turning on the entire surface of the memory region and the logic circuit region
Forming an O film, forming a second conductive layer above the ONO film, and anisotropically etching the second conductive layer to form the second conductive layer on both side surfaces of the word gate and the gate electrode. O
Leaving the second conductive layer via an NO film, a first impurity layer to be a source region or a drain region of the nonvolatile memory device, and a second impurity layer to be a source region or a drain region of the insulated gate field effect transistor. A step of forming an impurity layer, a step of removing the second conductive layer left on both side surfaces of the gate electrode, a step of forming a second layer on the entire surface of the memory region and the logic circuit region.
A step of forming an insulating layer, wherein the first impurity layer and the second impurity layer are partially exposed and the second conductive layer left in the memory region is not exposed. Removing the second insulating layer, forming a silicide layer on the surfaces of the first impurity layer and the second impurity layer, and forming a third layer on the entire surface of the memory region and the logic circuit region.
Forming an insulating layer, polishing the third insulating layer until the stopper layer is exposed, removing the stopper layer, patterning the word gate layer in the memory region, and then in the memory region Forming a word gate of the non-volatile memory device. 3. The process according to claim 1, wherein after forming the word gate, an element isolation impurity layer is further formed between the word gates adjacent to each other in the extending direction of the first impurity layer.