JP2003092287A - Ashing method - Google Patents

Ashing method

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Publication number
JP2003092287A
JP2003092287A JP2001284373A JP2001284373A JP2003092287A JP 2003092287 A JP2003092287 A JP 2003092287A JP 2001284373 A JP2001284373 A JP 2001284373A JP 2001284373 A JP2001284373 A JP 2001284373A JP 2003092287 A JP2003092287 A JP 2003092287A
Authority
JP
Japan
Prior art keywords
plasma
ashing
insulating film
interlayer insulating
msq
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001284373A
Other languages
Japanese (ja)
Inventor
Eiichi Soda
栄一 曽田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2001284373A priority Critical patent/JP2003092287A/en
Priority to KR1020020052352A priority patent/KR20030025174A/en
Priority to US10/237,053 priority patent/US20030054656A1/en
Priority to TW091120537A priority patent/TW559889B/en
Publication of JP2003092287A publication Critical patent/JP2003092287A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/42—Stripping or agents therefor
    • G03F7/427—Stripping or agents therefor using plasma means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1031—Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)

Abstract

PROBLEM TO BE SOLVED: To suppress damage to an interlayer insulating film when photoresist is etched by using N2 /H2 . SOLUTION: A reformed layer which has resistance to N2 /H2 plasma, is formed at an exposed part of the interlayer insulating film by using N2 plasma (process 1). The photoresist is removed by using N2 /H2 plasma (process 2).

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、層間絶縁膜上に形
成されたフォトレジストをプラズマを用いて除去するア
ッシング方法に関する。以下、窒素と水素との混合ガス
のプラズマを「Ｎ ２／Ｈ２プラズマ」、窒素ガスのプラ
ズマを「Ｎ２プラズマ」と表記する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is formed on an interlayer insulating film.
The removed photoresist is removed by using plasma.
Regarding the sashing method. Below, mixed gas of nitrogen and hydrogen
Plasma of "N Two/ HTwoPlasma ", nitrogen gas plastic
Zuma is "NTwoIt is written as "plasma".

【０００２】[0002]

【従来の技術】近年の半導体製造技術では、微細化技術
の進展によって、配線の間隔がますます狭くなってい
る。その結果、配線間容量が増加してしまうので、これ
を防ぐために低誘電率層間絶縁膜（ｌｏｗ−ｋ材料）が
注目されている。そのようなｌｏｗ−ｋ材料の一つとし
てＭＳＱが知られている。ＭＳＱとは、ＳｉＯ２のＳｉ
原子に結合する四つのＯ原子のうち一つをメチル基ＣＨ
３で置換した物質であり、（ＣＨ３−ＳｉＯ３／２）ｎ
と表記される。2. Description of the Related Art In recent semiconductor manufacturing technology, wiring intervals are becoming narrower due to the progress of miniaturization technology. As a result, the inter-wiring capacitance increases, and therefore, a low dielectric constant interlayer insulating film (low-k material) is receiving attention in order to prevent this. MSQ is known as one of such low-k materials. MSQ is SiO 2 Si
One of four O atoms bonded to an atom is a methyl group CH
3 is a substance substituted with 3 , and is (CH 3 —SiO 3/2 ) n
Is written.

【０００３】従来、フォトレジストをマスクにしてＭＳ
Ｑをエッチングした後に、フォトレジストをアッシング
するには、Ｏ２プラズマ又はＮ２／Ｈ２プラズマを用い
ていた。Conventionally, MS is used with a photoresist as a mask.
O 2 plasma or N 2 / H 2 plasma was used to ash the photoresist after etching Q.

【０００４】[0004]

【発明が解決しようとする課題】しかしながら、従来の
アッシング方法では、アッシング後のＭＳＱの側壁がオ
ーバーハング形状となるため、次工程のＣｕ埋め込みが
できなくなることがあった。これに加え、ＭＳＱの膜変
質によって誘電率が上昇するという問題もあった。However, in the conventional ashing method, the side wall of the MSQ after ashing has an overhang shape, and thus Cu filling in the next step may not be possible. In addition to this, there is also a problem that the dielectric constant increases due to the alteration of the MSQ film.

【０００５】その理由は、アッシングガスがＭＳＱ内に
拡散することにより、ＣＨ３基が脱離してＳｉＯ骨格が
収縮するので、オーバーハング形状となったり誘電率が
上昇したりするから、と考えられる。It is considered that the reason is that the ashing gas diffuses into the MSQ, the CH 3 group is desorbed and the SiO skeleton contracts, resulting in an overhang shape or an increase in the dielectric constant. .

【０００６】[0006]

【発明の目的】そこで、本発明の目的は、フォトレジス
トをＮ２／Ｈ２プラズマを用いて除去する際に、層間絶
縁膜の損傷を抑制できるアッシング方法を提供すること
にある。SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an ashing method capable of suppressing damage to an interlayer insulating film when removing a photoresist using N 2 / H 2 plasma.

【０００７】[0007]

【課題を解決するための手段】本発明は、一部が露出し
た層間絶縁膜の上に形成されたフォトレジストをＮ２／
Ｈ２プラズマを用いて除去するアッシング方法におい
て、予め、層間絶縁膜の露出部分に、Ｎ２／Ｈ２プラズ
マに耐え得る改質層をＮ２プラズマを用いて形成してお
くことを特徴とするものである（請求項１）。According to the present invention, a photoresist formed on a partially exposed interlayer insulating film is N 2 /
In the ashing process for removing with H 2 plasma, previously, the exposed portion of the interlayer insulating film, a modified layer that can withstand the N 2 / H 2 plasma, characterized in that to be formed with a N 2 plasma (Claim 1).

【０００８】層間絶縁膜としては、ＣＨ３基又はＨ原子
を有する材料、特にＭＳＱ、ＨＳＱ、ＭＨＳＱ等が適当
である（請求項２〜６）。また、フォトレジストをＮ２
／Ｈ ２プラズマを用いて除去する際に、層間絶縁膜を０
〜８０℃に保持してもよく（請求項６）、Ｎ２／Ｈ２の
圧力を１．３３〜１３．３Ｐａ（１０〜１００ｍＴｏｒ
ｒ）としてもよい（請求項７）。CH is used as the interlayer insulating film.ThreeGroup or H atom
Suitable materials with, especially MSQ, HSQ, MHSQ, etc.
(Claims 2 to 6). In addition, the photoresist is NTwo
/ H TwoWhen removing it using plasma, the interlayer insulating film is
It may be maintained at -80 ° C (claim 6), NTwo/ HTwoof
The pressure is 1.33 to 13.3 Pa (10 to 100 mTorr)
It may be r) (Claim 7).

【０００９】層間絶縁膜の一例としてＭＳＱについて説
明する。ＭＳＱは、半導体デバイスのＣｕ配線間に用い
られるｌｏｗ‐ｋ絶縁膜である。本発明は、フォトレジ
ストをマスクにしてＭＳＱをエッチングした後に、ＭＳ
Ｑに膜ダメージを与えることなく、フォトレジストをア
ッシングする方法である。すなわち最初に、ＭＳＱをＮ
２プラズマで処理することにより、ＣＨ３基がＣＮに置
換された薄い改質層を形成する。次に、フォトレジスト
をＮ２／Ｈ２プラズマでアッシングする。このとき、Ｎ
２／Ｈ２プラズマと改質層との反応性は低い。よって、
改質層がＭＳＱの保護膜となることにより、Ｎ２／Ｈ２
プラズマがＭＳＱ内部まで拡散しないので、膜ダメージ
の抑制が可能になる。MSQ will be described as an example of the interlayer insulating film. MSQ is a low-k insulating film used between Cu wirings of a semiconductor device. According to the present invention, after etching the MSQ using the photoresist as a mask,
This is a method of ashing the photoresist without damaging the film on Q. That is, first, MSQ is set to N
Treatment with 2 plasma forms a thin modified layer in which CH 3 groups are replaced by CN. Next, the photoresist is ashed with N 2 / H 2 plasma. At this time, N
The reactivity between the 2 / H 2 plasma and the modified layer is low. Therefore,
Since the modified layer serves as a protective film for MSQ, N 2 / H 2
Since plasma does not diffuse to the inside of the MSQ, it is possible to suppress film damage.

【００１０】[0010]

【発明の実施の形態】図１は、本発明に係るアッシング
方法の一実施形態を示す工程図である。被処理基板に
は、一部が露出した層間絶縁膜上に、フォトレジストが
形成されている。まず、層間絶縁膜の露出部分に、Ｎ２
／Ｈ２プラズマに耐え得る改質層をＮ２プラズマを用い
て形成する（工程１）。続いて、フォトレジストをＮ２
／Ｈ２プラズマを用いて除去する（工程２）。1 is a process diagram showing an embodiment of an ashing method according to the present invention. On the substrate to be processed, a photoresist is formed on the partially exposed interlayer insulating film. First, N 2 is formed on the exposed portion of the interlayer insulating film.
A modified layer capable of withstanding / H 2 plasma is formed using N 2 plasma (step 1). Subsequently, the photoresist is changed to N 2
/ H 2 plasma is used for removal (step 2).

【００１１】以下、層間絶縁膜がＭＳＱである場合につ
いて、具体的に説明する。本実施形態では、ＭＳＱの溝
及びビアエッチング後のフォトレジストアッシングを二
つの工程で行う。工程１ではＮ２プラズマを、工程２で
はＮ２／Ｈ２プラズマをそれぞれ用いる。The case where the interlayer insulating film is MSQ will be specifically described below. In the present embodiment, the photoresist ashing after the MSQ groove and via etching is performed in two steps. In step 1, N 2 plasma is used, and in step 2, N 2 / H 2 plasma is used.

【００１２】ＭＳＱのＣＨ３基はアッシング方法によっ
てダメージを受けることがある。そのＣＨ３基のダメー
ジ膜厚を観察するため、アッシング後にフォトレジスト
を塗布し、断面サンプルを作成し、フッ酸で側壁ダメー
ジ層を選択的に溶解する。本実施形態では、側壁ダメー
ジ膜厚がエッチング後と同等であったので、アッシング
によるダメージを抑制できることがわかる。The CH 3 group of MSQ may be damaged by the ashing method. In order to observe the damaged film thickness of the CH 3 group, a photoresist is applied after ashing, a cross-section sample is prepared, and the sidewall damage layer is selectively dissolved with hydrofluoric acid. In the present embodiment, the sidewall damage film thickness was the same as that after etching, so it can be seen that damage due to ashing can be suppressed.

【００１３】アッシング装置としては、ダウンフロー型
表面波プラズマアッシャー、ＩＣＰ（inductive couple
d plasma）型プラズマアッシャー、二周波ＲＩＥ（reac
tiveion etching）型エッチャー、ＩＣＰ型エッチャー
などいずれの装置を利用してもよい。また、バイアスパ
ワーを印加してもよい。As an ashing device, a downflow type surface wave plasma asher, an ICP (inductive couple)
d plasma) type plasma asher, dual frequency RIE (reac
Any device such as a tiveion etching type etcher or an ICP type etcher may be used. Also, bias power may be applied.

【００１４】[0014]

【実施例１】図２は、本発明に係るアッシング方法の実
施例１を示す断面図である。図３は、アッシング方法を
除き実施例１と同じ条件とした比較例を示す断面図であ
る。以下、この図面に基づき説明する。Embodiment 1 FIG. 2 is a sectional view showing Embodiment 1 of the ashing method according to the present invention. FIG. 3 is a cross-sectional view showing a comparative example under the same conditions as in Example 1 except for the ashing method. Hereinafter, description will be given with reference to this drawing.

【００１５】本実施例は、ミドルファースト方法でのデ
ュアルダマシン作成方法に本発明を適用したものであ
る。まず、配線であるＣｕ１上に、５０ｎｍのＳｉＣ
（ビアストッパー）２、３００ｎｍのＭＳＱ（ビア層間
膜）３、５０ｎｍのＳｉＣ（溝ストッパー）４を順次成
膜する。続いて、ＡＲＣ（anti reflective coat：反射
防止膜）５、ＫｒＦレジスト６を順次塗布し、０．１８
μｍ径のビアを露光及び現像する。続いて、ＫｒＦレジ
スト６をマスクとして、ＡＲＣ５及びＳｉＣ４をドライ
エッチングする。このエッチングには、二周波ＲＩＥエ
ッチャー及びＣＦ４、Ａｒ、Ｏ２ガスプラズマを用い
る。ＳｉＣ４のビアエッチング後、ＭＳＱ３の一部が露
出する（図２［１］）。続いて、ＫｒＦレジスト６及び
ＡＲＣ５をアッシングする。このとき、ＭＳＱ３の露出
部分にダメージを与えることなくアッシングする必要が
あるので、本発明に係るアッシング方法を用いる。In this embodiment, the present invention is applied to a dual damascene forming method by the middle first method. First, 50 nm of SiC is formed on the wiring Cu1.
(Via stopper) 2, MSQ (via interlayer film) 3 having a thickness of 300 nm, and SiC (groove stopper) 4 having a thickness of 50 nm are sequentially formed. Subsequently, an ARC (anti reflective coat) 5 and a KrF resist 6 are sequentially applied to form a 0.18 film.
The via having a diameter of μm is exposed and developed. Then, the ARC 5 and the SiC 4 are dry-etched using the KrF resist 6 as a mask. A dual-frequency RIE etcher and CF 4 , Ar, and O 2 gas plasma are used for this etching. After the via etching of SiC4, a part of MSQ3 is exposed (FIG. 2 [1]). Then, the KrF resist 6 and the ARC 5 are ashed. At this time, the ashing method according to the present invention is used because it is necessary to ash without damaging the exposed portion of the MSQ3.

【００１６】続いて、ＫｒＦレジスト６のアッシング後
に有機剥離液処理を行い、３００ｎｍのＭＳＱ７（溝層
間膜）、５０ｎｍのＳｉＣ８（ハードマスク）を順次成
膜する。続いて、ＡＲＣ９、ＫｒＦレジスト１０を順次
塗布し、Ｌ／Ｓ（line/space）＝０．１８μｍ／０．１
８μｍの溝を露光する。続いて、ＫｒＦレジスト１０を
マスクとして、ＡＲＣ９、ＳｉＣ８、ＭＳＱ７をドライ
エッチングする。ＡＲＣ９、ＳｉＣ８のエッチングガス
にはＣＦ４、Ａｒ、Ｏ２を用い、溝ＭＳＱ７のエッチン
グガスにはＣ４Ｆ８、Ａｒ、Ｎ２を用いる。溝ＭＳＱ７
のエッチングはＳｉＣ４のストッパーで止まるが、引き
続きビアＭＳＱ３をエッチングすることにより、図２
［２］のような構造となる。Subsequently, an organic stripping solution treatment is performed after the ashing of the KrF resist 6 to sequentially form a 300 nm MSQ7 (groove interlayer film) and a 50 nm SiC8 (hard mask). Subsequently, ARC9 and KrF resist 10 are sequentially applied, and L / S (line / space) = 0.18 μm / 0.1
The groove of 8 μm is exposed. Then, the ARC 9, SiC 8 and MSQ 7 are dry-etched using the KrF resist 10 as a mask. CF 4 , Ar, and O 2 are used as the etching gas for ARC9 and SiC8, and C 4 F 8 , Ar, and N 2 are used as the etching gas for the groove MSQ7. Groove MSQ7
Although the etching of Fig. 2 is stopped by the stopper of SiC4, by subsequently etching the via MSQ3,
The structure is as shown in [2].

【００１７】続いて、ＫｒＦレジスト６及びＡＲＣ５を
アッシングする。このとき、ＭＳＱ３，７の側壁が露出
していることから、これらにダメージを与えることなく
アッシングする必要があるので、本発明に係るアッシン
グ方法を用いる。その結果、図２［３］に示すような、
ダメージのないＭＳＱ３，７が得られる。一方、従来の
アッシング方法では、図３に示すように、ＭＳＱ３，７
がダメージを受けてオーバーハング形状となっているThen, the KrF resist 6 and the ARC 5 are ashed. At this time, since the side walls of the MSQs 3 and 7 are exposed, it is necessary to ash them without damaging them, so the ashing method according to the present invention is used. As a result, as shown in FIG.
You can get MSQ3,7 without damage. On the other hand, in the conventional ashing method, as shown in FIG.
Has been damaged and has become an overhang shape

【００１８】図４は、本実施例で使用するアッシャーを
示す構成図である。ソース源は、誘導結合プラズマ（Ｉ
ＣＰ）である。アッシングガスは、ガス導入ライン１１
を通って供給される。ソースＲＦ電源１３からコイル１
２に高周波電力が供給されると、誘導結合プラズマが発
生する。被処理基板としてのウエハー１５は、真空チャ
ンバー１７内のステージ１６上に固定される。ステージ
１６の温度は可変（−２０℃〜２５０℃）である。プラ
ズマはダウンフローによりウエハー１５まで到達するの
で、アッシング処理が可能になる。アッシング後の反応
生成物及びガスは、排気ライン１４を通って排気され
る。FIG. 4 is a block diagram showing the asher used in this embodiment. The source is an inductively coupled plasma (I
CP). The ashing gas is the gas introduction line 11
Supplied through. Source RF power supply 13 to coil 1
When high-frequency power is supplied to 2, inductively coupled plasma is generated. A wafer 15 as a substrate to be processed is fixed on a stage 16 in a vacuum chamber 17. The temperature of the stage 16 is variable (-20 ° C to 250 ° C). Since the plasma reaches the wafer 15 by the downflow, the ashing process can be performed. The reaction product and gas after ashing are exhausted through the exhaust line 14.

【００１９】本実施例でのアッシング条件を以下に示
す。 工程１：１３．３Ｐａ（１００ｍＴｏｒｒ）／ソースパ
ワー２５００Ｗ／バイアスパワー３００Ｗ／Ｎ２５００
ｓｃｃｍ／２０℃／６０ｓｅｃ 工程２：１３．３Ｐａ（１００ｍＴｏｒｒ）／ソースパ
ワー２５００Ｗ／バイアスパワー５００Ｗ／Ｎ２４５０
ｓｃｃｍ＋Ｈ２５０ｓｃｃｍ／２０℃／２００ｓｅｃThe ashing conditions in this embodiment are shown below. Step 1: 13.3Pa (100mTorr) / Source Power 2500W / bias power 300 W / N 2 500
sccm / 20 ° C./60 sec Step 2: 13.3 Pa (100 mTorr) / source power 2500 W / bias power 500 W / N 2 450
sccm + H 2 50sccm / 20 ℃ / 200sec

【００２０】図５は、ＭＳＱの構造を示す図である。Ｍ
ＳＱは、Ｓｉ‐Ｏ鎖にＣＨ３基が結合した構造になって
いる。アッシングによってＣＨ３基が脱離した場合に、
ダメージが発生すると考えられる。FIG. 5 is a diagram showing the structure of the MSQ. M
SQ has a structure in which a CH 3 group is bonded to the Si-O chain. When the CH 3 group is eliminated by ashing,
It is thought that damage will occur.

【００２１】ここでアッシングによるダメージ層を観察
する方法について説明する。まず、溝及びビアアッシン
グ後の図２［２］の状態において、フォトレジストを塗
布して埋め込む。続いて、断面サンプルを作成し、これ
を希釈フッ酸にて浸析する。ダメージ層は、ＭＳＱ中の
ＣＨ３基が脱離しているためにＳｉＯ２構造に近くなっ
ているので、フッ酸に対する溶解速度がＭＳＱより大き
い。すなわち、ダメージ層が速く溶解するため、ダメー
ジの有無が観察可能となる。Here, a method of observing a damaged layer due to ashing will be described. First, in the state of FIG. 2 [2] after the groove and via ashing, a photoresist is applied and embedded. Then, a cross-section sample is created and this is immersed in diluted hydrofluoric acid. Since the damaged layer is close to the SiO 2 structure due to the elimination of the CH 3 group in MSQ, the dissolution rate in hydrofluoric acid is higher than that in MSQ. That is, since the damaged layer dissolves quickly, the presence or absence of damage can be observed.

【００２２】断面ＳＥＭ観察によって溝側壁のダメージ
膜厚を見積もった結果を、図６に示す。エッチング後
（リファレンス）、Ｏ２アッシング後、Ｎ２／Ｈ２アッ
シング後、Ｎ２＋Ｎ２／Ｈ２アッシング後で比較した場
合、Ｏ２及びＮ２／Ｈ２では、エッチング後よりもダメ
ージ膜厚が増加している。これに対し、Ｎ２＋Ｎ２／Ｈ
２では、エッチング後から変化がないので、アッシング
によるダメージを受けていないことが分かる。Damage to the side wall of the groove by SEM observation of the cross section
The results of estimating the film thickness are shown in FIG. After etching
(Reference), OTwoAfter ashing, NTwo/ HTwoUp
After Sing, NTwo+ NTwo/ HTwoWhen comparing after ashing
If OTwoAnd NTwo/ HTwoThen, it ’s worse than after etching.
The film thickness is increasing. On the other hand, NTwo+ NTwo/ H
TwoSince there is no change after etching, ashing
You can see that it has not been damaged by.

【００２３】これは、工程１のＮ２プラズマによって、
ＣＨ３基がＣＮに置換した薄い改質層が形成されたた
め、と考えられる。工程２のＮ２／Ｈ２プラズマでアッ
シングするときに、Ｎ２／Ｈ２プラズマと改質層との反
応性は低い。よって、改質層はＭＳＱの保護膜となるこ
とにより、Ｎ２／Ｈ２プラズマがＭＳＱ内部まで拡散し
ないので、膜ダメージの抑制が可能となる。This is due to the N 2 plasma of step 1,
It is considered that this is because a thin modified layer in which the CH 3 group was substituted with CN was formed. When performing ashing with N 2 / H 2 plasma in step 2, the reactivity between the N 2 / H 2 plasma and the modified layer is low. Therefore, since the modified layer serves as a protective film for MSQ, N 2 / H 2 plasma does not diffuse into the inside of MSQ, so that film damage can be suppressed.

【００２４】また、実際の形状サンプルに本実施例のア
ッシング条件を適用した結果、ＭＳＱ３，７において、
膜ダメージが発生した場合に発生するオーバーハングは
見られなかった。また、同時にフォトレジストも除去で
きるので、本実施例の有効性が確認された。Further, as a result of applying the ashing conditions of this embodiment to an actual shape sample, as a result, in MSQ3,7,
No overhang occurred when the film was damaged. Further, since the photoresist can be removed at the same time, the effectiveness of this embodiment was confirmed.

【００２５】[0025]

【実施例２】図７は、本発明に係るアッシング方法の実
施例２を示す断面図である。以下、この図面に基づき説
明する。Second Embodiment FIG. 7 is a sectional view showing a second embodiment of the ashing method according to the present invention. Hereinafter, description will be given with reference to this drawing.

【００２６】本実施例は、他のデュアルダマシン作成方
法であるビアファースト方法に本発明を適用したもので
ある。まず、配線であるＣｕ１８の上に、５０ｎｍのＳ
ｉＣ（ビアストッパー）１９、３００ｎｍのＭＳＱ（ビ
ア層間膜）２０、５０ｎｍのＳｉＣ（溝ストッパー）２
１、３００ｎｍのＭＳＱ（溝層間膜）２２、５０ｎｍの
ＳｉＣ（ハードマスク）２３を順次成膜する。続いて、
ＡＲＣ２４、ＫｒＦレジスト２５を順次塗布し、０.１
８μｍ径のビアを露光及び現像によりパターニングす
る。続いて、ＫｒＦレジスト２５をマスクとして、ＡＲ
Ｃ２４、ＳｉＣ２３、ＭＳＱ２２、ＳｉＣ２１、ＭＳＱ
２０をドライエッチングすることにより、ビアを形成す
る。エッチング装置には、二周波ＲＩＥエッチャーを使
用する。ＡＲＣ２４、ＳｉＣ２３，２１のエッチングガ
スはＣＦ４、Ａｒ、Ｏ２であり、ＭＳＱ２２，２０のエ
ッチングガスはＣ４Ｆ８、Ａｒ、Ｎ２である。ビアエッ
チング後の形状を、図７［１］に示す。In this embodiment, the present invention is applied to the via first method, which is another method for making a dual damascene. First, on the Cu18 which is the wiring, S of 50 nm
iC (via stopper) 19, 300 nm MSQ (via interlayer film) 20, 50 nm SiC (groove stopper) 2
An MSQ (groove interlayer film) 22 having a thickness of 1,300 nm and a SiC (hard mask) 23 having a thickness of 50 nm are sequentially formed. continue,
ARC24 and KrF resist 25 are applied in order, and then 0.1
A via having a diameter of 8 μm is patterned by exposure and development. Then, using the KrF resist 25 as a mask, AR
C24, SiC23, MSQ22, SiC21, MSQ
A via is formed by dry etching 20. A dual frequency RIE etcher is used for the etching device. ARC24, etching gas SiC23,21 is CF 4, Ar, are O 2, the etching gas MSQ22,20 is C 4 F 8, Ar, N 2. The shape after via etching is shown in FIG. 7 [1].

【００２７】続いて、ＫｒＦレジスト２５及びＡＲＣ２
４をアッシングする。このとき、ＭＳＱ２２，２０の側
壁が露出しているので、実施例１と同じアッシング条件
を適用する。そのため、ＭＳＱ２２，２０に膜ダメージ
を与えることなく、アッシングが可能である。続いて、
ＫｒＦレジスト２６を塗布し、Ｌ／Ｓ＝０.１８μｍ／
０.１８μｍの溝を露光及び現像によりパターニングす
る。続いて、ＫｒＦレジスト２６をマスクとして、Ｓｉ
Ｃ２３、ＭＳＱ２２をドライエッチングすることによ
り、溝を形成する。ここで、露光不良により、再度フォ
トリソグラフィをする場合（ＰＲ再工事）、アッシング
時にＭＳＱ２２，２０の側壁が露出しているので、実施
例１と同じアッシング条件を適用する（図７［２］）。Subsequently, KrF resist 25 and ARC2
Ashing 4. At this time, since the sidewalls of the MSQs 22 and 20 are exposed, the same ashing conditions as in Example 1 are applied. Therefore, ashing can be performed without damaging the MSQs 22 and 20. continue,
Apply KrF resist 26, L / S = 0.18 μm /
A 0.18 μm groove is patterned by exposure and development. Then, using the KrF resist 26 as a mask, Si
A groove is formed by dry etching C23 and MSQ22. Here, when photolithography is performed again due to poor exposure (PR rework), since the sidewalls of the MSQs 22 and 20 are exposed during ashing, the same ashing conditions as in Example 1 are applied (FIG. 7 [2]). .

【００２８】ＳｉＣ２３のエッチングガスはＣＦ４、Ａ
ｒ、Ｏ２であり、ＭＳＱ２２のエッチングガスはＣ４Ｆ
８、Ａｒ、Ｎ２である。溝エッチング後の形状を図７
［３］に示す。ＭＳＱ２２の溝及びＭＳＱ２０のビアが
露出しているので、実施例１と同じアッシング条件を適
用する。これにより、ＭＳＱ２２，２０に膜ダメージを
与えることなく、ＫｒＦレジスト２６をアッシングでき
る。The etching gas for SiC23 is CF 4 , A
r, O 2 and the etching gas of MSQ22 is C 4 F
8 , Ar and N 2 . Figure 7 shows the shape after groove etching.
It is shown in [3]. Since the groove of MSQ22 and the via of MSQ20 are exposed, the same ashing conditions as in Example 1 are applied. As a result, the KrF resist 26 can be ashed without damaging the MSQs 22 and 20.

【００２９】[0029]

【実施例３】図８は、本発明に係るアッシング方法の実
施例３を示す断面図である。以下、この図面に基づき説
明する。Third Embodiment FIG. 8 is a sectional view showing a third embodiment of the ashing method according to the present invention. Hereinafter, description will be given with reference to this drawing.

【００３０】本実施例は、他のデュアルダマシン作成方
法であるデュアルハードマスク方法に本発明を適用した
ものである。まず、配線であるＣｕ１８の上に、５０ｎ
ｍのＳｉＣ（ビアストッパー）１９、３００ｎｍのＭＳ
Ｑ（ビア層間膜）２０、５０ｎｍのＳｉＣ（溝ストッパ
ー）２１、３００ｎｍのＭＳＱ（溝層間膜）２２、５０
ｎｍのＳｉＣ（下層ハードマスク）２３、１２０ｎｍの
ＳｉＮ（上層ハードマスク）２７を順次成膜する。続い
て、ＡＲＣ２４、ＫｒＦレジスト２５を順次塗布し、Ｌ
／Ｓ＝０.１８μｍ／０.１８μｍの溝を露光及び現像す
ることによりパターニングする。続いて、ＫｒＦレジス
ト２５をマスクとしてＳｉＮ２７をドライエッチングし
（図８［１］）、ＡＲＣ２４、ＫｒＦレジスト２５をア
ッシングする。ここでは、まだＭＳＱ２２が露出してい
ないので、アッシングは通常の高温Ｏ２プラズマで構わ
ない。In this embodiment, the present invention is applied to a dual hard mask method which is another dual damascene manufacturing method. First, 50n on the Cu18 which is the wiring
m SiC (via stopper) 19, 300 nm MS
Q (via interlayer film) 20, 50 nm SiC (groove stopper) 21, 300 nm MSQ (groove interlayer film) 22, 50
nm (lower layer hard mask) 23 and 120 nm SiN (upper layer hard mask) 27 are sequentially formed. Subsequently, the ARC 24 and the KrF resist 25 are sequentially applied, and L
Patterning is performed by exposing and developing a groove of /S=0.18 μm / 0.18 μm. Subsequently, the SiN 27 is dry-etched using the KrF resist 25 as a mask (FIG. 8 [1]), and the ARC 24 and the KrF resist 25 are ashed. Here, since the MSQ 22 has not been exposed yet, the ashing may be performed using normal high temperature O 2 plasma.

【００３１】続いて、ＡＲＣ２４、ＫｒＦレジスト２８
を塗布し、０.１８μｍのビアを露光及び現像によりパ
ターニングする。続いて、ＫｒＦレジスト２８をマスク
として、ＳｉＣ２３、ＭＳＱ２２、ＳｉＣ２１、ＭＳＱ
２０をドライエッチングすることにより、ビアを形成す
る（図８［２］）。続いて、ＫｒＦレジスト２８及びＡ
ＲＣ２４をアッシングする。このとき、ＭＳＱ２２，２
０の側壁が露出しているので、実施例１と同じアッシン
グ条件を適用する。これにより、ＭＳＱ２２，２０に膜
ダメージを与えることなく、アッシングが可能となる。Then, the ARC 24 and the KrF resist 28 are formed.
And 0.18 μm vias are exposed and developed to be patterned. Then, using the KrF resist 28 as a mask, SiC23, MSQ22, SiC21, MSQ
A via is formed by dry etching 20 (FIG. 8 [2]). Then, KrF resist 28 and A
Ashing RC24. At this time, MSQ22, 2
Since the side wall of 0 is exposed, the same ashing conditions as in Example 1 are applied. This enables ashing without damaging the MSQs 22 and 20.

【００３２】続いて、ＳｉＮ（上層ハードマスク）２７
をマスクとして、ＳｉＣ２３、ＭＳＱ２２、ＳｉＣ２１
及びＳｉＣ１９をドライエッチングして溝を形成し、デ
ュアルダマシン構造を作成する（図８［３］）。Subsequently, SiN (upper layer hard mask) 27
As a mask, SiC23, MSQ22, SiC21
Then, the SiC 19 is dry-etched to form a groove to form a dual damascene structure (FIG. 8 [3]).

【００３３】[0033]

【他の実施例】ＭＳＱに代えてＨＳＱ又はＭＨＳＱを用
いた場合も、同様の効果が得られた。ＨＳＱとは、Ｓｉ
Ｏ２のＳｉ原子に結合する四つのＯ原子のうち一つをＨ
原子で置換したｌｏｗ−ｋ材料であり、（Ｈ−ＳｉＯ
３／２）ｎと表記される。ＭＨＳＱとは、ＳｉＯ２のＳ
ｉ原子に結合する四つのＯ原子のうち一つをＣＨ３基又
はＨ原子で置換したｌｏｗ−ｋ材料であり、（ＣＨ３，
Ｈ−ＳｉＯ３／２）ｎと表記される。Other Embodiments Similar effects were obtained when HSQ or MHSQ was used instead of MSQ. HSQ is Si
One of the four O atoms bonded to the Si atom of O 2 is H
It is a low-k material that has been replaced with atoms, and
3/2 ) n. MHSQ is S of SiO 2 .
a low-k material in which one of four O atoms bonded to an i atom is replaced with a CH 3 group or an H atom, and (CH 3 ,
H-SiO 3/2 ) n.

【００３４】また、ストッパーＳｉＣの代わりにＳｉ
Ｎ、ＳｉＯＮ、ＳｉＣＮを用いた場合や、デュアルハー
ドマスクの材質をＳｉＯ２、ＳｉＮ、ＳｉＯＮ、Ｓｉ
Ｃ、ＳｉＣＮのどれか二つの組み合わせにした場合や、
フォトレジストをＫｒＦレジストの代わりにＡｒＦレジ
ストとした場合においても同様の効果が得られた。Further, instead of the stopper SiC, Si is used.
When N, SiON, or SiCN is used, or the material of the dual hard mask is SiO 2 , SiN, SiON, or Si.
In the case of combining any two of C and SiCN,
Similar effects were obtained when ArF resist was used as the photoresist instead of KrF resist.

【００３５】[0035]

【発明の効果】本発明に係るアッシング方法によれば、
層間絶縁膜の露出部分にＮ２／Ｈ２プラズマに耐え得る
改質層をＮ２プラズマを用いて形成した後、フォトレジ
ストをＮ２／Ｈ２プラズマを用いて除去することによ
り、Ｎ２／Ｈ２プラズマに対して改質層が層間絶縁膜の
保護膜として働くので、フォトレジスト除去時の層間絶
縁膜のダメージを抑制できる。According to the ashing method of the present invention,
After the modified layer can withstand N 2 / H 2 plasma to the exposed portion of the interlayer insulating film formed using a N 2 plasma, by removing the photoresist with a N 2 / H 2 plasma, N 2 / Since the modified layer acts as a protective film for the interlayer insulating film against H 2 plasma, damage to the interlayer insulating film when removing the photoresist can be suppressed.

【００３６】層間絶縁膜としてＣＨ３基又はＨ原子を有
する材料、特にＭＳＱ、ＨＳＱ、ＭＨＳＱ等を採用した
場合は、Ｎ２プラズマによって、ＣＨ３基又はＨ原子が
ＣＮに置換した薄い改質層が形成される。一方、この改
質層は、Ｎ２／Ｈ２プラズマとの反応性が低いので、層
間絶縁膜の保護膜となる。したがって、Ｎ２／Ｈ２プラ
ズマが層間絶縁膜の内部まで拡散しないので、層間絶縁
膜のダメージを抑制できる。When a material having a CH 3 group or H atom, particularly MSQ, HSQ, MHSQ, etc. is adopted as the interlayer insulating film, a thin modified layer in which the CH 3 group or H atom is replaced by CN by N 2 plasma Is formed. On the other hand, this modified layer has a low reactivity with N 2 / H 2 plasma and therefore serves as a protective film for the interlayer insulating film. Therefore, the N 2 / H 2 plasma does not diffuse into the interlayer insulating film, so that damage to the interlayer insulating film can be suppressed.

【００３７】フォトレジストをＮ２／Ｈ２プラズマを用
いて除去する際に、層間絶縁膜を０〜８０℃に保持した
場合、又はＮ２／Ｈ２の圧力を１．３３〜１３．３Ｐａ
とした場合は、層間絶縁膜のダメージを更に抑制でき
る。なぜなら、一般に低温化又は低圧化するほど、層間
絶縁膜のダメージが低減するからである。このときの上
限値は、これ以上に高温又は高圧になるとダメージの低
減が僅少になって、実用的でなくなる値である。下限値
は、これ以下に低温又は低圧になると反応速度が遅くな
って、実用的でなくなる値である。When the photoresist is removed using N 2 / H 2 plasma, the interlayer insulating film is held at 0 to 80 ° C., or the N 2 / H 2 pressure is 1.33 to 13.3 Pa.
In that case, damage to the interlayer insulating film can be further suppressed. This is because generally, the lower the temperature or the lower the pressure, the less the damage to the interlayer insulating film. The upper limit value at this time is a value at which the reduction in damage becomes negligible when the temperature becomes higher or the pressure becomes higher than this value, which is not practical. The lower limit value is a value at which the reaction rate becomes slower at lower temperatures or lower pressures, and is not practical.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明に係るアッシング方法の一実施形態を示
す工程図である。FIG. 1 is a process chart showing an embodiment of an ashing method according to the present invention.

【図２】本発明に係るアッシング方法の実施例１を示す
断面図であり、図２［１］〜図２［３］の順に工程が進
行する。FIG. 2 is a cross-sectional view showing a first embodiment of an ashing method according to the present invention, in which the steps proceed in the order of FIGS. 2 [1] to 2 [3].

【図３】アッシング方法を除き実施例１と同じ条件とし
た比較例を示す断面図である。FIG. 3 is a cross-sectional view showing a comparative example under the same conditions as in Example 1 except for the ashing method.

【図４】実施例で使用するアッシャーを示す構成図であ
る。FIG. 4 is a configuration diagram showing an asher used in an example.

【図５】ＭＳＱの構造を示す図である。FIG. 5 is a diagram showing a structure of MSQ.

【図６】アッシング方法とダメージ膜厚との関係を示す
グラフである。FIG. 6 is a graph showing a relationship between an ashing method and a damaged film thickness.

【図７】本発明に係るアッシング方法の実施例２を示す
断面図であり、図７［１］〜図７［３］の順に工程が進
行する。FIG. 7 is a cross-sectional view showing a second embodiment of the ashing method according to the present invention, in which the steps proceed in the order of FIGS. 7 [1] to 7 [3].

【図８】本発明に係るアッシング方法の実施例３を示す
断面図であり、図８［１］〜図８［３］の順に工程が進
行する。FIG. 8 is a cross-sectional view showing a third embodiment of the ashing method according to the present invention, in which the steps proceed in the order of FIGS. 8 [1] to 8 [3].

【符号の説明】[Explanation of symbols]

３，７，２０，２２ ＭＳＱ（層間絶縁膜） ６，１３，２５，２６，２８ ＫｒＦレジスト（フォト
レジスト）3,7,20,22 MSQ (interlayer insulating film) 6,13,25,26,28 KrF resist (photoresist)

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 2H096 AA25 LA08 LA30 5F004 AA09 BA04 BA20 DA01 DA23 DA24 DA25 DA26 DB00 EA03 EA07 EA14 EA22 EA23 EA28 5F033 KK11 MM02 QQ09 QQ25 QQ28 QQ37 QQ90 RR01 RR06 RR08 RR23 RR25 TT02 TT04 TT06 TT07 5F046 MA12    ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 2H096 AA25 LA08 LA30                 5F004 AA09 BA04 BA20 DA01 DA23                       DA24 DA25 DA26 DB00 EA03                       EA07 EA14 EA22 EA23 EA28                 5F033 KK11 MM02 QQ09 QQ25 QQ28                       QQ37 QQ90 RR01 RR06 RR08                       RR23 RR25 TT02 TT04 TT06                       TT07                 5F046 MA12

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 一部が露出した層間絶縁膜の上に形成さ
れたフォトレジストを窒素と水素との混合ガスのプラズ
マを用いて除去するアッシング方法において、 予め、前記層間絶縁膜の露出部分に、前記混合ガスのプ
ラズマに耐え得る改質層を窒素ガスのプラズマを用いて
形成しておく、 ことを特徴とするアッシング方法。1. An ashing method of removing a photoresist formed on a partially exposed interlayer insulating film by using plasma of a mixed gas of nitrogen and hydrogen, wherein an exposed portion of the interlayer insulating film is previously formed. An ashing method, characterized in that a modified layer that can withstand the plasma of the mixed gas is formed by using plasma of nitrogen gas. 【請求項２】 前記層間絶縁膜がＣＨ３基を有する材料
からなる、 請求項１記載のアッシング方法。2. The ashing method according to claim 1, wherein the interlayer insulating film is made of a material having a CH 3 group. 【請求項３】 前記層間絶縁膜がＨ原子を有する材料か
らなる、 請求項１記載のアッシング方法。3. The ashing method according to claim 1, wherein the interlayer insulating film is made of a material having H atoms. 【請求項４】 前記層間絶縁膜がＭＳＱ（methyl silse
squioxane）からなる、 請求項１記載のアッシング方法。4. The interlayer insulating film is MSQ (methyl silse).
squioxane), The ashing method according to claim 1. 【請求項５】 前記層間絶縁膜がＨＳＱ（hydrogen sil
sesquioxane）からなる、 請求項１記載のアッシング方法。5. The interlayer insulating film is HSQ (hydrogen sil
sesquioxane), The ashing method according to claim 1. 【請求項６】 前記層間絶縁膜がＭＨＳＱ（methyl hyd
rogen silsesquioxane）からなる、 請求項１記載のアッシング方法。6. The interlayer insulating film is MHSQ (methyl hyd).
rogen silsesquioxane), The ashing method according to claim 1. 【請求項７】 前記フォトレジストを前記混合ガスのプ
ラズマを用いて除去する際に、前記層間絶縁膜を０〜８
０℃に保持する、 請求項１、２、３、４、５又は６記載のアッシング方
法。7. When the photoresist is removed by using the plasma of the mixed gas, the interlayer insulating film is removed from 0 to 8
The ashing method according to claim 1, 2, 3, 4, 5 or 6, which is maintained at 0 ° C. 【請求項８】 前記フォトレジストを前記混合ガスのプ
ラズマを用いて除去する際に、当該混合ガスの圧力を
１．３３〜１３．３Ｐａとする、 請求項１、２、３、４、５又は６記載のアッシング方
法。8. The pressure of the mixed gas is set to 1.33 to 13.3 Pa when the photoresist is removed by using the plasma of the mixed gas, and the pressure is set to 1.33 to 13.3 Pa. 6. The ashing method according to 6.
JP2001284373A 2001-09-19 2001-09-19 Ashing method Pending JP2003092287A (en)

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KR1020020052352A KR20030025174A (en) 2001-09-19 2002-08-31 Method for manufacturing semiconductor device including two-step ashing process of N2 plasma gas and N2/H2 plasma gas
US10/237,053 US20030054656A1 (en) 2001-09-19 2002-09-09 Method for manufacturing semiconductor device including two-step ashing process of N2 plasma gas and N2/H2 plasma gas
TW091120537A TW559889B (en) 2001-09-19 2002-09-09 Method for manufacturing semiconductor device including two-step ashing process of N2 plasma gas and N2/H2 plasma gas

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