JP2003086890A - Method of manufacturing semiconductor light emitting element - Google Patents
Method of manufacturing semiconductor light emitting elementInfo
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- JP2003086890A JP2003086890A JP2001274851A JP2001274851A JP2003086890A JP 2003086890 A JP2003086890 A JP 2003086890A JP 2001274851 A JP2001274851 A JP 2001274851A JP 2001274851 A JP2001274851 A JP 2001274851A JP 2003086890 A JP2003086890 A JP 2003086890A
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- semiconductor substrate
- thermal conductivity
- light emitting
- main surface
- semiconductor light
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体レーザに適用
して好適な、半導体発光素子とその製造方法に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor light emitting device suitable for application to a semiconductor laser and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】半導体レーザは、主に光ファイバー通信
の分野で使用されており、特に半導体レーザアレイは、
波長分割多重（ＷＤＭ：Wavelength division multiple
xing)光伝送システム用の光源として使用されている。
これまで、広範囲な発振波長をもちかつ所望の発振波長
を精度良く発振させる半導体レーザアレイの研究が進め
られている。そこで、半導体基板上に隣り合う素子同士
でピッチの異なる複数の回折格子を形成するとともに、
隣り合う素子同士でマスク幅が異なる選択成長用マスク
を設けて結晶構造の異なる結晶成長層、例えば多重量子
井戸構造を選択成長させる方法が提案されている（特開
平８−１５３９２８号公報に記載）。この方法で作られ
た各半導体レーザにおいては、回折格子ピッチで決まる
発振波長と結晶構造で決まる利得ピーク波長をそれぞれ
独立に制御することができる。よって、ディチューニン
グ量（発振波長と利得ピーク波長との差）を常に一定範
囲に収めることができ、複数の所望の発振波長を得るこ
とができる。2. Description of the Related Art Semiconductor lasers are mainly used in the field of optical fiber communication. In particular, semiconductor laser arrays are
Wavelength division multiple (WDM)
xing) Used as a light source for optical transmission systems.
Up to now, research on a semiconductor laser array having a wide range of oscillation wavelengths and capable of accurately oscillating a desired oscillation wavelength has been advanced. Therefore, while forming a plurality of diffraction gratings with different pitches between adjacent elements on the semiconductor substrate,
A method has been proposed in which a mask for selective growth having a different mask width between adjacent elements is provided to selectively grow a crystal growth layer having a different crystal structure, for example, a multiple quantum well structure (described in Japanese Patent Laid-Open No. 8-153928). . In each semiconductor laser manufactured by this method, the oscillation wavelength determined by the diffraction grating pitch and the gain peak wavelength determined by the crystal structure can be controlled independently. Therefore, the detuning amount (difference between the oscillation wavelength and the gain peak wavelength) can always be kept within a certain range, and a plurality of desired oscillation wavelengths can be obtained.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、マスク
の幅を変えることによって利得ピーク波長を変える上記
従来方法では、隣り合うマスクの影響が不可避な構成で
あるため、結晶成長時における結晶種ガスの濃度分布の
制御が困難となる。この困難な状況下で、設計値通りの
利得ピーク波長をもつ結晶構造を形成させるためのマス
ク設計は複雑となる。However, in the above-mentioned conventional method in which the gain peak wavelength is changed by changing the width of the mask, the influence of the adjacent masks is inevitable, so that the concentration of the crystal seed gas during crystal growth is increased. It is difficult to control the distribution. Under this difficult situation, the mask design for forming a crystal structure having a gain peak wavelength as designed becomes complicated.
【０００４】また、多重量子井戸構造を形成する井戸層
及び障壁層を、それぞれの膜厚が各素子同士で実質的に
同一となるように、形成できないうえに、各層の組成を
個別に制御することが困難となる。Further, the well layer and the barrier layer forming the multiple quantum well structure cannot be formed so that the respective film thicknesses thereof are substantially the same among the respective elements, and the composition of each layer is individually controlled. Becomes difficult.
【０００５】層の膜厚及び組成を設計値通りに形成でき
ないと、得られる半導体発光素子の閾値電流、スロープ
効率及び温度特性等の各種特性が所望の設計値となら
ず、そのため製品歩留まりが低下する。If the film thickness and composition of the layer cannot be formed as designed, various characteristics such as threshold current, slope efficiency and temperature characteristics of the obtained semiconductor light emitting element do not reach desired designed values, and the product yield decreases. To do.
【０００６】そこで、上述の種々の問題点を技術的に解
決する手法の出現が望まれていた。Therefore, the advent of a technique for technically solving the above-mentioned various problems has been desired.
【０００７】[0007]
【課題を解決するための手段】そこで、この発明は下記
のような構成上の特徴を有する。Therefore, the present invention has the following structural features.
【０００８】すなわち、この発明の半導体レーザアレイ
の製造方法では、半導体基板上に、回折格子を複数区分
領域に形成し、回折格子を備える半導体基板上に結晶成
長させる際に、半導体基板と半導体基板を加熱する発熱
体との間に、半導体基板と発熱体との間の熱伝導度を、
半導体基板の区分領域毎に異なる熱伝導度変異部を介在
させて半導体基板を加熱する。That is, according to the method of manufacturing a semiconductor laser array of the present invention, when a diffraction grating is formed in a plurality of divided regions on a semiconductor substrate and crystal growth is performed on the semiconductor substrate having the diffraction grating, the semiconductor substrate and the semiconductor substrate are The heat conductivity between the semiconductor substrate and the heating element,
The semiconductor substrate is heated by interposing different thermal conductivity varying portions for each divided region of the semiconductor substrate.
【０００９】このように熱伝導度を変えると、半導体基
板の区分領域毎に温度が異なる。When the thermal conductivity is changed in this way, the temperature is different for each divided region of the semiconductor substrate.
【００１０】従って、半導体基板の温度分布と結晶構造
との関係を予め調べておけば、所望の結晶構造に応じた
熱伝導度を設定すれば良い。このように熱伝導度を設定
することにより、半導体基板上に、複数の結晶構造（組
成）の異なる成長結晶層、例えば、多重量子井戸構造と
なる井戸層及び障壁層を設計値通りに形成でき、製品歩
留まりが向上する。また、選択成長用マスクが不要とな
り製造工程が減るため、従来よりも安価に各半導体発光
素子を製造することができる。Therefore, if the relationship between the temperature distribution of the semiconductor substrate and the crystal structure is examined in advance, the thermal conductivity according to the desired crystal structure may be set. By setting the thermal conductivity in this way, a plurality of grown crystal layers having different crystal structures (compositions), for example, a well layer and a barrier layer having a multiple quantum well structure can be formed on the semiconductor substrate as designed. The product yield is improved. Further, since the mask for selective growth is not required and the number of manufacturing steps is reduced, each semiconductor light emitting element can be manufactured at a lower cost than before.
【００１１】[0011]
【発明の実施の形態】以下、図面を参照して、この発明
の実施の形態につき説明する。尚、各図は、この発明が
理解できる程度に各構成成分の形状、大きさ及び配置関
係を概略的に示してあるに過ぎず、従って、この発明を
図示例に限定するものではない。また、図を分かり易く
するために、断面を示すハッチング（斜線）は一部分を
除き省略してある。尚、以下の説明は、好適例であるに
過ぎないので、数値的条件は例示された値に何ら限定さ
れない。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the respective drawings merely schematically show the shapes, sizes and arrangement relationships of the respective constituents to the extent that the present invention can be understood, and therefore the present invention is not limited to the illustrated examples. Further, hatching (diagonal line) showing a cross section is omitted except for a part for the sake of easy understanding of the drawing. The following description is only a preferable example, and the numerical conditions are not limited to the exemplified values.
【００１２】＜第１の実施の形態＞図１〜図４を参照し
て、この発明の半導体発光素子の製造方法につき、半導
体レーザを例に挙げて、説明する。ここでは、一例とし
て、先ず、ＢＨ構造を有する分布帰還型半導体レーザア
レイの製造方法につき説明する。<First Embodiment> A method for manufacturing a semiconductor light emitting device according to the present invention will be described with reference to FIGS. 1 to 4 by taking a semiconductor laser as an example. Here, as an example, first, a method of manufacturing a distributed feedback semiconductor laser array having a BH structure will be described.
【００１３】第１の実施の形態によれば、半導体基板上
に、回折格子を複数列形成する。According to the first embodiment, a plurality of rows of diffraction gratings are formed on the semiconductor substrate.
【００１４】先ず、図１の概略斜視図に示すように、ｎ
型ＩｎＰ基板１０上に、回折格子１２を、電子ビーム露
光等を用いて、複数区分領域に形成する。この構成で
は、これら回折格子における格子間隔（ピッチ）は、隣
り合う区分領域内の回折格子毎に異ならせてある。これ
らピッチは、最小２０２ｎｍから最大２０３．２ｎｍま
での値とし、ピッチ差は０．４ｎｍとしてある。これら
各列の回折格子毎に、１つの半導体レーザが形成され
る。First, as shown in the schematic perspective view of FIG.
The diffraction grating 12 is formed on the type InP substrate 10 in a plurality of divided areas by using electron beam exposure or the like. In this configuration, the grating spacing (pitch) in these diffraction gratings is made different for each diffraction grating in the adjacent sectional areas. These pitches have a minimum value of 202 nm and a maximum value of 203.2 nm, and the pitch difference is 0.4 nm. One semiconductor laser is formed for each of the diffraction gratings in each column.
【００１５】このように回折格子の格子間隔を各列毎に
異ならせることによって、得られる半導体レーザの各々
の発振波長を、所望の波長となるように制御することが
できる。尚、ｎ型ＩｎＰ基板１０は、直径２インチ（１
インチは、約２．５４ｃｍ）及び厚さ３．５×１０5ｎ
ｍの円形基板（ウェハ）とし、ｎ型ＩｎＰ基板１０のド
ーパントは、例えばスズ（Ｓｎ）である。By thus varying the grating spacing of the diffraction grating for each column, it is possible to control the oscillation wavelength of each semiconductor laser obtained to a desired wavelength. The n-type InP substrate 10 has a diameter of 2 inches (1
Inch is about 2.54 cm) and thickness 3.5 × 10 5 n
The circular substrate (wafer) of m is used, and the dopant of the n-type InP substrate 10 is, for example, tin (Sn).
【００１６】そして、表面に回折格子構造を備えている
ｎ型ＩｎＰ基板１０を、気相結晶成長装置内に設置す
る。尚、気相成長法としては、例えば、有機金属気相成
長（ＭＯＶＰＥ）法などを用いることができる。Then, the n-type InP substrate 10 having a diffraction grating structure on its surface is installed in a vapor phase crystal growth apparatus. As the vapor phase growth method, for example, a metal organic chemical vapor deposition (MOVPE) method or the like can be used.
【００１７】気相結晶成長装置として、高速回転型気相
結晶成長装置１４の処理室（チャンバ）内の一構成例の
要部の概略的平面図を図２（Ａ）に示す。気相結晶成長
装置１４には、ｎ型ＩｎＰ基板１０を、第１主面（表
面）側に設置するためのウェハキャリア１６が設けられ
ている。ウェハキャリア１６の表面には、ｎ型ＩｎＰ基
板１０を個別に格納するためのウェハポケット１８が３
つ設けられている。尚、ウェハポケット１８の数は上述
に限定されず、気相結晶成長装置の構成や規模に応じて
任意に変更できるものとする。また、ウェハキャリア１
６の材料としては、カーボングラファイト（Ｃ）やモリ
ブデン（Ｍｏ）などの熱を伝導し易く、かつ結晶成長を
行う際の材料ガス等によって腐食しにくい安定な材料が
好ましい。FIG. 2A is a schematic plan view of a main part of a structural example of a processing chamber (chamber) of a high-speed rotation type vapor phase crystal growth apparatus 14 as a vapor phase crystal growth apparatus. The vapor phase crystal growth apparatus 14 is provided with a wafer carrier 16 for installing the n-type InP substrate 10 on the first main surface (front surface) side. The surface of the wafer carrier 16 has three wafer pockets 18 for individually storing the n-type InP substrate 10.
One is provided. The number of wafer pockets 18 is not limited to the above, and can be arbitrarily changed according to the configuration and scale of the vapor phase crystal growth apparatus. Also, the wafer carrier 1
As the material of No. 6, a stable material such as carbon graphite (C) or molybdenum (Mo) that easily conducts heat and is unlikely to be corroded by the material gas during crystal growth is preferable.
【００１８】図２（Ｂ）は、図２（Ａ）に示した気相結
晶成長装置１４のＡ−Ａ’線に沿って切断して得られる
断面の切り口を示す概略図である。この装置１４は、さ
らにサセプタと発熱体とを具えている。このサセプタ２
０は、ウェハキャリア１６とは反対側に設けられた発熱
体としてのヒータ２２により加熱される。従って、基板
１０は、サセプタ２０を介して加熱処理される。サセプ
タ２０には回転軸２４が接続されており、この回転軸２
４に接続された不図示の回転駆動源を駆動させることに
より、ｎ型ＩｎＰ基板１０をヒータ２２によって加熱さ
せる間、ウェハキャリア１６を一定速度で回転させる。
尚、サセプタ２０の材料としては、シリコンカーバイド
（ＳｉＣ）でコーティングされたカーボン（Ｃ）などが
好ましい。FIG. 2 (B) is a schematic view showing a cross section cut along a line AA 'of the vapor phase crystal growth apparatus 14 shown in FIG. 2 (A). The device 14 further comprises a susceptor and a heating element. This susceptor 2
0 is heated by a heater 22 as a heating element provided on the side opposite to the wafer carrier 16. Therefore, the substrate 10 is heat-treated via the susceptor 20. A rotation shaft 24 is connected to the susceptor 20.
By driving a rotation drive source (not shown) connected to No. 4, the wafer carrier 16 is rotated at a constant speed while the n-type InP substrate 10 is heated by the heater 22.
The material of the susceptor 20 is preferably carbon (C) coated with silicon carbide (SiC).
【００１９】この気相結晶成長装置１４によって、回折
格子を備える半導体基板の第１主面（表面）に対して結
晶成長を行う際に、半導体基板を加熱する。この発明で
は、この加熱処理を、半導体基板とこの半導体基板を加
熱する発熱体との間に、熱伝導度変異部５０を介在させ
て、行なう。この熱伝導度変異部５０は、半導体基板と
発熱体との間の熱伝導度を、半導体基板の区分領域毎に
異ならせる作用を有している。このように、この熱伝導
度変異部５０は、区分領域毎の温度、従って、半導体基
板での温度分布を決める作用を有している。The crystal growth apparatus 14 heats the semiconductor substrate when crystal growth is performed on the first main surface (front surface) of the semiconductor substrate having the diffraction grating. In the present invention, this heat treatment is performed with the thermal conductivity changing portion 50 interposed between the semiconductor substrate and the heating element that heats the semiconductor substrate. The thermal conductivity changing section 50 has a function of making the thermal conductivity between the semiconductor substrate and the heating element different for each divided region of the semiconductor substrate. As described above, the thermal conductivity changing portion 50 has a function of determining the temperature of each divided region, and thus the temperature distribution in the semiconductor substrate.
【００２０】この実施の形態によれば、半導体基板と発
熱体との間に熱伝導度変異部５０として、ウェハキャリ
ア１６の裏面に、互いに深さの異なる凹部を形成してい
る。すなわち、ウェハキャリア１６の第２主面（裏面）
に、深さの異なる凹部２６（点線で囲まれた領域）を連
続的に或いは不連続的に設けて、ウェハキャリア１６に
厚みが部分的に異なる構造部、すなわち厚み変異部を形
成してある。尚、空隙２７は、チャンバと同一圧力とし
ても良く、或いは、その他の圧力としても良い。また、
空隙２７には、適当なガスが存在していても良い。ま
た、熱伝導度変異部５０である凹部２６の形成によって
設けられる空隙２７と、連続するような空隙として空隙
２９が設けられていても良い。According to this embodiment, recesses having different depths are formed on the back surface of the wafer carrier 16 as the thermal conductivity varying portion 50 between the semiconductor substrate and the heating element. That is, the second main surface (back surface) of the wafer carrier 16
Further, recesses 26 (regions surrounded by dotted lines) having different depths are provided continuously or discontinuously to form a structural portion having a partially different thickness in the wafer carrier 16, that is, a thickness variation portion. . The void 27 may have the same pressure as the chamber, or may have another pressure. Also,
A suitable gas may be present in the void 27. Further, the voids 27 may be provided as continuous voids with the voids 27 provided by forming the recesses 26 that are the thermal conductivity varying portions 50.
【００２１】図３（Ａ）は、１つのウェハポケット１８
に着目して拡大して示した概略断面図である。ここで説
明する構成例では、この熱伝導度変異部５０を、ウェハ
キャリア１６の裏面に段差のある複数の区分領域とし
て、形成してある。これら区分領域は、円形状のウェハ
ポケット１８と対向する円形状領域を、厚みの異なる複
数の領域に分けて形成してある。例えば、この円形状領
域を、図３（Ｂ）に示すように、４つのセクタ領域（こ
こでは、象限）３０，３２，３４，３６に区分し、それ
ぞれのセクタ領域の厚みを、ウェハポケット１８の底部
２８から垂直方向に、それぞれａ，ｂ，ｃ及びｄとして
ある。FIG. 3A shows one wafer pocket 18
It is the schematic sectional drawing which expanded and showed paying attention to. In the configuration example described here, the thermal conductivity changing portion 50 is formed as a plurality of divided areas having steps on the back surface of the wafer carrier 16. These divided regions are formed by dividing a circular region facing the circular wafer pocket 18 into a plurality of regions having different thicknesses. For example, as shown in FIG. 3B, this circular area is divided into four sector areas (here, quadrants) 30, 32, 34, 36, and the thickness of each sector area is defined as the wafer pocket 18 Vertically from the bottom 28 of the a, b, c and d respectively.
【００２２】図３（Ｃ）に、この熱伝導度変異部５０を
構成するウェハキャリア１６の凹部２６の領域部分を、
ウェハキャリア１６の裏面側から見た様子を概略的に斜
視図で示してある。ウェハポケット１８の底部２８から
の距離が異なる上述４つの領域は、図３（Ｂ）及び
（Ｃ）に示すように、底部２８からの距離がａである領
域３０、ｂである領域３２、ｃである領域３４及びｄで
ある領域３６である。このように、ウェハポケット１８
の裏面側のウェハキャリア領域が、このように４つの領
域に分割されている。尚、ウェハキャリア１６に形成さ
れる熱伝導度変異部５０の形態は、底部２８からの距離
が異なる領域の数及び形状を、上述した構成例に限定す
るものではなく、また、回折格子の配列方向やピッチに
依存せずに他の適当な形態に変更することができる。す
なわち、熱伝導度変異部５０の形態は、半導体基板に成
長させる結晶層に所望の結晶構造を与えることが出来る
ように、半導体基板に温度分布を形成させる形態ならば
良い。FIG. 3C shows the region of the recess 26 of the wafer carrier 16 which constitutes the thermal conductivity varying portion 50.
FIG. 3 is a perspective view schematically showing a state of the wafer carrier 16 viewed from the back surface side. As shown in FIGS. 3B and 3C, the above-mentioned four regions having different distances from the bottom portion 28 of the wafer pocket 18 have regions a and b which are distances a and b from the bottom portion 28, 32 and c, respectively. The area 34 is and the area 36 is d. Thus, the wafer pocket 18
The wafer carrier area on the back surface side of is divided into four areas in this manner. The form of the thermal conductivity changing portion 50 formed on the wafer carrier 16 is not limited to the number and shape of the regions having different distances from the bottom portion 28 from the above-described configuration example, and the arrangement of the diffraction gratings is not limited. It can be changed to another suitable form without depending on the direction or the pitch. That is, the thermal conductivity changing portion 50 may have any form as long as the temperature distribution is formed in the semiconductor substrate so that the crystal layer grown on the semiconductor substrate can have a desired crystal structure.
【００２３】上述した構成の高速回転型気相結晶成長装
置１４を用いて、所定の条件下において、ｎ型ＩｎＰ基
板１０上に順次所望の結晶成長を行い薄膜を累積形成す
る。但し、この形成方法は従来公知の方法であるため、
概略的に説明する。Using the high-speed rotation type vapor phase crystal growth apparatus 14 having the above-described structure, desired crystals are sequentially grown on the n-type InP substrate 10 under predetermined conditions to cumulatively form thin films. However, since this forming method is a conventionally known method,
A brief description will be given.
【００２４】先ず、回折格子１２を備える各ｎ型ＩｎＰ
基板１０をその面のうち、結晶成長させる表面を上側に
して気相結晶成長装置１４内のウェハポケット１８に設
置する。First, each n-type InP having the diffraction grating 12 is provided.
The substrate 10 is placed in the wafer pocket 18 in the vapor phase crystal growth apparatus 14 with the surface on which the crystal is to be grown facing upwards.
【００２５】そして、圧力５５Ｔｏｒｒ及びヒータ２２
の設定温度６１０℃という成膜条件下で、回折格子１２
を備えるｎ型ＩｎＰ基板１０上面に、分布帰還型レーザ
における光ガイド層用膜（ＩｎＧａＡｓＰ）（図示せ
ず）を成長させた後、当該光ガイド層用膜上に多重量子
井戸構造用膜（ＩｎＧａＡｓＰ）３８、光ガイド層用膜
（ＩｎＧａＡｓＰ）３９ａ及びクラッド層用膜（ｐ型Ｉ
ｎＰ）３９ｂを、Ａ3Ｈ3（アルシン）、（ＣＨ3）3Ｉｎ
（トリメチルインジウム）、（Ｃ2Ｈ5）3Ｇａ（トリエ
チルガリウム）及びＰＨ3（フォスフィン）の混合ガス
を、適時に適量だけそれぞれ供給することにより、順次
結晶成長させる（第１結晶成長工程）。尚、この実施の
形態における多重量子井戸構造用膜（ＩｎＧａＡｓＰ）
は、一例として、７つの井戸層とこれら７つの井戸層を
隔てる６つの障壁層を備えた多重量子井戸構造（７井戸
構造）を構成しており、これら井戸層及び障壁層の膜厚
はそれぞれ６ｎｍ及び１０ｎｍとしてある。Then, the pressure is 55 Torr and the heater 22.
Under the film forming condition of the set temperature of 610 ° C.
After growing a film (InGaAsP) for an optical guide layer in a distributed feedback laser (not shown) on the upper surface of the n-type InP substrate 10 provided with, a film for a multiple quantum well structure (InGaAsP) is formed on the film for an optical guide layer. ) 38, an optical guide layer film (InGaAsP) 39a, and a cladding layer film (p-type I)
nP) 39b to A 3 H 3 (arsine), (CH 3 ) 3 In
A mixed gas of (trimethylindium), (C 2 H 5 ) 3 Ga (triethylgallium) and PH 3 (phosphine) is supplied in an appropriate amount at appropriate times to sequentially perform crystal growth (first crystal growth step). The film for the multiple quantum well structure (InGaAsP) in this embodiment
, As an example, constitutes a multi-quantum well structure (7 well structure) having 7 well layers and 6 barrier layers separating these 7 well layers. 6 nm and 10 nm.
【００２６】次に、クラッド層用膜（ｐ型ＩｎＰ）３９
ｂの上側に、マスク幅が数μｍ程度であるストライプ状
のエッチングマスク４０を、各回折格子を覆うように、
形成する。マスク材料には酸化シリコン（ＳｉＯ2）な
どの酸化膜を用いて、ＣＶＤ法及びホトリソグラフィ技
術により形成する（図４（Ａ）参照）。Next, the cladding layer film (p-type InP) 39
A striped etching mask 40 having a mask width of about several μm is provided on the upper side of b so as to cover each diffraction grating.
Form. An oxide film such as silicon oxide (SiO 2 ) is used as a mask material and is formed by a CVD method and a photolithography technique (see FIG. 4A).
【００２７】そして、エッチングマスク４０から露出す
る領域に対して、少なくともｎ型ＩｎＰ基板１０に到達
する深さまでドライエッチングを行い、メサ（ｍｅｓ
ａ）構造（多重量子井戸構造３８’、光ガイド層３９
ａ’およびクラッド層３９ｂ’）を形成する。その後、
第１結晶成長工程と同条件下（圧力５５Ｔｏｒｒ及びヒ
ータ２２の設定温度６１０℃）で、エッチングマスクか
ら露出する領域（多重量子井戸層の両側に位置するｎ型
ＩｎＰ基板）に、ｐ型ＩｎＰ及びｎ型ＩｎＰからなる電
流狭窄層（電流ブロック層ともいう）４２を結晶成長さ
せる。尚、ｐ型電流狭窄層のドーパントに（ＣＨ3）2Ｚ
ｎ（ジメチル亜鉛）を用い、ｎ型電流狭窄層のドーパン
トにＳｉ2Ｈ6（ジシラン）を用いる。Then, the region exposed from the etching mask 40 is dry-etched at least to a depth reaching the n-type InP substrate 10 to form a mesa (mes).
a) Structure (multiple quantum well structure 38 ', optical guide layer 39)
a'and the cladding layer 39b ') are formed. afterwards,
Under the same conditions as the first crystal growth step (pressure 55 Torr and set temperature of the heater 22 of 610 ° C.), p-type InP and n-type InP are formed in the regions exposed from the etching mask (n-type InP substrates located on both sides of the multiple quantum well layer). A current confinement layer (also referred to as a current block layer) 42 made of n-type InP is crystal-grown. The dopant for the p-type current confinement layer is (CH 3 ) 2 Z
n (dimethyl zinc) is used, and Si 2 H 6 (disilane) is used as a dopant for the n-type current confinement layer.
【００２８】その後、ストライプ状のエッチングマスク
を、酸性のエッチング溶液を用いてウェットエッチング
により除去する。然る後、第１及び第２結晶成長工程と
同条件下で、クラッド層（ｐ型ＩｎＰ）４３及びコンタ
クト層（ｐ型ＩｎＧａＡｓまたはＩｎＧａＡｓＰ）４４
を結晶成長させた後、任意好適な方法によって電極等を
形成しＢＨ構造を有する分布帰還型半導体レーザアレイ
を形成する（図４（Ｂ）参照）。尚、双方の層のドーパ
ントには、（ＣＨ3）2Ｚｎ（ジメチル亜鉛）を用いる。After that, the striped etching mask is removed by wet etching using an acidic etching solution. Then, under the same conditions as in the first and second crystal growth steps, the cladding layer (p-type InP) 43 and the contact layer (p-type InGaAs or InGaAsP) 44.
After crystal growth, a distributed feedback semiconductor laser array having a BH structure is formed by forming electrodes and the like by any suitable method (see FIG. 4B). Note that (CH 3 ) 2 Zn (dimethyl zinc) is used as the dopant for both layers.
【００２９】上述した説明から明らかなように、この実
施の形態では、ウェハキャリア１６の裏面に加工を施し
て、ウェハポケット１８の底部２８からの距離を異なら
せる複数の領域（３０，３２，３４，３６）を形成した
ことにより、ウェハキャリア１６とサセプタ２０との間
に距離の異なる空隙が出来ている。これら空隙に起因し
て、ヒータ２２側からｎ型ＩｎＰ基板１０に向かう方向
の熱伝導度が、ｎ型ＩｎＰ基板１０の裏面の部分領域毎
に異なる。As is clear from the above description, in this embodiment, the back surface of the wafer carrier 16 is processed to form a plurality of regions (30, 32, 34) having different distances from the bottom 28 of the wafer pocket 18. , 36), gaps having different distances are formed between the wafer carrier 16 and the susceptor 20. Due to these voids, the thermal conductivity in the direction from the heater 22 side toward the n-type InP substrate 10 is different for each partial region on the back surface of the n-type InP substrate 10.
【００３０】このように、ヒータ２２から基板１０の第
２主面（裏面）への熱伝導度が、基板の裏面の部分領域
毎に変わると、基板の裏面から表面に至る区分領域毎に
温度差が生じる。すなわち、基板の表面での温度が区分
領域毎に異なってくる。As described above, when the thermal conductivity from the heater 22 to the second main surface (back surface) of the substrate 10 changes for each partial area of the back surface of the substrate, the temperature for each divided area from the back surface of the substrate to the front surface is increased. There is a difference. That is, the temperature on the surface of the substrate differs for each divided area.
【００３１】従って、基板１０表面の温度分布と基板表
面に成膜される各層の層厚及び組成との相関関係の実測
データを予め求めれば、成膜すべき結晶層の種類に応じ
た熱伝導度変異部５０が形成されたウェハキャリア１６
を用意することが出来る。Therefore, if the actual measurement data of the correlation between the temperature distribution on the surface of the substrate 10 and the layer thickness and composition of each layer formed on the substrate surface is obtained in advance, the thermal conductivity according to the type of the crystal layer to be formed is obtained. Wafer carrier 16 in which the degree variation portion 50 is formed
Can be prepared.
【００３２】よって、形成しようとする多重量子井戸構
造に適した構造のウェハキャリア１６を用いて、ウェハ
に結晶構造（組成）の異なる多重量子井戸層を設計値通
りに複数形成できるため、各素子ごとに利得ピーク波長
を異ならせることができる。その上、各多重量子井戸層
の膜厚を実質的に同一に形成できることから、得られる
半導体発光素子の閾値電流、スロープ効率及び温度特性
等の各種特性を所望の設計値通りに形成でき、製品歩留
まりが向上する。Therefore, by using the wafer carrier 16 having a structure suitable for the multiple quantum well structure to be formed, it is possible to form a plurality of multiple quantum well layers having different crystal structures (compositions) on the wafer according to the design value. The gain peak wavelength can be different for each. Moreover, since the film thickness of each multiple quantum well layer can be formed to be substantially the same, various characteristics such as threshold current, slope efficiency and temperature characteristics of the obtained semiconductor light emitting device can be formed according to desired design values. Yield improves.
【００３３】従って、回折格子ピッチで決まる発振波長
と結晶構造で決まる利得ピーク波長との差（ディチュー
ニング量）を、従来よりも精度良く制御することができ
るので、高信頼性でかつ広範囲の発振波長をもつ半導体
発光素子アレイを得ることができる。Therefore, the difference (detuning amount) between the oscillation wavelength determined by the diffraction grating pitch and the gain peak wavelength determined by the crystal structure can be controlled more accurately than before, so that the oscillation is highly reliable and in a wide range. A semiconductor light emitting device array having a wavelength can be obtained.
【００３４】また、選択成長用マスクが不要なため製造
工程が減り、従来よりも安価に各半導体発光素子を製造
することができる。Further, since the selective growth mask is not required, the number of manufacturing steps is reduced, and each semiconductor light emitting element can be manufactured at a lower cost than before.
【００３５】尚、熱伝導度変異部５０となるウェハキャ
リア１６の裏面の加工形状は、上述のみに限られず、例
えば、図５（Ａ）及び（Ｂ）に示すような形状であって
も、この実施の形態と同様の効果を得ることが出来る。The processing shape of the back surface of the wafer carrier 16 which becomes the thermal conductivity varying portion 50 is not limited to the above, and for example, even if it has a shape as shown in FIGS. 5 (A) and 5 (B), The same effect as this embodiment can be obtained.
【００３６】図５（Ａ）に示す構成例では、熱伝導度変
異部５０を、ウェハポケット１８と同一の大きさの裏面
領域に、中心が山高で、周辺に向かって階段的に低くな
る同心リング状の形態に、形成している。In the configuration example shown in FIG. 5 (A), the thermal conductivity varying portion 50 is concentric in the back surface region of the same size as the wafer pocket 18, with the center being a mountain height and stepwise decreasing toward the periphery. It is formed in a ring shape.
【００３７】また、図５（Ｂ）に示す構成例では、熱伝
導度変異部５０を、円の直径の一端から他端に向けて、
当該直径に直交する方向にストライプ状に伸びているス
トライプを階段状の形態に、形成している。Further, in the configuration example shown in FIG. 5B, the thermal conductivity changing portion 50 is arranged from one end of the diameter of the circle to the other end thereof,
Stripes extending in a stripe shape in a direction orthogonal to the diameter are formed in a stepwise shape.
【００３８】＜第２の実施の形態＞第２の実施の形態に
よれば、ｎ型ＩｎＰ基板１０とヒータ２２との間の熱伝
導度を、ｎ型ＩｎＰ基板１０の区分領域毎に異ならせる
熱伝導度変異部５０として、ｎ型ＩｎＰ基板１０のうち
ヒータ２２と対向する側の面、すなわち第２主面（裏
面）自体に形成する。<Second Embodiment> According to the second embodiment, the thermal conductivity between the n-type InP substrate 10 and the heater 22 is made different for each divided region of the n-type InP substrate 10. The thermal conductivity varying portion 50 is formed on the surface of the n-type InP substrate 10 facing the heater 22, that is, the second main surface (back surface) itself.
【００３９】すなわち、この実施の形態では、ウェハキ
ャリア１６は、第１の実施の形態とは異なり、上述した
ような熱伝導度変異部を備えておらず、ウェハキャリア
１６の裏面は、例えば、平坦構造（図示せず）である。
しかし、この実施の形態での構成例では、ｎ型ＩｎＰ基
板１０のうち、ヒータ２２と対向する側の第２主面自体
に加工を施すことによって熱伝導度変異部５０を形成し
て、ｎ型ＩｎＰ基板１０とヒータ２２との間の熱伝導度
を、ｎ型ＩｎＰ基板１０の区分領域毎に異ならせてい
る。That is, in this embodiment, unlike the first embodiment, the wafer carrier 16 does not include the thermal conductivity changing portion as described above, and the back surface of the wafer carrier 16 is, for example, It is a flat structure (not shown).
However, in the configuration example of this embodiment, the thermal conductivity changing portion 50 is formed by processing the second main surface itself of the n-type InP substrate 10 on the side facing the heater 22, The thermal conductivity between the type InP substrate 10 and the heater 22 is made different for each divided region of the n-type InP substrate 10.
【００４０】図６（Ａ）は、第２の実施の形態における
熱伝導度変異部５０を説明するための、ｎ型ＩｎＰ基板
１０の第２主面（裏面）側からみた概略平面図である。
この実施の形態では、熱伝導度変異部５０として、ｎ型
ＩｎＰ基板１０のうち、ヒータ２２と対向する第２主面
すなわち裏面自体に、複数の厚みの異なる区分領域とし
て同心円状に形成してある。FIG. 6A is a schematic plan view from the second main surface (back surface) side of the n-type InP substrate 10 for explaining the thermal conductivity changing portion 50 in the second embodiment. .
In this embodiment, the thermal conductivity varying portion 50 is formed concentrically as a plurality of divided regions having different thicknesses on the second main surface of the n-type InP substrate 10 facing the heater 22, that is, the back surface itself. is there.
【００４１】各区分領域間に段差４６ａ，４６ｂを設け
てある。尚、段差４６ａ，４６ｂは、任意好適なエッチ
ング等の切削加工によって、基板１０裏面側に底面まで
の距離の異なる貫通しない凹部４７ａ，４７ｂを形成す
ることによって、得ることが出来る。Steps 46a and 46b are provided between the divided areas. The steps 46a and 46b can be obtained by forming recesses 47a and 47b that do not penetrate the substrate 10 on the back surface side and have different distances to the bottom surface by cutting such as suitable etching.
【００４２】また、ｎ型ＩｎＰ基板１０の裏面形状を同
心円状とすることにより、ウェハポケット１８内でのｎ
型ＩｎＰ基板１０を、安定な状態で支持させることがで
きる。Further, by making the back surface of the n-type InP substrate 10 concentric, the n inside the wafer pocket 18 is reduced.
The type InP substrate 10 can be supported in a stable state.
【００４３】そして、この実施の形態では、この熱伝導
度変異部５０が形成されたウェハ上に、第１の実施の形
態と同様の工程を経て、半導体発光素子アレイを形成す
る。尚、切削加工によって形成された段差４６ａ，４６
ｂは、後工程において任意好適な研磨処理によって平坦
化することが出来る。尚、この場合も、熱伝導度変異部
５０の形態は、半導体基板に成長させる結晶層に所望の
結晶構造を与えることが出来るように、半導体基板に温
度分布を形成させる形態ならば良い。Then, in this embodiment, a semiconductor light emitting element array is formed on the wafer on which the thermal conductivity varying portion 50 is formed, through the same steps as those in the first embodiment. The steps 46a, 46 formed by cutting
b can be flattened by any suitable polishing treatment in a later step. In this case as well, the form of the thermal conductivity changing portion 50 may be any form that forms a temperature distribution in the semiconductor substrate so that a desired crystal structure can be given to the crystal layer grown on the semiconductor substrate.
【００４４】上述した説明から明らかなように、この実
施の形態では、これまでの結晶成長装置をそのまま適用
させることができるとともに、第１の実施の形態と同様
の効果が得られる。As is clear from the above description, in this embodiment, the crystal growth apparatus up to this point can be applied as it is, and the same effect as that of the first embodiment can be obtained.
【００４５】＜第３の実施の形態＞第３の実施の形態に
よれば、第２の実施の形態と同様に、熱伝導度変異部５
０を、ｎ型ＩｎＰ基板１０の第２主面上に形成する点が
第１の実施の形態と異なる。<Third Embodiment> According to the third embodiment, as in the second embodiment, the thermal conductivity changing section 5 is used.
0 is formed on the second main surface of the n-type InP substrate 10, which is different from the first embodiment.
【００４６】そこで、ｎ型ＩｎＰ基板１０の概略平面図
を図６（Ｂ）に示す。この実施の形態では、熱伝導度変
異部５０として、ｎ型ＩｎＰ基板１０のうちヒータ２２
と対向する第２主面すなわち裏面上に、複数の厚みの異
なる区分を同心円状に形成してある。各区分領域間に、
段差４８ａ，４８ｂを設けてある。これらの段差４８
ａ，４８ｂは、基板１０の裏面上に、熱的安定性を有す
る酸化膜及び窒化膜の双方またはいずれか一方によっ
て、円盤上の凸部４９ａ，４９ｂを順次に同心円状に重
ねた形態で形成する。この凸部４９ａ，４９ｂは、通常
の、ＣＶＤ法及びホトリソグラフィ技術によって設ける
ことが出来る。Therefore, a schematic plan view of the n-type InP substrate 10 is shown in FIG. 6 (B). In this embodiment, the heater 22 of the n-type InP substrate 10 is used as the thermal conductivity changing portion 50.
A plurality of sections having different thicknesses are concentrically formed on the second main surface, that is, the back surface, which faces the. Between each divided area,
Steps 48a and 48b are provided. These steps 48
a and 48b are formed on the back surface of the substrate 10 in the form of concentric circular convex portions 49a and 49b sequentially formed by an oxide film and / or a nitride film having thermal stability. To do. The protrusions 49a and 49b can be provided by a usual CVD method and photolithography technique.
【００４７】そして、第１の実施の形態と同様の工程を
経て、この熱伝導度変異部５０が形成されたウェハ上に
半導体発光素子アレイを形成する。尚、設けられた段差
４８ａ，４８ｂは、後工程において任意好適なエッチン
グ処理によって平坦化することが出来る。尚、この場合
も、熱伝導度変異部５０の形態は、半導体基板に成長さ
せる結晶層に所望の結晶構造を与えることが出来るよう
に、半導体基板に温度分布を形成させる形態ならば良
い。Then, through the same steps as those in the first embodiment, a semiconductor light emitting element array is formed on the wafer on which the thermal conductivity varying portion 50 is formed. The provided steps 48a and 48b can be flattened by any suitable etching process in a post process. In this case as well, the form of the thermal conductivity changing portion 50 may be any form that forms a temperature distribution in the semiconductor substrate so that a desired crystal structure can be given to the crystal layer grown on the semiconductor substrate.
【００４８】上述した説明から明らかなように、この実
施の形態では、第１の実施の形態と同様の効果が得られ
る。As is clear from the above description, in this embodiment, the same effect as in the first embodiment can be obtained.
【００４９】＜第４の実施の形態＞第４の実施の形態に
よれば、ｎ型ＩｎＰ基板１０とヒータ２２との間の熱伝
導度変異部５０として、ウェハキャリア１６の裏面とヒ
ータ２２との間に、複数の熱伝導度変異領域をｎ型Ｉｎ
Ｐ基板１０の区分領域毎に備えるとともに、実質的に均
一な厚みを有する熱伝導度変異部５０を形成している。<Fourth Embodiment> According to the fourth embodiment, the back surface of the wafer carrier 16 and the heater 22 are provided as the thermal conductivity varying portion 50 between the n-type InP substrate 10 and the heater 22. Between the n-type In and
The thermal conductivity varying portion 50 is provided for each divided region of the P substrate 10 and has a substantially uniform thickness.
【００５０】図７（Ａ）は、この実施の形態における気
相結晶成長装置のうち、１つのウェハポケット１８に着
目して示した概略断面図及び概略平面図である。ここで
説明する構成例では、この熱伝導度変異部５０として、
例えば、４つの異なる材料から成る熱伝導度変異領域
（６０，６２，６４，６６）をｎ型ＩｎＰ基板１０の区
分領域毎に形成するとともに、この熱伝導度変異部５０
の厚みを実質的に均一となるように形成してある。尚、
領域６８には、適当なガスが存在していても良く、或い
は、熱伝導度変異部５０の一部として形成しても良い。
この実施の形態では、この熱伝導度変異部５０を、例え
ば、４つの縞状に区分してある。FIG. 7A is a schematic cross-sectional view and a schematic plan view showing one wafer pocket 18 in the vapor phase crystal growth apparatus of this embodiment. In the configuration example described here, as the thermal conductivity changing unit 50,
For example, thermal conductivity variation regions (60, 62, 64, 66) made of four different materials are formed for each divided region of the n-type InP substrate 10, and the thermal conductivity variation portion 50 is formed.
Is formed to have a substantially uniform thickness. still,
A suitable gas may be present in the region 68, or may be formed as a part of the thermal conductivity variation section 50.
In this embodiment, the thermal conductivity varying portion 50 is divided into, for example, four stripes.
【００５１】そして、第１の実施の形態と同様の工程を
経て、ウェハ上に半導体発光素子アレイを形成する。Then, the semiconductor light emitting element array is formed on the wafer through the same steps as those in the first embodiment.
【００５２】上述した説明から明らかなように、この実
施の形態では、第１の実施の形態と同様の効果が得られ
る。尚、区分領域の形状は上述のみに限られず、半導体
基板に成長させる結晶層に所望の結晶構造を与えること
が出来るように、半導体基板に温度分布を形成させる形
態ならば良い。この熱伝導度変異部５０は、例えば、図
７（Ｂ）及び（Ｃ）に示す概略平面図のような同心リン
グ状の区分領域（図７（Ｂ）及びセクタ領域（図７
（Ｃ））とした形状であっても、この実施の形態と同様
の効果を得ることが出来る。As is clear from the above description, in this embodiment, the same effect as that of the first embodiment can be obtained. The shape of the sectioned region is not limited to the above, and any shape may be used as long as the temperature distribution is formed in the semiconductor substrate so that the crystal layer grown on the semiconductor substrate can have a desired crystal structure. The thermal conductivity varying portion 50 is, for example, a concentric ring-shaped sectioned region (FIG. 7B) and sector region (FIG. 7) as shown in the schematic plan views of FIGS. 7B and 7C.
Even if the shape is (C), the same effect as this embodiment can be obtained.
【００５３】[0053]
【発明の効果】上述した説明から明らかなように、この
発明によれば、成長させるべき結晶層に応じて、基板の
結晶成長面の温度を、熱伝導度変異部を利用することに
より、より正確に制御できるので、半導体基板上に、複
数の結晶構造（組成）の異なる成長結晶層、例えば、多
重量子井戸構造となる井戸層及び障壁層を設計値通りに
形成でき、製品歩留まりを向上させることができる。As is apparent from the above description, according to the present invention, the temperature of the crystal growth surface of the substrate can be set to a higher value by utilizing the thermal conductivity variation portion in accordance with the crystal layer to be grown. Since it can be controlled accurately, a plurality of growth crystal layers having different crystal structures (compositions), for example, a well layer and a barrier layer having a multiple quantum well structure can be formed on a semiconductor substrate according to design values, and product yield is improved. be able to.
【００５４】従って、回折格子ピッチで決まる発振波長
と結晶構造で決まる利得ピーク波長との差（ディチュー
ニング量）を、従来よりも精度良く制御することができ
るので、高信頼性でかつ広範囲の発振波長をもつ半導体
発光素子アレイを得ることができる。Therefore, the difference (detuning amount) between the oscillation wavelength determined by the diffraction grating pitch and the gain peak wavelength determined by the crystal structure can be controlled more accurately than before, so that the oscillation is highly reliable and in a wide range. A semiconductor light emitting device array having a wavelength can be obtained.
【００５５】また、選択成長用マスクが不要なため製造
工程が減り、従来よりも安価に各半導体発光素子を製造
することができる。Further, since the selective growth mask is unnecessary, the number of manufacturing steps is reduced, and each semiconductor light emitting element can be manufactured at a lower cost than before.
【図１】この発明に用いられる半導体基板を示す図であ
る。FIG. 1 is a diagram showing a semiconductor substrate used in the present invention.
【図２】第１の実施の形態の説明図である。FIG. 2 is an explanatory diagram of the first embodiment.
【図３】第１の実施の形態の説明図である。FIG. 3 is an explanatory diagram of the first embodiment.
【図４】第１の実施の形態の半導体発光素子の製造方法
を説明する図である。FIG. 4 is a diagram illustrating the method for manufacturing the semiconductor light emitting device according to the first embodiment.
【図５】第１の実施の形態における変形例の説明図であ
る。FIG. 5 is an explanatory diagram of a modified example of the first embodiment.
【図６】第２及び第３の実施の形態の説明図である。FIG. 6 is an explanatory diagram of the second and third embodiments.
【図７】第４の実施の形態の説明図である。FIG. 7 is an explanatory diagram of the fourth embodiment.
１０：ｎ型ＩｎＰ基板
１２：回折格子
１４：高速回転型気相結晶成長装置
１６：ウェハキャリア
１８：ウェハポケット
２０：サセプタ
２２：ヒータ
２４：回転軸
２６：凹部（＝熱伝導度変異部５０）
２７，２９：空隙
２８：ウェハポケット底部
３０，３２，３４，３６：領域
３８：多重量子井戸構造用膜
３８'：多重量子井戸構造
３９ａ：光ガイド層用膜
３９ａ'：光ガイド層
３９ｂ：クラッド層用膜
３９ｂ'，４３：クラッド層
４０：エッチングマスク
４２：電流狭窄層
４４：コンタクト層
４６ａ，４６ｂ：切削加工によって形成された段差
４７ａ，４７ｂ：切削加工によって形成された凹部
４８ａ，４８ｂ：ＣＶＤ法及びホトリソグラフィ技術に
よって形成された段差
４９ａ，４９ｂ：ＣＶＤ法及びホトリソグラフィ技術に
よって形成された凸部
５０：熱伝導度変異部
６０，６２，６４，６６：熱伝導度変異領域（＝熱伝導
度変異部５０）
６８：領域10: n-type InP substrate 12: diffraction grating 14: high-speed rotation type vapor phase crystal growth apparatus 16: wafer carrier 18: wafer pocket 20: susceptor 22: heater 24: rotating shaft 26: concave portion (= thermal conductivity changing portion 50) 27, 29: Void 28: Wafer pocket bottom 30, 32, 34, 36: Region 38: Multiple quantum well structure film 38 ': Multiple quantum well structure 39a: Optical guide layer film 39a': Optical guide layer 39b: Clad Layer films 39b ', 43: Cladding layer 40: Etching mask 42: Current confinement layer 44: Contact layers 46a, 46b: Steps 47a, 47b formed by cutting work: Recesses 48a, 48b formed by cutting work: CVD And steps 49a and 49b formed by the photolithography technique: formed by the CVD method and the photolithography technique Convex part 50: Thermal conductivity varying part 60, 62, 64, 66: Thermal conductivity varying region (= thermal conductivity varying part 50) 68: Region
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Claims (9)
列させて半導体発光素子を製造するに当たり、 半導体基板上に、回折格子を複数区分領域に形成し、 前記回折格子を備える前記半導体基板上に結晶成長させ
る際に、前記半導体基板と該半導体基板を加熱する発熱
体との間に、前記半導体基板と前記発熱体との間の熱伝
導度を、前記半導体基板の区分領域毎に異ならせる熱伝
導度変異部を介在させて、前記半導体基板を加熱するこ
とを特徴とする半導体発光素子の製造方法。1. When manufacturing a semiconductor light emitting device by arranging a plurality of semiconductor light emitting devices on a semiconductor substrate, a diffraction grating is formed in a plurality of divided regions on the semiconductor substrate, and the diffraction grating is formed on the semiconductor substrate. A heat for varying the thermal conductivity between the semiconductor substrate and the heating element between the semiconductor substrate and the heating element for heating the semiconductor substrate during crystal growth. A method for manufacturing a semiconductor light emitting device, comprising heating the semiconductor substrate with a conductivity varying portion interposed.
ッチは、隣り合う区分領域内の前記回折格子ごとに異な
っていることを特徴とする請求項１に記載の半導体発光
素子の製造方法。2. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein a grating pitch of each divided region of the diffraction grating is different for each of the diffraction gratings in adjacent divided regions.
記結晶成長させる第１主面とは反対側の第２主面側に設
けていることを特徴とする請求項１または２に記載の半
導体発光素子の製造方法。3. The heating element is provided on the second main surface side of the semiconductor substrate opposite to the first main surface on which the crystal growth is performed, according to claim 1 or 2. Method for manufacturing semiconductor light emitting device.
と、前記熱伝導度変異部が形成された第２主面とを有す
るウェハキャリアを用意し、 前記半導体基板を、該ウェハキャリアを介在させて前記
発熱体に対向配置して、前記半導体基板を加熱すること
を特徴とする請求項１ないし３のいずれか一項に記載の
半導体発光素子の製造方法。4. A wafer carrier having a first main surface on which the semiconductor substrate is placed and a second main surface on which the thermal conductivity varying portion is formed is prepared, and the semiconductor substrate is attached to the wafer carrier. The method for manufacturing a semiconductor light emitting element according to claim 1, wherein the semiconductor substrate is heated by interposing a heating element between the heating element and the heating element.
リアの第２主面に、互いに深さの異なる複数の凹部を形
成して設けることを特徴とする請求項４に記載の半導体
発光素子の製造方法。5. The semiconductor light emitting device according to claim 4, wherein the thermal conductivity changing portion is provided by forming a plurality of concave portions having different depths on the second main surface of the wafer carrier. Manufacturing method.
のうち、前記結晶成長させる第１主面とは反対側の第２
主面に形成することを特徴とする請求項１ないし３のい
ずれか一項に記載の半導体発光素子の製造方法。6. The thermal conductivity variation portion is provided on a second side of the semiconductor substrate opposite to the first major surface on which the crystal is grown.
The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the method is formed on the main surface.
の第２主面に、酸化膜及び窒化膜の双方またはいずれか
一方で、各区分領域ごとに厚みを変えて形成することを
特徴とする請求項６に記載の半導体発光素子の製造方
法。7. The thermal conductivity varying portion is formed on the second main surface of the semiconductor substrate by changing the thickness of each of the divided regions of one or both of an oxide film and a nitride film. The method for manufacturing a semiconductor light emitting device according to claim 6.
の第２主面自体に、各区分領域ごとに深さの異なる複数
の凹部を形成して設けることを特徴とする請求項６に記
載の半導体発光素子の製造方法。8. The thermal conductivity varying portion is provided in the second main surface of the semiconductor substrate itself by forming a plurality of recesses having different depths for each divided region. A method for manufacturing a semiconductor light emitting device as described above.
リアの第１主面と、前記ウェハキャリアは、前記発熱体
と対向する第２主面を有し、 前記熱伝導度変異部を、前記ウェハキャリアの第２主面
と前記発熱体との間に、熱伝導度変異領域を前記半導体
基板の各区分領域毎に、前記熱伝導度が異なるように設
け、 前記半導体基板を、該ウェハキャリアの前記第１主面に
載置して、前記発熱体に対向配置する前記半導体基板の
第２主面を加熱することを特徴とする請求項１ないし３
のいずれか一項に記載の半導体発光素子の製造方法。9. A first main surface of a wafer carrier on which the semiconductor substrate is mounted, and a second main surface of the wafer carrier facing the heating element. Between the second main surface of the wafer carrier and the heating element, a thermal conductivity variation region is provided so that the thermal conductivity is different for each divided region of the semiconductor substrate, and the semiconductor substrate is the wafer carrier. 4. The second main surface of the semiconductor substrate, which is placed on the first main surface of the semiconductor substrate and faces the heating element, is heated.
A method for manufacturing a semiconductor light emitting device according to any one of 1.
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|---|---|---|---|
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|---|---|---|---|
| JP2001274851A JP2003086890A (en) | 2001-09-11 | 2001-09-11 | Method of manufacturing semiconductor light emitting element |
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|---|---|
| JP2003086890A true JP2003086890A (en) | 2003-03-20 |
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ID=19099818
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| JP2001274851A Pending JP2003086890A (en) | 2001-09-11 | 2001-09-11 | Method of manufacturing semiconductor light emitting element |
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| JP2016508668A (en) * | 2013-01-24 | 2016-03-22 | サントル ナスィオナル ド ラ ルシェルシュ スィアンティフィク（セ．エン．エル．エス．） | Method for manufacturing a monolithic white diode |
| JP2017208543A (en) * | 2016-05-13 | 2017-11-24 | オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ | Semiconductor chip manufacturing method and semiconductor chip |
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