JP2003084858A - Information processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing device having an operation mode to lower power consumption in those parts where power supply is impossible or difficult to stop. SOLUTION: This information processing device 10 is equipped with a clock generating circuit 13 capable of changing the frequency of a clock signal CLK to output, and a mechanism (CPU 11 and a data transfer control circuit 12) to supply a signal CNTL indicating output of a clock signal CLK having a lower frequency than a normal one to the clock generating circuit 13 when a normal mode should be switched over to a save power mode, and to supply a signal CNTL indicating output of a clock signal CLK having a normal frequency to the clock generating circuit 13 when the mode should be switched over to the normal mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device including an element that operates based on a clock signal.

[0002]

2. Description of the Related Art In recent years, commercially available printers, FA
X, computer, etc. (hereinafter referred to as information processing device)
Most of the operation of the power-saving mode (also called standby mode, power saving mode), that is, the input of the start instruction of the operation is monitored when the actual non-use time continues for a certain time or more. Power is supplied only to the parts necessary for the operation (the parts necessary for the user to input instructions, input devices such as the operation panel and keyboard, and the interface circuits with other devices to function). It is configured to start the operation in a state where the power supply to the other parts is stopped) and the normal operation is restarted when some operation start instruction is given.

[0003]

The above-mentioned technique used for power saving does not aim at power saving in a portion where power supply cannot be stopped, and also stops power supply. It is only applicable to a device having a possible part.

The present invention has been made in view of such circumstances, and an object of the present invention is to perform information processing having an operation mode in which power consumption is reduced in a portion where reduction or stop of power supply is impossible or difficult. To provide the device.

[0005]

In order to solve the above-mentioned problems, according to the present invention, a clock signal generator for outputting a clock signal to an information processing apparatus, in which the frequency of the clock signal to be output can be externally controlled. Section, one or more processing execution sections that respectively execute specific processing in a form synchronized with the clock signal output by the clock signal generation section, and transition to the power saving mode when the operation mode is the normal mode. When the operation mode is the power saving mode, it monitors the occurrence of the event that should be switched to the normal mode, and when the occurrence of the event that should be switched to the power saving mode is detected, the clock When the processing for outputting the clock signal of the frequency for the normal mode to the signal generator is performed and the occurrence of the event to shift to the normal mode is detected, the Tsu is intended to comprise an operation mode management unit that performs processing for outputting a clock signal of lower power-saving mode frequency than the normal mode frequencies click signal generator.

That is, the information processing apparatus of the present invention has one or more processing execution units that need to be supplied with a clock signal, and has an event, such as no input for a certain period of time, that should enter the power saving mode. It has a mechanism (clock signal generation unit and operation mode management unit) that lowers the frequency of the clock signal supplied to the one or more process execution units when an event occurs. Then, the power consumption of the circuit (processing execution unit) that needs to supply the clock signal decreases as the frequency of the supplied clock signal becomes lower. Therefore, if the configuration of the present invention is adopted, the power supply can be reduced or It is possible to realize an information processing apparatus having an operation mode (power saving mode) in which the power consumption of a portion that cannot be stopped or is difficult is reduced.

Note that the information processing apparatus of the present invention may be realized such that any one of the one or more processing execution units functions as an operation mode management unit.
It may be realized by providing a device that does not receive the supply of the clock signal from the clock signal generator (a device that does not receive the supply of the clock signal or a device that receives the supply of the clock signal from another circuit).

Further, in realizing the information processing apparatus of the present invention, the operation mode management unit outputs the clock signal of the frequency for the normal mode when detecting the occurrence of the event to shift to the power saving mode. A signal for instructing is supplied to the clock signal generator, and when the occurrence of an event to shift to the normal mode is detected, a signal for instructing the output of the clock signal of the power saving mode frequency is supplied to the clock signal generator. When a signal for instructing the output of the clock signal of the power saving mode frequency is supplied as the clock signal generation unit, the frequency of the output clock signal is gradually reduced to the power saving mode frequency. Then, when a signal instructing the output of the clock signal of the normal mode frequency is supplied, the frequency of the output clock signal is set to the normal mode. It may be used as the gradually increased up to a frequency. Further, a clock signal generator that outputs a clock signal of an instructed frequency is used, and an operation mode management unit detects the occurrence of an event to shift to the power saving mode. When the instruction to gradually reduce the frequency to the power saving mode frequency is given to the clock signal generator and the occurrence of the event that should shift to the normal mode is detected, the frequency of the output clock signal is set to the normal mode frequency. It may be possible to use an instruction to give the clock signal generating unit an instruction to gradually raise the clock signal.

By adopting such a configuration, it is possible to realize an information processing apparatus in which each processing execution unit does not malfunction due to a change in the frequency of the clock signal supplied.

Further, when the information processing apparatus of the present invention is configured as an apparatus further provided with one or more type 2 processing execution units capable of reducing or stopping the supply of electric power, an operation mode management unit As a result, when the occurrence of an event to shift to a specific power saving mode is detected, a process for stopping the power supply to one or more second type process executing units is also performed to shift to the normal mode. When the occurrence of a power event is detected, it is desirable to use a device that also performs processing for stopping the supply of power to one or more second type processing execution units.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a block diagram of an information processing apparatus according to an embodiment of the present invention.

The information processing apparatus 10 according to this embodiment is a so-called laser beam printer, and its main components are a CPU 11, a data transfer control circuit 12, a clock generation circuit 13, an SDRAM 14, a ROM 15, a panel control unit 16, An EEPROM 17, a host I / F 18, and a print engine 19 are provided.

The CPU 11 is a control circuit for integrally controlling each section in the information processing apparatus 10. ROM15 is C
It is a non-volatile memory that stores programs executed by the PU 11 and font data used by the CPU 11.
The Panel control unit 16 is a circuit including a group of elements (a plurality of push button switches, a plurality of LEDs and a liquid crystal panel) that form an operation panel provided on the upper surface of the information processing apparatus 10 and their control circuits. . EEPROM17,
It is a rewritable non-volatile memory for storing various operating conditions set by the user of the information processing apparatus 10 and information indicating the usage status of the apparatus itself. Host I /
F18 is a circuit for receiving print data from the host computer (in this embodiment, a parallel interface circuit compliant with IEEE1284).

The print engine 19 is a unit that actually prints on paper. The SDRAM 14 uses the CPU 11 to generate data to be supplied to the print engine 19 from the print data received by the host I / F 18.
Is the memory used by. This SDRAM 14
Is also a memory in which the program is executed (the program stored in the ROM 15 is read).

The data transfer control circuit 12 includes a host I / O.
The print data received by the F18 is transferred to the SDRAM 14
In order to allow the CPU 11 to perform the process of storing in the CPU 14 and the process of supplying the data prepared by the CPU 11 on the SDRAM 14 to the print engine 19 (that is, a simple data transfer process), It is a manufactured ASIC. This data transfer control circuit 12
Is a level (“H” level) instructed by the CPU 11.
or a function of outputting the frequency control signal CNTL of "L" level. The frequency control signal CNTL output from the data transfer control circuit 12 is the clock generation circuit 1
3 is being supplied. The data transfer control circuit 12
When the information processing device 10 is powered on,
The circuit is in a state of outputting the "H" level frequency control signal CNTL.

The clock generation circuit 13 has a clock signal C.
It is a kind of frequency synthesizer that generates LK. As shown in FIG. 2, the clock generation circuit 13 includes an oscillation circuit 21 and a frequency control circuit 22, and the frequency control signal CNTL is input to the frequency control circuit 22.

The oscillating circuit 21 is a circuit which uses a crystal oscillator and outputs a signal of a predetermined frequency. On the other hand, the frequency control circuit 22 receives the frequency control signal CNTL supplied from the data transfer control circuit 12 and the oscillation circuit 21.
The circuit operates as shown in FIGS. 3A and 3B based on the signal supplied from the circuit.

That is, the frequency control circuit 22 is shown in FIG.
As shown in (A), when the "H" level frequency control signal CNTL is input, a 100 MHz clock signal is generated and output based on the signal supplied from the oscillation circuit 21. Then, in the frequency control circuit 22, the level of the input frequency control signal CNTL is “H”.
When changing from "L" to "L", a process of gradually lowering the frequency of the clock signal to be output to 66 MHz is performed, and then a state of continuously outputting the clock signal of 66 MHz is entered.

Further, the frequency control circuit 22 changes the level of the frequency control signal CNTL from "L" to "H" (when outputting a clock signal of 66 MHz,
When the “H” level frequency control signal CNTL is input, as shown in FIG. 3B, after the process of gradually increasing the frequency of the clock signal to be output to 100 MHz, 100 MHz It shifts to the state where it continues to output the clock signal of.

The information processing apparatus 10 according to this embodiment
Then, as the frequency control circuit 22, a circuit that changes the frequency of the clock signal CLK to a target frequency by taking about 5 μs (a circuit that increases or decreases the clock cycle by about 10 ps per 1 clock cycle).
Is used.

Then, the ROM 1 in the information processing apparatus 10
5, the CPU 11 responds to the original process (the process for ejecting the print engine 19 with a print according to the received print data and the user's operation on the operation panel). A program to be executed in parallel with (processing etc.) is recorded.

That is, when the power is turned on, the CPU
11 is a state in which the operation in the normal mode is started and the standby state is monitored for a predetermined time or longer (step S10
Take 1). Here, the standby state means the host I / F 18
Monitoring that print data is received by the Panel
The control unit 16 monitors the detection of an operation on the operation panel, but does not perform any other processing.

When it is detected that the standby state has continued for a certain period of time (step S101; YES), the CPU 11
Performs power saving processing (step S102) for reducing the power consumption of the print engine 19 and the like.
The data transfer control circuit 12 is instructed to output the "L" level frequency control signal CNTL (step S103).

As described above, the information processing apparatus 10
The internal data transfer control circuit 12 has a function of outputting the frequency control signal CNTL of the level (“H” level or “L” level) instructed by the CPU 11, and when the power is turned on, The H "level frequency control signal CNTL is output. Further, the clock generation circuit 13, when supplied with the frequency control signal CNTL of the “L” level, changes the frequency of the clock signal CLK to be output to 6 by taking about 5 μs.
Change to 6MHz. Therefore, when step S103 is executed, the frequency of the clock signal CLK, which was 100 MHz at the time of execution, gradually decreases,
When approximately 5 μs has passed from the execution, 66 MH
It becomes z and becomes stable.

CPU 1 which has completed the processing of step S103
1 starts operation in the power saving mode, and the host I / F 1
8 receives print data, and the Pane
The control unit 16 takes a state (step S104) of monitoring that the operation on the operation panel is detected (in the figure, an input event occurs). And host I / F
18 received print data, or Pa
When the nel control unit 16 recognizes that an operation on the operation panel is detected (step S104; YE
S), the CPU 11 controls the "H" level frequency control signal C
The data transfer control circuit 12 is instructed to output NTL (step S105).

The data transfer control circuit 12 includes a CPU 11
Level instructed by (“H” level or “L” level)
When the frequency control signal CNTL of "H" level is supplied, the clock generation circuit 13 changes the frequency of the clock signal CLK to be output to 100 MHz by taking about 5 μs. Therefore, when this step S105 is executed, the frequency of the clock signal CLK, which was 66 MHz at the time of its execution, gradually increases, and becomes about 100 MHz when about 5 μs has elapsed from the execution, and stabilizes. It will be.

After completing the processing in step S105, the CPU 11 performs the power saving canceling processing (step S106) for operating the print engine 19 and the like in the normal state, and then returns to step S101 to set the standby state again. Take a state of monitoring for a certain time or more.

As described above, in the information processing apparatus 10 according to the present embodiment, the process of lowering the frequency of the clock signal CLK is performed when the standby state continues for a certain time. Therefore, the information processing device 1 in the standby state
The power consumption of 0 is smaller than the power consumption of the information processing device 10 when not in the standby state, because the power consumption of each unit to which the clock signal CLK is supplied is small.

More specifically, for an information processing apparatus that has a portion that can reduce or stop the supply of electric power and that reduces or stops the electric power supply to that portion when shifting to the standby state. If the technique used in the information processing apparatus 10 is applied, the clock signal CL
Since the power consumption of each unit to which K is supplied is reduced, an information processing apparatus that consumes less power than the information processing apparatus can be obtained. Further, when the present technology is applied to an information processing device that does not have a part that can reduce or stop the supply of power, the power saving mode can be applied to an information processing device that does not have a power saving mode until then. Can be given.

Further, the information processing apparatus 10 is constructed so that the frequency of the clock signal CLK is gradually changed. Therefore, the information processing device 10 is also a device in which the CPU 11, the data transfer control circuit 12, and the like do not malfunction due to the frequency change of the clock signal.

<Modifications> The information processing apparatus 10 according to this embodiment can be modified in various ways. For example,
A circuit for outputting a clock signal CLK having a frequency indicated by the supplied analog / digital signal is used as the clock generation circuit 13, and as the data transfer control circuit 12,
The information processing device 10 may be modified so that a circuit for supplying the clock generation circuit 13 with an analog / digital signal for gradually changing the frequency of the clock signal CLK is used. Further, the clock generation circuit 13 is connected to the CPU 1
Alternatively, the designation of the frequency of the clock signal directly output from 1 may be received.

If all circuits to which the clock signal CLK is supplied do not malfunction even when the frequency of the clock signal CLK suddenly changes, the clock signal CLK is used as the clock generation circuit 13. It is possible to use the one that changes the frequency of (1) immediately (at almost "0" time).

In addition, the frequency of the clock signal CLK in the normal state (when operating in the normal mode) and in the standby state (when operating in the power saving mode) is 1 respectively.
Of course, it is not necessary to set the frequency to 00 MHz and 66 MHz, and the technology used in the information processing apparatus 10 may be applied to an apparatus other than the printer.

[0035]

As described above, according to the present invention, it is possible to obtain an information processing apparatus having an operation mode in which power consumption is reduced in a portion where it is impossible or difficult to reduce or stop power supply.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an information processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a clock generation circuit included in the information processing apparatus according to the embodiment.

FIG. 3 is a diagram for explaining a function of a clock generation circuit included in the information processing device according to the embodiment.

FIG. 4 is a flowchart showing a control procedure of the clock generation circuit in the information processing apparatus according to the embodiment.

[Explanation of symbols]

10 Information processing equipment 11 CPU 12 Data transfer control circuit 13 Clock generation circuit 14 SDRAM 15 ROM 16 Panel control unit 17 EEPROM 18 Host I / F 19 print engine 21 Oscillation circuit 22 Frequency control circuit

Claims (4)

[Claims] 1. An information processing apparatus having a normal mode and a power saving mode as operation modes, wherein a frequency of a clock signal to be output, for outputting a clock signal, can be externally controlled. And one or more process execution units that execute specific processes in synchronization with the clock signal output from the clock signal generation unit, and when the operation mode is the normal mode, the power saving mode should be entered. Monitors the occurrence of events, monitors the occurrence of events that should transition to normal mode when the operation mode is power saving mode, and detects the occurrence of events that should transition to power saving mode, When a process for outputting a clock signal of a frequency to the clock signal generation unit is performed and the occurrence of an event to shift to the normal mode is detected, And an operation mode management unit that performs a process for outputting a clock signal of a power saving mode frequency lower than the normal mode frequency to the clock signal generation unit. 2. The operation mode management unit, when detecting the occurrence of an event to shift to the power saving mode, supplies a signal instructing the output of the clock signal of the frequency for the normal mode to the clock signal generation unit. However, when detecting the occurrence of an event to be shifted to the normal mode, the signal for instructing the output of the clock signal of the power saving mode frequency is supplied to the clock signal generating unit, the clock signal generating unit, When the signal instructing the output of the clock signal of the power saving mode frequency is supplied, the frequency of the clock signal to be output is gradually reduced to the power saving mode frequency, and the clock signal of the normal mode frequency is output. When the signal for instructing the output of is supplied, the frequency of the clock signal to be output is gradually increased to the frequency for the normal mode. 1 The information processing apparatus according. 3. The clock signal generation unit outputs a clock signal of an instructed frequency, and the operation mode management unit outputs the clock signal when detecting the occurrence of an event to shift to the power saving mode. An instruction to gradually reduce the frequency of the signal to the frequency for the power saving mode is given to the clock signal generation unit, and when the occurrence of an event to be shifted to the normal mode is detected, the frequency of the clock signal to be output is normally set. The information processing apparatus according to claim 1, wherein an instruction for gradually increasing the frequency for mode is given to the clock signal generator. 4. The system further comprises one or more second-type process execution units capable of reducing or stopping power supply, and the operation mode management unit detects occurrence of an event to shift to a power saving mode. In this case, a process for stopping the supply of electric power to the one or more second type process execution units is also performed, and when the occurrence of an event to be shifted to the normal mode is detected, the one or more second type process execution units are performed. 4. The information processing apparatus according to claim 1, further comprising a process for reducing or stopping the supply of electric power to the second type process executing unit.