JP2002091606A - Device for supplying clock signal and method for controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate two clock signals whose frequencies are different by using one oscillation source for generating a clock signal whose frequencies are relatively low in low power consumption. SOLUTION: A PLL 20 is divided into a first driving part 20A, a second driving part 20B, and a third driving part 20C, and driving signals ON1, ON2, and ON3 are successively supplied by a module. The third driving part 20C is driven when an active lock signal Lock is outputted from a lock judging circuit 25. In this clock signal supplying device, a reference clock signal CLK1 is always supplied to a CPU unit, and an operating clock signal CLK whose frequencies are stabilized is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal supply apparatus suitable for use in, for example, a twin-clock microcomputer driven by a reference clock signal and an operation clock signal, and a control method therefor.

[0002]

2. Description of the Related Art Mobile communication devices such as mobile phones, pagers and cordless phones, OA devices such as word processors, copiers and fax machines, personal computers, OA devices such as peripheral devices for personal computers, televisions, videos, air conditioners and the like. Some electric appliances and remote control devices for remote-controlling these products have a clock function or a timer function, and these devices are equipped with a twin-clock microcomputer.

For example, as an example of these devices, there is a remote control device for controlling the operation of a remote main device (for example, a television) by a remote control signal, and this remote control device is provided with a liquid crystal panel and an infrared transmitting section. ing. The microcomputer mounted on the remote control device has a time & calendar function driven by a reference clock signal (for example, 32.768 kHz) and a remote control signal processing function driven by an operation clock signal (for example, 4 MHz). I have. An operation switch is connected to the input side of the microcomputer, a liquid crystal display driver for controlling and driving the liquid crystal panel, a remote control signal driver for transmitting a remote control signal from the infrared transmitting section, and the like are connected to the output side. Then, when the microcomputer is in a standby state in which the user does not operate the operation switch,
Receiving the reference clock signal, the date and time are displayed on the liquid crystal panel, and in the operation state where the operation switch is operated, the operation clock signal is received and the infrared remote control signal is transmitted from the infrared transmitting section to the main unit. It is to send.

Here, referring to FIGS. 9 and 10,
The connection state of the clock oscillator that drives the microcomputer will be described with reference to two examples. FIG. 9 shows a microcomputer of a twin clock system (hereinafter referred to as CP).
U unit 1000) and a reference clock oscillator 11
0 and the operation clock oscillator 120 are connected.

The CPU unit 1000 has a time & calendar function driven by receiving a reference clock signal from a reference clock oscillator 110, and an operation clock oscillator 1
And a function of operating the apparatus itself in response to the operation clock signal from the control unit 20 (for example, a remote control signal processing function). The reference clock oscillator 110 is, for example, 32.76.
A reference clock signal having a frequency of 8 kHz is generated, and a vibrator X1 including a tuning-fork type crystal vibrator and the like,
An oscillation circuit OSC1 for extracting a stable signal from the vibrator X1 is provided. Operation clock oscillator 1
Reference numeral 20 denotes an oscillator for generating an operation clock signal having a frequency of, for example, 4 MHz.
2 and an oscillation circuit OSC2 for extracting a stable signal from the vibrator X2. The oscillation circuit OSC2 is ON / OFF controlled based on a command signal from the CPU unit 1000.

When the CPU unit 1000 is in a standby state in which the functions of the apparatus itself are not operated, an OFF command signal is output from the CPU unit 1000 to the oscillation circuit OSC2, and the operation clock oscillator 120 From the CPU unit 1000
Stop being supplied to Thus, CPU unit 1000 receives only the reference clock signal from reference clock oscillator 110, and operates only the time & calendar function based on the reference clock signal. At this time, when a liquid crystal display driver and a liquid crystal panel are connected to the CPU unit 1000 as described above, the date and time are displayed on the liquid crystal panel.

On the other hand, in an operation state in which the function of the apparatus itself is operated, an ON command signal is output from the CPU unit 1000 to the oscillation circuit OSC2, and an operation clock signal is supplied from the operation clock oscillator 120. .
Thus, the CPU unit 1000 receives the operation clock signal and causes the device itself to perform a functional operation (for example, an operation of transmitting a remote control signal).

FIG. 10 shows another prior art. In this prior art, the reference clock oscillator 11
Instead of 0, a reference clock oscillator 130 having an RTC (Real Time Clock) is connected to a CPU unit 1000 'of a twin clock system.

The reference clock oscillator 130 is configured as an oscillator X1, an oscillation circuit OSC1, and an RTC having a time and calendar function. In the time & calendar function, the time and calendar are always measured by a low frequency clock, and these information are selectively supplied to the CPU unit 1000 'based on a command signal from the CPU unit 1000'. Here, since the reference clock oscillator 130 is configured as an RTC,
The PU unit 1000 'does not need to have a time & calendar function operated based on the reference clock signal.

[0010]

By the way, in order to generate a high-frequency operation clock signal, an AT (thickness slip) is applied to the vibrator X2 constituting the operation clock oscillator 120.
A quartz crystal resonator or a piezoelectric ceramic resonator is used. These vibrators are mechanically vibrated by vibrator X1.
Since the oscillator oscillates at a much higher frequency, the current consumption of the operation clock oscillator 120 becomes several mA. On the other hand, a tuning fork type crystal resonator or the like is employed as the resonator X1 constituting the reference clock oscillators 110 and 130, and the current consumption thereof is several μA. When an operation clock oscillator 120 that generates an operation clock signal with a high frequency is connected to the CPU unit as in these related arts, there is a problem that the current consumption increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and uses one oscillation source that generates a clock signal of a relatively low frequency to generate two different frequency clock signals with low power consumption. It is an object of the present invention to provide a clock signal supply device that can generate the clock signal and a control method thereof.

[0012]

According to a first aspect of the present invention, there is provided a clock signal supply apparatus for supplying a reference clock signal and an operation clock signal to an external processing unit. An oscillation source for generating the reference clock signal, frequency synthesizer means for multiplying or dividing the reference clock signal to generate the operation clock signal, and a lock signal when the frequency of the operation clock signal is locked. Lock determining means for outputting the operation clock signal to the processing unit, controlling the frequency synthesizer means, and outputting the operation clock signal based on the lock signal. And control means for controlling

According to a second aspect of the present invention, there is provided a clock signal supply device for selectively supplying a reference clock signal or an operation clock signal to an external processing unit, comprising: an oscillation source for generating a reference clock signal having a constant frequency; Frequency synthesizer means for generating an operation clock signal by multiplying or dividing the reference clock signal; lock determination means for outputting a lock signal when the frequency of the operation clock signal is in a locked state; Selection output means for selectively outputting a signal or the operation clock signal, and control means for controlling the frequency synthesizer means and controlling the selection output means based on a command signal and the lock signal from the processing unit. It is characterized by having.

According to a third aspect of the present invention, there is provided a clock signal supply device for selectively supplying a reference clock signal or an operation clock signal to an external processing unit, comprising: an oscillation source for generating a reference clock signal having a constant frequency; Frequency synthesizer means for generating an operation clock signal by multiplying or dividing the reference clock signal, lock determination means for outputting a lock signal when the frequency of the operation clock signal is in a locked state, and the processing unit An operation clock signal output unit for supplying the operation clock signal to the control unit, a selection output unit for selectively outputting the operation clock signal supplied through the reference clock signal or the operation clock signal output unit, and the frequency synthesizer Controlling the operation clock signal output means based on the lock signal. Performs control, is characterized by comprising a control means for controlling said selective output means based on a command signal from the processing unit.

[0015] The invention according to claim 4 is the invention according to claim 1 or 3.
In the clock signal supply device described above, the frequency synthesizer means compares a phase of an input reference clock signal and a phase of a comparison signal to output a phase difference detection signal, and converts the phase difference detection signal to DC. A control signal generator for converting to generate a control signal, a voltage control oscillator for generating a clock signal having a frequency corresponding to the control signal, and a comparator for multiplying or dividing the clock signal to generate the comparison signal And a signal generation unit.

According to a fifth aspect of the present invention, in the clock signal supply device of the fourth aspect, the control means drives the phase comparison section, the control signal generation section, the comparison signal generation section, and the lock determination section. A drive unit, a second drive unit for driving the voltage controlled oscillator, and a third drive unit for driving the operation clock signal output unit when a lock signal is output from the lock determination unit. It is characterized by.

According to a sixth aspect of the present invention, in the clock signal supply device of the second aspect, the frequency synthesizer means compares the phases of the input reference clock signal and the comparison signal to output a phase difference detection signal. A phase comparison unit,
A control signal generation unit that converts the phase difference detection signal into direct current to generate a control signal, a voltage control oscillation unit that generates a clock signal having a frequency corresponding to the control signal, and multiplies or divides the clock signal. And a comparison signal generation section for generating the comparison signal.

According to a seventh aspect of the present invention, in the clock signal supply device of the sixth aspect, the control means drives the phase comparison section, the control signal generation section, the comparison signal generation section, and the lock determination section. And a second driving unit for driving the voltage controlled oscillation unit.

The invention according to claim 8 is the invention according to claim 4 or 6.
In the clock signal supply device described above, the lock determination unit determines the lock state of the operation clock signal based on whether a control signal output from a control signal generation unit is within a predetermined range. .

According to a ninth aspect of the present invention, in the clock signal supply device according to the first, second or third aspect, an RTC (Real Tim Clock) for controlling the control means to measure at least one of a clock operation and a calendar operation by a reference clock signal.
e Clock) circuit.

According to a tenth aspect of the present invention, in the clock signal supply device according to the first, second or third aspect, the control means is provided in an RTC (Real Time Clock) circuit which performs an operation of clocking by the reference clock signal. It is characterized by that.

According to an eleventh aspect of the present invention, in the clock signal supply device according to the first, second or third aspect, the oscillation source includes a piezoelectric vibrator and an oscillation circuit for extracting a stable signal from the piezoelectric vibrator. It is characterized by having.

According to a twelfth aspect of the present invention, in the clock signal supply device according to the eleventh aspect, the piezoelectric vibrator comprises:
It is characterized by being a tuning fork type crystal resonator.

According to a thirteenth aspect of the present invention, in the clock signal supply device of the first, second or third aspect, the frequency synthesizer means can generate the operation clock signals having different frequencies by changing the set value. Means, wherein the control means comprises setting means for setting a set value for oscillating at a predetermined frequency from the plurality of set values in the frequency synthesizer means.

According to a fourteenth aspect of the present invention, there is provided an oscillation source for generating a reference clock signal having a constant frequency, a frequency synthesizer circuit for generating the operation clock signal by multiplying or dividing the reference clock signal, and When the frequency of the clock signal is in a locked state, the lock determination circuit outputs a lock signal, the operation clock signal output circuit supplies the operation clock signal to the processing unit, and controls the frequency synthesizer circuit. A control circuit for controlling the operation clock signal output circuit based on the lock signal, wherein the frequency synthesizer circuit compares a phase of the input reference clock signal with a phase of the comparison signal and outputs a phase difference detection signal. And a control signal for converting the phase difference detection signal into direct current to generate a control signal. A generation unit, a voltage control oscillator that generates a clock signal having a frequency corresponding to the control signal, and a comparison signal generation unit that generates the comparison signal by multiplying or dividing the clock signal. A method for controlling a clock signal supply device that supplies a clock signal and an operation clock signal to an external processing unit, comprising: a first driving step of driving the phase comparison unit, the control signal generation unit, the comparison signal generation unit, and a lock determination circuit A second driving step of driving the voltage controlled oscillator, and a third driving step of driving the operation clock signal output circuit when a lock signal is output from the lock determination circuit. And

According to a fifteenth aspect of the present invention, there is provided an oscillation source for generating a reference clock signal having a constant frequency, a frequency synthesizer circuit for generating an operation clock signal by multiplying or dividing the reference clock signal, and A lock determination circuit that outputs a lock signal when the frequency of the signal is in a locked state; a selection output circuit that selectively outputs the reference clock signal or the operation clock signal; and a control unit that controls the frequency synthesizer circuit and performs the processing. A control circuit for controlling the selection output circuit based on a command signal from the unit and the lock signal, wherein the frequency synthesizer circuit compares a phase of an input reference clock signal with a phase of a comparison signal to detect a phase difference. A phase comparison unit for outputting a signal, and a control signal generated by converting the phase difference detection signal into direct current A control signal generating unit for generating a clock signal having a frequency corresponding to the control signal, and a comparison signal generating unit for generating the comparison signal by multiplying or dividing the clock signal. And a control method of a clock signal supply device for selectively supplying a reference clock signal or an operation clock signal to an external processing unit, wherein the control circuit includes the phase comparison unit, a control signal generation unit, and a comparison signal generation unit. A first driving step of driving the lock determination circuit; and a second driving step of driving the voltage controlled oscillator.

The invention according to claim 16 is an oscillation source for generating a reference clock signal having a constant frequency, a frequency synthesizer circuit for generating an operation clock signal by multiplying or dividing the reference clock signal, and the operation clock. A lock determination circuit that outputs a lock signal when the frequency of the signal is in a locked state; an operation clock signal output circuit that supplies the operation clock signal to the processing unit; and the reference clock signal or the operation clock signal A selection output circuit that selectively outputs the operation clock signal supplied through an output circuit, and controls the frequency synthesizer circuit, controls the operation clock signal output circuit based on the lock signal, and performs processing from the processing unit. Control means for controlling the selection output circuit based on the command signal of The frequency synthesizer circuit compares a phase of an input reference clock signal with a phase of a comparison signal and outputs a phase difference detection signal, and generates a control signal by converting the phase difference detection signal into direct current. A control signal generator, a voltage control oscillator that generates a clock signal having a frequency corresponding to the control signal, and a comparison signal generator that generates the comparison signal by multiplying or dividing the clock signal. A control method of a clock signal supply device for selectively supplying a reference clock signal or an operation clock signal to an external processing unit, the method comprising driving the phase comparison unit, control signal generation unit, comparison signal generation unit, and lock determination circuit A first driving step of driving the voltage-controlled oscillator, and a second driving step of driving the voltage-controlled oscillator. It is characterized by comprising a third drive step for driving the click signal output circuit.

The invention according to claim 17 is the invention according to claims 14 and 1
17. The control method of the clock signal supply device according to 5 or 16, wherein the lock signal output from the lock determination circuit is monitored, and the lock signal is activated even after a predetermined time has elapsed from the start of operation of the clock signal supply device. If not, a step of diagnosing the clock signal supply device as a failure is provided.

The invention according to claim 18 is the invention according to claims 14 and 1
17. The method of controlling a clock signal supply device according to claim 5 or 16, wherein the control signal output from the control signal generator deviates from a predetermined range to diagnose the clock signal supply device as a failure. It is characterized by having provided.

[0030]

Next, a preferred embodiment of the present invention will be described with reference to the drawings.

[1] First Embodiment [1.1] Schematic Configuration of First Embodiment FIG. 1 shows a clock signal supply device 10 according to a first embodiment.
Is shown. This clock signal supply device 10
Are mobile communication devices such as mobile phones, pagers, cordless phones, word processors, copiers, fax machines, etc.
A device, a personal computer, OA devices such as peripheral devices of this personal computer, electric appliances such as a television, a video, an air conditioner, etc., and a clock for driving a microcomputer mounted on a remote control device for controlling these products by remote control. Things. Next, details of the clock signal supply device 10 will be described. The clock signal supply device 10 includes an RTC 11 and a PLL (Phase
Locked Loop) 20.

[1.2] Configuration of RTC 11 Here, the RTC 11 is for extracting a vibrator X composed of a tuning-fork type crystal vibrator or the like and a stable reference clock signal CLK1 (for example, 32.768 kHz) from the vibrator X. Clock oscillator 12 comprising an oscillator circuit OSC
Receiving the reference clock signal CLK1 from the reference clock oscillator 12,
PLL for controlling calendar function and operation of PLL 20
And a module 13 having a control processing function. The module 13 is provided with a register 14.

Then, the reference clock oscillator 12
The reference clock signal CLK1 is directly supplied to the U unit 1000 ', and is also supplied to the module 13 and the PLL 20. The module 13 receives the reference clock signal C
In response to LK1, the time and calendar function is operated. This time & calendar function is to always keep time and calendar by the reference clock signal CLK1, and to selectively supply these information to the CPU unit 1000 'based on a command signal from the CPU unit 1000'. On the other hand, the PLL control processing function of the module 13 will be described later.

[1.3] Configuration of PLL 20 As shown in FIG.
3 and a predetermined frequency (for example, 4M
(Hz) operating clock signal CLK2.

The PLL 20 compares the phase of the input reference clock signal CLK1 with the phase of the comparison signal and outputs a phase difference detection signal. The phase comparator 21 converts the phase difference detection signal into a direct current to control a control signal. (Hereinafter referred to as LPF) 22, a voltage controlled oscillator (hereinafter referred to as VCO) 23 for generating a control clock signal having a frequency corresponding to the control signal, and the control clock signal supplied from the module 12. And a programmable frequency divider 24 for multiplying or dividing based on the set value N to generate the comparison signal.
The lock determination circuit 25 outputs a lock signal when the frequency of the control clock signal is within a predetermined frequency range, and supplies the control clock signal as an operation clock signal CLK2 to the CPU unit 1000 '. Is provided.
In this embodiment, the phase comparator 21 is provided with a charge pump 21A.

Here, of the PLL 20, the phase comparator 2
1, a control clock signal (frequency: N × 32.7) by the LPF 22, the VCO 23 and the programmable frequency divider 24
Since the generation operation at 68 kHz) is general, the details thereof are omitted.

In the PLL 20 according to the present embodiment, this P
The individual circuits constituting the LL 20 are sequentially driven and controlled by drive signals ON1, ON2, and ON3 supplied from the module 13. Therefore, in the PLL 20, the phase comparator 21, the LPF 22, the programmable frequency divider 24, and the lock determination circuit 25 are divided into a first driving unit 20A, the VCO 23 is divided into a second driving unit 20B, and the buffer 26 is divided into a third driving unit 20C. .

Next, the signals supplied from the module 13 to the PLL 20 will be described. Drive signal ON1, ON
2, the voltage value of ON3 is a value VCC necessary for driving each circuit. The set value N sets the frequency division ratio of the programmable frequency divider 24. By changing the set value N, the frequency of the operation clock output from the PLL 20 is set in multiple stages. DF
The signal sets the cut-off frequency f0 of the LPF 22, and this f0 is a value emphasizing the lock-up time and the frequency stability, which are in a trade-off relationship.

[1.4] Operation of Lock Judgment Circuit 25 Next, the lock state detection operation of the lock judgment circuit 25 will be described with reference to FIG. This FIG.
The relationship between the control signal (DC voltage) output from the controller 22 and the phase difference is displayed. That is, the voltage of the control signal is 0
In the case of [V], the phase difference is “0 °”, and in this case, the control clock signal output from the VCO 23 has a predetermined frequency. When the voltage of the control signal is V ⁺ [V], the phase difference is “−180 °”, and when the voltage of the control signal is V ⁻ [V], the phase difference is “180 °”. Then, the lock determination circuit 25 compares the voltage value of the control signal output from the LPF 22 with a predetermined range (−Vx to + Vx), thereby obtaining the VCO 2
It monitors whether or not the frequency of the control clock signal output from 3 is set to a predetermined frequency. The lock determination circuit 25 sets the lock state when the value of the control signal is within a predetermined range (−Vx to + Vx) for a predetermined time by a window comparator, and sends the activated lock signal Lock to the module 13. Output.

[1.5] PL by module 13
Control processing of L20 Next, PLL2 by the module 13 according to the present embodiment
The control operation of 0 will be described based on the flowchart of FIG.

Supply of the drive signal ON1 First, the module 13 sends the drive signal O to the first drive section 20A.
N1 is supplied (step S1). Thereby, the phase comparator 21, the LPF 22, the programmable frequency divider 24, and the lock determination circuit 25 are driven. At this time, VCO2
3 is not driven, no comparison signal is output from the programmable frequency divider 24, and the current consumption is mainly consumed by the charge pump 21A of the phase comparator 21 and the frequency f
Will be charged to the side that becomes “+”.

Supply of Drive Signal ON2 Next, after a predetermined time has elapsed, the module 13
The drive signal ON2 is supplied to 0B (step S2). As a result, the VCO 23 is driven to generate a control clock signal having a frequency f based on the control signal output from the LPF 23. And the programmable frequency divider 24
Then, the count is started in response to the control clock signal. Therefore, current consumption increases in the VCO 23 and the programmable frequency divider 24. Then, the module 13 starts the timer T (step S
3).

Supply of drive signal ON3 Further, the module 13 monitors whether an active lock signal Lock is supplied from the lock determination circuit 25 (step S4), and keeps this state (drive signals ON1, ON2) until supplied. Is maintained) (step S4; NO), and it is determined whether the timer T has passed a predetermined time T0 (step S5). Here, when the lock signal Lock is supplied (step S4; Y
ES), the drive signal ON3 is supplied to the third drive unit 20C (step S6). Thereby, the buffer 26 is driven to supply the control clock signal supplied from the VCO 23 to the buffer 26 to the CPU unit 1000 'as the operation clock signal CLK2.

On the other hand, if the lock signal Lock is not supplied even after the timer T has passed the predetermined time T0, the module 13 determines that the PLL 20 has failed (step S7), and ends this processing. . At this time, in order to stop supplying the drive signal ON3 to the buffer 26 (third driver 20C), supply of the operation clock signal CLK2 is forcibly prohibited.

[1.6] Effects of the First Embodiment As described above, the clock signal supply device 1 according to the present embodiment.
0 is composed of an RTC 11 and a PLL 20 having one reference clock oscillator 12 for generating a reference clock signal CLK1 having a relatively low frequency (32.768 kHz), so that the reference clock signal CLK1 and the operation clock signal having different frequencies are provided. Generate CLK2. The current consumption of the RTC 11 and the PLL 20 is smaller than the current consumption of the conventional operation clock oscillator 120. For this reason, the clock signal supply device 10 according to the present embodiment greatly reduces the current consumption as compared with the case where both the reference clock oscillator 110 and the operation clock oscillator 120 are used to drive the CPU unit as in the related art. Can be done.

In the clock signal supply device 10, P
The lock judgment circuit 25 is provided in the LL 20 and the PLL
20 is divided into a first driving unit 20A, a first driving unit 20B, and a third driving unit 20C, and are sequentially driven by driving signals ON1, ON2, and ON3 supplied from the module 13. Thereby, the clock signal supply device 10
Can drive the buffer 26 and supply the operation clock signal CLK2 to the CPU unit 1000 'after the frequency of the control clock signal output from the VCO 23 is locked, thereby suppressing the frequency fluctuation of the operation clock signal CLK2. can do.

In addition, since the PLL 20 is driven in multiple stages, the driving units 20A, 20B, and 20C are reliably operated, and the operation clock signal CLK2 is output. The time required for the operation clock signal CLK2 to rise to a stable state can be greatly reduced as compared with the case where the frequency of the operation clock signal CLK2 is stabilized by driving at one time.

Further, the reference clock oscillator 12 not only generates the reference clock signal CLK1 but also is used as an oscillation source of the PLL 20 for generating the operation clock signal CLK2.
Since the timing circuit and the like are shared by having the control processing function of (1), cost can be reduced.

The PLL control processing by the module 13 includes the failure judgment of the PLL 20 as shown in steps S3, S4, S5 and S7 in FIG. 4 to diagnose the failure of the clock signal supply device 10. Thereby, the reliability of the device can be improved.

[1.7] Modification of First Embodiment [1.7-1] Modification 1 In the first embodiment, the time during which the lock signal Lock does not become active is measured and the clock signal supply device 10 fails. Although the diagnosis is performed, the present invention is not limited to this. As shown in FIG. 5, a predetermined range (−Vx to + Vx) is determined.
A second predetermined range (−Vy to + Vy) larger than Vx) may be set, and a failure may be diagnosed when the control signal becomes larger than this range (−Vy to + Vy).

[1.7.2] Modification 2 In the first embodiment, the module 13 having the time & calendar function for performing the time & calendar operation is used as the control function of the PLL.
However, the present invention is not limited to this, and the RTC 51 of the clock signal supply device 50 shown in FIG.
As described above, the module 52 having a timer function of performing a time measurement operation may be provided.

[2] Second Embodiment The feature of the clock signal supply device according to the present embodiment is that the reference clock signal CLK1 or the operation clock signal CLK2
Is selectively supplied. The same components as those in the first embodiment described above are denoted by the same reference numerals, and description thereof will be omitted.

[2.1] Schematic Configuration of Second Embodiment FIG. 7 shows a clock signal supply device 60 according to the second embodiment.
Is shown. The clock signal supply device 60 includes a reference clock oscillator 1 that generates a reference clock signal CLK1.
2, a PLL 61 that receives the reference clock signal CLK1 and generates the operation clock signal CLK2, a selection circuit 62 that selects and outputs the reference clock signal CLK1 or the operation clock signal CLK2, and a controller 63 that controls the selection circuit 62. It is roughly configured by:

[2.2] Configuration of PLL 61 Also, the PLL 61
The frequency synthesizer is configured to generate an operation clock signal CLK2 having a predetermined frequency (for example, 4 MHz) in response to the signal.

The PLL 61 includes an M frequency divider 64 for outputting a frequency-divided signal obtained by dividing the input reference clock signal CLK1 by M, a phase comparator 21 for detecting a phase difference between the frequency-divided signal and the comparison signal, and , LPF 22, a VCO 23, and a programmable frequency divider 24.
1 is provided with a lock determination circuit 25.

In the PLL 61, each of the constituent circuits is driven by a drive signal ON supplied from the controller 63.
1 and ON2, the M divider 64, the phase comparator 21, the LPF 22, the programmable divider 24, and the lock determination circuit 25 are connected to the first drive unit 61.
A, VCO 23 is divided into a second drive unit 61B.
The driving units 61A and 61B are driven in sequence by the sequentially supplied driving signals ON1 and ON2, thereby speeding up the rise of the operation clock signal.

[2.3] Selection Circuit 62 The selection circuit 62 selects and outputs the reference clock signal CLK1 from the reference clock oscillator 12 or the operation clock signal CLK2 from the PLL 61, and outputs the instruction signal from the controller 63. A clock signal is selectively output based on the clock signal.

[2.4] Controller 63 The controller 63 has a lock determination circuit 25 on its input side.
And a CPU unit (not shown), and a selection circuit 62 is connected to the output side. Then, the controller 63 outputs the lock signal Loc from the lock determination circuit 25.
k, and only when the lock signal Lock is active and a command signal requesting an operation clock signal is supplied from the CPU unit, an instruction signal for switching the clock signal to the operation clock signal CLK2 toward the selection circuit 62 is output. Output. Further, as described in the first embodiment, the controller 63 controls the lock determination circuit 2
If the lock signal Lock from No. 5 does not become active even after the elapse of a predetermined time, it is determined that the PLL 61 is out of order and transmitted to the CPU unit.

[2.5] Effects of the Second Embodiment In the clock signal supply device 60 configured as described above, the driving signals ON1 and ON1 from the controller 63 are divided into two driving units 61A and 61B of the PLL 61. ON2
Thus, the same effects as those of the clock signal supply device 10 according to the above-described first embodiment can be obtained. Moreover, the controller 63 controls the selection circuit 62 based on the lock signal Lock signal. Therefore, in the clock signal supply device 60, C
Even when the command signal from the PU unit requests the operation clock signal, supply of the operation clock signal output from the PLL 61 can be prohibited if the operation clock signal is not in the locked state.

[2.6] Modification of Second Embodiment A clock signal supply device 60 'according to this modification is shown in FIG. In this modified example, the buffer 26 described in the first embodiment is provided in the PLL 61 ′, and the driving of the buffer 26 is controlled as a third driving unit 61C by a driving signal ON3 output from the controller 63. As described above, in the case where the clock supply device 60 ′ is configured, the buffer 26 is driven when the operation clock signal is locked, and the operation clock signal having a stable frequency is supplied to the selection circuit 62. It becomes possible to supply.

[3] Modifications In the clock signal supply device according to each of the above-described embodiments, the frequency of the reference clock signal CLK1 is set to 32.76.
8 kHz, the frequency of the operation clock signal CLK2 is 4 MHz
z, but is not limited to this. In particular, the operation clock signal CLK2 can be arbitrarily set by the set value N.

As described above, the clock signal supply device according to the present invention uses one oscillating source for generating a clock signal having a relatively low frequency to reduce two different frequency clock signals. Generate by power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a clock supply device according to a first embodiment.

FIG. 2 is a block diagram illustrating a configuration of a PLL according to the embodiment.

FIG. 3 is a diagram illustrating a relationship between a control signal and a phase difference.

FIG. 4 is a flowchart showing a PLL control process according to the embodiment.

FIG. 5 is a diagram illustrating a relationship between a control signal and a phase difference according to a modification of the first embodiment.

FIG. 6 is a block diagram illustrating a clock supply device according to a modification of the first embodiment.

FIG. 7 is a block diagram illustrating a clock supply device according to a second embodiment.

FIG. 8 is a block diagram illustrating a clock supply device according to a modification of the second embodiment.

FIG. 9 is a block diagram showing a connection state of a clock oscillator according to the related art.

FIG. 10 is a block diagram showing a connection state of a clock oscillator according to another conventional technique.

[Explanation of symbols]

 10, 50, 60, 60 ′ clock signal supply device 11, 51 RTC 12 reference clock oscillator 13, 52 module 14, 53 register 20, 20, 61 ′ PLL 20A, 61A first drive unit 20B .., 61B... Second drive unit 20C, 61C... Third drive unit 21... Phase comparator 22... LPF 23...

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (18)

[Claims] 1. A clock signal supply device for supplying a reference clock signal and an operation clock signal to an external processing unit, comprising: an oscillation source for generating a reference clock signal having a constant frequency; Frequency synthesizer means for generating the operation clock signal by circulating the clock signal; lock determination means for outputting a lock signal when the frequency of the operation clock signal is in a locked state; and A clock signal supply device, comprising: an operation clock signal output unit for supplying the clock signal; and a control unit for controlling the frequency synthesizer unit and controlling the operation clock signal output unit based on the lock signal. . 2. A clock signal supply device for selectively supplying a reference clock signal or an operation clock signal to an external processing unit, comprising: an oscillation source for generating a reference clock signal having a constant frequency; Frequency synthesizer means for generating an operation clock signal by multiplying or dividing; lock determination means for outputting a lock signal when the frequency of the operation clock signal is in a locked state; and the reference clock signal or the operation clock signal Selection output means for selecting and outputting, and control means for controlling the frequency synthesizer means and controlling the selection output means based on a command signal and the lock signal from the processing unit. Clock signal supply device. 3. A clock signal supply device for selectively supplying a reference clock signal or an operation clock signal to an external processing unit, comprising: an oscillation source for generating a reference clock signal having a constant frequency; Frequency synthesizer means for multiplying or dividing to generate an operation clock signal, lock determination means for outputting a lock signal when the frequency of the operation clock signal is in a locked state, and the operation clock for the processing unit An operation clock signal output unit for supplying a signal; a selection output unit for selectively outputting the operation clock signal supplied through the reference clock signal or the operation clock signal output unit; a control of the frequency synthesizer unit; While controlling the operation clock signal output means based on the signal, A clock signal supply device comprising: control means for controlling the selection output means based on a command signal from the processing unit. 4. The clock signal supply device according to claim 1, wherein the frequency synthesizer compares the phases of the input reference clock signal and the comparison signal and outputs a phase difference detection signal. A control signal generation unit that converts the phase difference detection signal into direct current to generate a control signal, a voltage control oscillation unit that generates a clock signal having a frequency corresponding to the control signal, and multiplies or separates the clock signal. A clock signal supply device, comprising: a comparison signal generation unit configured to generate the comparison signal around the clock signal. 5. The clock signal supply device according to claim 4, wherein the control unit is configured to drive the phase comparison unit, the control signal generation unit, the comparison signal generation unit, and the lock determination unit, and the voltage includes: A second drive unit for driving the control oscillator, and when a lock signal is output from the lock determination unit,
And a third driving means for driving the operation clock signal output means. 6. The clock signal supply device according to claim 2, wherein the frequency synthesizer compares a phase of an input reference clock signal with a phase of a comparison signal and outputs a phase difference detection signal. A control signal generation unit that converts the phase difference detection signal into direct current to generate a control signal, a voltage control oscillation unit that generates a clock signal having a frequency corresponding to the control signal, and multiplies or divides the clock signal. A comparison signal generation unit for generating the comparison signal. 7. The clock signal supply device according to claim 6, wherein the control unit is configured to drive the phase comparison unit, the control signal generation unit, the comparison signal generation unit, and the lock determination unit, and the voltage includes: A clock signal supply device comprising: a second driving unit that drives a control oscillation unit. 8. The clock signal supply device according to claim 4, wherein the lock determination unit is configured to determine the operation clock signal based on whether a control signal output from the control signal generation unit is within a predetermined range. A clock signal supply device for determining a lock state of the clock signal. 9. The clock signal supply device according to claim 1, wherein the control means clocks at least one of a clock operation and a calendar operation by a reference clock signal.
(Real Time Clock) A clock signal supply device provided in a circuit. 10. The clock signal supply device according to claim 1, wherein said control means is provided in an RTC (Real Time Clock) circuit which performs an operation of timing by said reference clock signal. Clock signal supply device. 11. The clock signal supply device according to claim 1, wherein the oscillation source includes a piezoelectric vibrator and an oscillation circuit for extracting a stable signal from the piezoelectric vibrator. Characteristic clock signal supply device. 12. The clock signal supply device according to claim 11, wherein the piezoelectric vibrator is a tuning-fork type crystal vibrator. 13. The clock signal supply device according to claim 1, wherein the frequency synthesizer means is capable of generating the operation clock signals having different frequencies by changing a set value thereof, and A clock signal supply device, comprising: a setting unit that sets a set value for oscillating at a predetermined frequency from the plurality of set values in the frequency synthesizer unit. 14. An oscillation source for generating a reference clock signal having a fixed frequency, a frequency synthesizer circuit for generating the operation clock signal by multiplying or dividing the reference clock signal, and locking the frequency of the operation clock signal. When in the state, a lock determination circuit that outputs a lock signal, an operation clock signal output circuit that supplies the operation clock signal to the processing unit, and controls the frequency synthesizer circuit, and controls the lock signal. A control circuit for controlling the operation clock signal output circuit based on the reference signal, wherein the frequency synthesizer circuit compares a phase of the input reference clock signal with a phase of the comparison signal and outputs a phase difference detection signal. A control signal generating unit that converts the phase difference detection signal into direct current to generate a control signal; A voltage-controlled oscillating unit for generating a clock signal having a frequency corresponding to the signal, and a comparison signal generating unit for multiplying or dividing the clock signal to generate the comparison signal, wherein a reference clock signal and an operation clock signal are provided. A control method of a clock signal supply device for supplying a clock signal to an external processing unit, comprising: a first driving step of driving the phase comparison unit, the control signal generation unit, the comparison signal generation unit, and the lock determination circuit; A second driving step of driving the unit, and when a lock signal is output from the lock determination circuit,
And a third driving step of driving the operation clock signal output circuit. 15. An oscillation source for generating a reference clock signal having a constant frequency, a frequency synthesizer circuit for generating an operation clock signal by multiplying or dividing the reference clock signal, and a state in which the frequency of the operation clock signal is locked. When is, a lock determination circuit that outputs a lock signal, a selection output circuit that selectively outputs the reference clock signal or the operation clock signal, and controls the frequency synthesizer circuit, and a command signal from the processing unit and A control circuit for controlling the selection output circuit based on the lock signal, wherein the frequency synthesizer circuit compares a phase of an input reference clock signal with a phase of a comparison signal and outputs a phase difference detection signal. Department and
A control signal generation unit that converts the phase difference detection signal into direct current to generate a control signal, a voltage control oscillation unit that generates a clock signal having a frequency corresponding to the control signal, and multiplies or divides the clock signal. A comparison signal generation unit that generates the comparison signal by using a clock signal supply device that selectively supplies a reference clock signal or an operation clock signal to an external processing unit. A first driving step of driving the phase comparison section, the control signal generation section, the comparison signal generation section, and the lock determination circuit; and a second driving step of driving the voltage control oscillation section. A method for controlling a clock signal supply device. 16. An oscillation source for generating a reference clock signal having a constant frequency, a frequency synthesizer circuit for generating an operation clock signal by multiplying or dividing the reference clock signal, and a state in which the frequency of the operation clock signal is locked. A lock determination circuit that outputs a lock signal, an operation clock signal output circuit that supplies the operation clock signal to the processing unit, and a lock determination circuit that outputs the lock signal through the reference clock signal or the operation clock signal output circuit. A selection output circuit for selecting and outputting the operation clock signal to be performed, controlling the frequency synthesizer circuit, controlling the operation clock signal output circuit based on the lock signal, and controlling the operation clock signal based on a command signal from the processing unit. Control means for controlling the selection output circuit, the frequency synthesizer comprising: The circuit includes a phase comparison unit that compares a phase of an input reference clock signal and a phase of a comparison signal to output a phase difference detection signal, and a control signal generation unit that converts the phase difference detection signal into direct current to generate a control signal. A voltage control oscillator for generating a clock signal having a frequency corresponding to the control signal; and a comparison signal generator for multiplying or dividing the clock signal to generate the comparison signal. A method for controlling a clock signal supply device for selectively supplying a signal or an operation clock signal to an external processing unit, the method comprising: driving a phase comparison unit, a control signal generation unit, a comparison signal generation unit, and a lock determination circuit. A driving step; a second driving step of driving the voltage controlled oscillator; and when a lock signal is output from the lock determination circuit,
And a third driving step of driving the operation clock signal output circuit. 17. The method of controlling a clock signal supply device according to claim 14, 15, or 16, wherein a lock signal output from the lock determination circuit is monitored, and a predetermined time has elapsed from the start of operation of the clock signal supply device. A step of diagnosing the clock signal supply device as a failure if the lock signal does not become active even if the lock signal does not become active. 18. The control method for a clock signal supply device according to claim 14, 15, or 16, wherein the control signal output from the control signal generation unit deviates from a predetermined range. A method for controlling a clock signal supply device, comprising a step of diagnosing a failure of the signal supply device.