JP2003078401A - Controller of power mos transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a controller of a power MOS transistor capable of suppressing noise and heat generation with a new configuration. SOLUTION: The power MOS transistor 1 and a load 2 are serially connected to a power source Vcc, and voltage is applied to a gate terminal of the power MOS transistor 1 to cause current of a pulse shape in which a rise and a fall become in a slope shape to flow to the load 2. A circuit 5 for detecting voltage between a gate and a source detects voltage Vgs between a gate and a source of the power MOS transistor in accordance with voltage application to a gate terminal of the power MOS transistor. A control logic 4 calculates deviation between rise and fall times Tup and Tdown and a target value in a conductive current waveform of the load 2 of this time from the voltage Vgs between the gate and the source and performs feedback control of the power MOS transistor so as to eliminate the deviation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOS transistor control device.

[0002]

2. Description of the Related Art An example of a conventional power MOS transistor control device is shown in FIG. In FIG. 9, the power MOS transistor 50 and the load 51 are connected in series to the power supply Vcc, and the power MOS transistor 50 is PWM-controlled by the pulse wave generation circuit 52 and the non-inverting amplifier circuit 53 so that a predetermined current i is applied to the load 51. Can be flushed. However, in such a case, there is a problem that the current i flowing through the load 51 changes greatly when the power MOS transistor 50 is switched and a large noise is generated. This is because the time change di / dt of the current is proportional to the noise amount. As a countermeasure, instead of the pulse current waveform of FIG. 10A, a method of tilting the current during PWM control as shown in FIG. 10B to reduce the current fluctuation di / dt with respect to time to reduce noise Is proposed. As the circuit configuration, a trapezoidal wave generation circuit that replaces the pulse wave generation circuit 52 of FIG. 9 outputs a trapezoidal waveform voltage. A voltage similar in shape to this waveform is applied to the load 51, and the energizing current i of the load 51 is a value obtained by dividing this voltage by the load resistance. Therefore, when the load resistance is constant, it is possible to output a current having a waveform similar to the waveform created by the trapezoidal wave generation circuit.

However, in the case of a load, such as a lamp, in which a current that is 10 times as high as the normal current flows at the moment of lighting, the load resistance at the time of lighting is very low, so that there is a problem that an extremely large current gradient occurs and noise is generated. . Therefore, Japanese Patent Laid-Open No. 2000-
Japanese Patent No. 138570 proposes a method of controlling with a current instead of a voltage of a load.

However, when such a method is adopted, the current gradient di / dt takes a certain constant value (di / dt) const as shown in FIG. The load current imax changes (imax1>
imax2), the time T during which the current i is inclined changes. Specifically, when the load current is large, the tilt time T (= T1)
Is long and the load current is small, the slope time T (= T
2) becomes shorter. In this case, since the current gradient di / dt is constant, the amount of noise is constant.

Here, attention is paid to the time T during which the current i is inclined. If the slope di / dt of the current with respect to time is small, noise is reduced, but there is a demerit that heat generation of the power MOS transistor is increased. This is for the following reason. The power MOS transistor is normally used in the linear region (non-saturation region). In this linear region, the gate-source voltage is large and the drain-source voltage is small. On the other hand, while the current i is inclined, T uses the saturation region of the power MOS transistor, and in this saturation region, the gate-source voltage is small,
The drain-source voltage is large, the power consumption is larger than in the linear region, and the heat generation of the power MOS transistor is large.

Therefore, a control is considered in which the noise is a certain value or less and the noise is minimized in a range where heat generation does not increase. At this time, the normal 1
In the case of a load in which a current flows as much as 0 times, the upper limit (di / dt) max of the slope of the current with respect to time is set, and the current slope is controlled during lighting to reduce noise. When the load resistance value of the lamp increases and the current value decreases, the control is performed so that the current slope time is constant. By using this control, the slope of the current with respect to time in the small current region can be reduced.
It can be further reduced and noise can be reduced as compared with Japanese Patent No. 8570. Further, since the current value is reduced, it is not necessary to consider the increase in heat generation.

In introducing the above control,
It is necessary to control the tilt time to be constant. As a simple method for detecting the tilt time, the circuit configuration shown in FIG. 12 can be considered. In FIG. 12, the current detection resistor 60
The voltage difference (corresponding to the current flowing through the resistor 60) between the two terminals is detected, amplified by the differential amplifier circuit 61, differentiated by the differentiating circuit 62, and the voltage detecting circuits 63, 64 compare the magnitude of the current change. The time when the current is inclined is detected.

However, the current detection resistor 60 of FIG.
Since the resistance value is as small as 0 mΩ, if a noise of about several tens of mV is applied to the input of the differentiating circuit 62, a large output voltage is generated in the differentiating circuit 62, which is apt to be erroneously detected.

[0009]

The present invention has been made under such a background, and an object thereof is a power MOS capable of suppressing noise and heat generation with a novel structure.
It is to provide a control device for a transistor.

[0010]

According to the invention described in claim 1, when a voltage is applied to the gate terminal of the power MOS transistor, a pulse shape of rising and falling with respect to the load is inclined. An electric current flows. Here, the gate-source voltage detecting means detects the gate-source voltage of the power MOS transistor due to the voltage application to the gate terminal of the power MOS transistor. Then, the feedback means obtains the deviation between the target value and the rise / fall time in the current waveform of the current flowing through the load from the gate-source voltage of the power MOS transistor by the gate-source voltage detection means. The power MOS transistor is feedback-controlled so as to eliminate the deviation.

In this way, even if the resistance value of the load changes as the load is driven, the rising and falling current gradients in the current waveform of the load are kept below a predetermined value and the rising and falling times are reduced. Can be reduced to a predetermined value or less, and noise and heat generation can be suppressed.

Further, as described in claim 2, the rise time and the fall time in the current waveform of the current of the load are obtained by measuring the duration of the saturation region in the transistor characteristics. As described in claim 3, the first comparison means compares the detected gate-source voltage with a first determination value between the off-time voltage and the threshold voltage, and a second comparison value. The means compares the detected gate-source voltage with a second determination value between the threshold voltage and the voltage at the time of turning on, and the timing means uses the comparison result obtained by the first and second comparing means. First judgment value and second
By measuring the duration between the determination value and the determination value as the duration of the saturation region in the transistor characteristics, the time when the current is inclined can be easily detected. Further, in the case of the circuit configuration of FIG. 12, if a noise of about several tens of mV is added to the input of the differentiating circuit 62, a large output voltage is generated in the differentiating circuit 62, which is apt to be erroneously detected. Since it does not use the or differentiating circuit, there is no false detection.

Further, as described in claim 4, the power MOS transistor may be feedback-controlled so that the rise time becomes constant and the fall time becomes constant.

Further, as described in claim 5, it is more preferable that the load is a lamp.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of a power MOS transistor control device according to the present embodiment.

In FIG. 1, power MO is supplied to power supply Vcc.
The S transistor 1 and the load 2 are connected in series. The load 2 is a lamp. A gate voltage control circuit 3 is connected to the gate terminal of the power MOS transistor 1.
A control logic 4 is connected to the gate voltage control circuit 3. A trapezoidal wave is output from the gate voltage control circuit 3 to the gate terminal of the power MOS transistor 1 according to a command from the control logic 4, and the power MOS transistor 1 is PWM-controlled by this signal so that a predetermined current i flows through the load 2. You can

FIG. 2 shows a specific configuration of the gate voltage control circuit 3. 2, the gate voltage control circuit 3 includes constant current circuits 31, 32, a switch 33, a capacitor 34, bipolar transistors 35, 36 and resistors 37, 38, 3.
9 is equipped. When the load is driven (when the lamp is on), the switch 33 is open, the transistor 36 is on, and the constant current circuit 31 charges the capacitor 34 to turn on the transistor 35.
From this state, when driving of the load is stopped (when the lamp is off), the switch 33 is closed and the capacitor 34 is discharged through the constant current circuit 32. At this time, the waveform falls obliquely. Then, the transistor 35 is turned off. On the other hand, when the load is driven from the discharged state of the capacitor 34, the switch 33 is opened and the constant current circuit 3
1, the capacitor 34 is charged. The waveform at this time rises obliquely. Then, the transistor 35 is turned on. In this way, a trapezoidal wave is generated.

Further, the power MOS transistor 1 of FIG.
A gate-source voltage detection circuit 5 as a gate-source voltage detection means is connected to the gate-source terminal of the power MOS transistor 1 by this circuit 5 when the voltage is applied to the gate terminal of the power MOS transistor 1. It is possible to detect the gate-source voltage Vgs. The gate-source voltage detection circuit 5 includes a differential amplifier 6
And resistors 7, 8, 9, and 10. Power M
A series circuit of resistors 7 and 8 is connected between the gate terminal of the OS transistor 1 and the ground, and the point a between the resistors is connected to the non-inverting input terminal of the differential amplifier 6. Also,
The inverting input terminal of the differential amplifier 6 has power M via the resistor 8.
It is connected to the source terminal of the OS transistor 1. The differential amplifier 6 is negatively fed back via the resistor 10. Then, in the differential amplifier 6, the difference between the gate voltage and the source voltage of the power MOS transistor 1 is amplified and output.

The output terminal of the differential amplifier 6 of the gate-source voltage detection circuit 5 is connected to the inverting input terminal of the comparator 12 of the voltage detection circuit 11 and the inverting input terminal of the comparator 14 of the voltage detection circuit 13. It is connected. The reference power supply 15 is connected to the non-inverting input terminal of the comparator 12, and the reference power supply 16 is connected to the non-inverting input terminal of the comparator 14. The voltage value at the reference power supply 15 corresponds to 1/2 (= Vt / 2) of the threshold voltage Vt as a comparison value for the gate-source voltage Vgs, and the voltage value at the reference power supply 16 corresponds to the gate-source voltage Vgs. It corresponds to 4 volts as a comparison value.

Further, the output terminals of the comparators 12 and 14 are connected to the control logic 4. Next, power M
The operation of the control device for the OS transistor will be described.

The operation will be described with reference to the time chart of FIG. FIG. 3 shows the conduction current i of the power MOS transistor, the gate-source voltage Vgs, and the outputs of the comparators 12 and 14 from the top.

The control logic 4 shown in FIG. 1 applies a voltage to the gate terminal of the power MOS transistor 1 through the gate voltage control circuit 3 so that the load 2 has a rising and falling slope as shown in FIG. A pulse-shaped current i is applied. That is, in the period from t1 to t2, the rising is inclined and t
In the period from 3 to t4, the trailing edge becomes oblique. At this time, in FIG. 3, regarding the gate-source voltage Vgs in the power MOS transistor 1, the gate-source voltage Vgs is 0 volt when the power MOS transistor 1 shown in the period up to t1 in FIG. 3 is off. .
Further, when the current shown in the periods of t1 to t2 and t3 to t4 in FIG.
gs is near the threshold voltage Vt of the power MOS transistor 1. During the period in which the current is inclined, the operating region of the power MOS transistor 1 becomes the saturation region, the gate-source voltage is small, and the drain-source voltage is large.
Further, when it is turned on during the period from t2 to t3 in FIG. 3, the gate-source voltage Vgs is as large as 5 to 10 volts. Power MOS for a period when this current is constant
Using the linear region (non-saturation region) of transistor 1,
The gate-source voltage is large, and the drain-source voltage is small.

The differential amplifier 6 of FIG. 1 amplifies the gate-source voltage Vgs. Then, the voltage detection circuit 11 (comparator 12) and the voltage detection circuit 13 (comparator 1
4), the gate-source voltage Vgs is set to the threshold voltage V
Compare with 1/2 of t (= Vt / 2), and 4 volts. The voltage detection circuit 11 (comparator 12) and the voltage detection circuit 13 (comparator 14) compare the Vgs value with the boundary determination value (Vt / 2 or 4 volts) to determine the saturation region of the MOS transistor in FIG. It is possible to detect which one of the operating regions, the unsaturated region and the non-saturated region, is in. As a result, the time (Tup, Tdown in FIG. 3) in which the current is inclined is detected in the control logic 4.

Specifically, the power MOS transistor 1
The rise time (Tup in FIG. 3) for controlling the slope of the current when turning on the power supply is such that the Vgs value in the voltage detection circuit 11 is ½ of the threshold voltage Vt of the power MOS transistor 1 (=
The voltage is detected as the time from when Vt / 2) is exceeded to when it exceeds 4 volts (the intermediate value of the gate-source voltage at which the power MOS transistor 1 can be sufficiently turned on) in the voltage detection circuit 13. Further, the fall time (Tdown in FIG. 3) for controlling the slope of the current when turning off the power MOS transistor 1 is Vt in the voltage detection circuit 11 after the Vgs value in the voltage detection circuit 13 is less than 4 volts. It is detected as the time until it becomes / 2.

In this way, the rise and fall times Tup and Tdown in the current waveform of the load 2 at this time are obtained by measuring the duration of the saturation region in the transistor characteristics, and specifically, The voltage detecting circuit 11 as the first comparing means compares the detected gate-source voltage Vgs with the first determination value between the off-time voltage and the threshold voltage, and as the second comparing means. Voltage detection circuit 1
3, the detected gate-source voltage Vgs is compared with a second judgment value between the threshold voltage and the voltage at the time of turning on, and the voltage detection circuits 11, 13 are further controlled by the control logic 4 as a time measuring means. The duration between the first determination value and the second determination value is measured as the duration of the saturation region in the transistor characteristics based on the comparison result of 1. In this way, it is possible to easily detect the time when the current is inclined.

Further, FIG. 1 as a feedback means.
The control logic 4 determines the deviation between the target values and the rising and falling times Tup and Tdown in the current waveform of the load 2 this time, and feedback-controls the power MOS transistor 1 so as to eliminate the deviation.

An example of a specific circuit configuration for that purpose is shown in FIG.
Shown in. FIG. 6 is a time chart for explaining the operation. In FIG. 5, the output signal A from the voltage detection circuit 11 is input to the NAND gate 42 via the inverter 41, and the output signal B from the voltage detection circuit 13 is N.
Input to the AND gate 42. The output signal of the NAND gate 42 is directly input to the NAND latch circuit 43 and is also input to the NAND latch circuit 43 via the 200 μs generation circuit 44. Further, the NAND latch circuit 43
Output signal of the AND gate 48 via the inverter 46.
Is input to the exclusive OR circuit 45 and A
It is input to the ND gate 47. Further, the output signal of the NAND gate 42 is input to the exclusive OR circuit 45. The output signal of the exclusive OR circuit 45 is the AND gate 4
7 and 48, and the output signals of the AND gates 47 and 48 become α signal and β signal.

With this circuit configuration, as shown in FIG. 6, the output (voltage at the point C) of the NAND gate 42 becomes L level from the fall of the signal A to the fall of the signal B. In synchronization with the fall of the output of the NAND gate 42 (fall of the signal A), a pulse of 200 μs which is the reference time is generated in the 200 μs generating circuit 44 (see the voltage at point D), and the same signal is sent to the NAND latch circuit 43. Sent. When the time T from the fall of the signal A to the fall of the signal B is longer than 200 μs, the L level α signal is output, and when the time T is shorter than 200 μs, the L level β is output. The signal is output.

The duration of the L level in the α and β signals reflects the deviation between the rising and falling times Tup and Tdown in the current waveform of the load 2 at this time and the target value. The currents in the constant current circuits 31 and 32 of the gate voltage control circuit 3 in FIG.
Rise time Tup and fall time Tdown in the current waveform of
Power MO so that the reference time is 200 μs
The S-transistor 1 is feedback-controlled. More specifically, the currents in the constant current circuits 31 and 32 are increased or decreased, that is, the charging / discharging speed of the capacitor 34 in FIG. In other words,
When the fall times Tup and Tdown are shorter than the reference time of 200 μs, the gate voltage control circuit 3 outputs an output that reduces the slope of the current. On the contrary, when the rising / falling times Tup and Tdown are longer than the reference time of 200 μs, the gate voltage control circuit 3 outputs an output that increases the slope of the current.

Specifically, when a lamp is used as the load 2, driving is started at t10 as shown in FIG. The lamp resistance is small during the period up to t11. In this period, the current change di / dt per time is increased as shown in FIG. Further, after t12 in FIG. 7, the lamp resistance is large. During this period, as shown in FIG. 8C, the current change d per hour
Make i / dt very small. Furthermore, t11 to t11 in FIG.
In the transition period of t12, as shown in FIG.
Set i / dt to an intermediate value.

As a result, it is the same in the period when the lamp resistance shown in FIG. 8A is small, the period where the lamp resistance shown in FIG. 8B is an intermediate value, and the period where the lamp resistance shown in FIG. 8C is large. The current startup / shutdown control is performed only for the time. At this time, as shown in FIG. 8 (a), by setting di / dt to a predetermined value or less during the period when the lamp resistance is small,
Noise can be kept below a certain level, and heat generation can be kept below a certain level. Further, as shown in FIG. 8C, noise can be extremely reduced by reducing di / dt during a period when the lamp resistance is high. Further, since the current value is small, it is not necessary to consider heat generation. Further, as shown in FIG. 8B, di / dt is applied during the period when the lamp resistance has an intermediate value.
The noise can be reduced by setting the value to a middle value.

By the control as described above, it is possible to perform control such that the current inclining time (rise / fall time) Tup, Tdown is kept constant. That is, the power MOS transistor is feedback-controlled so that the rise time becomes constant and the fall time becomes constant.

Further, since the differentiating circuit 62 in FIG. 12 is not adopted, the power MOS transistor 1 has several tens of mV.
Even if a certain amount of noise is applied, the signal is not amplified and there is no fear of malfunction. That is, in the case of the circuit configuration of FIG. 12, if a noise of about several tens of mV is added to the input of the differentiating circuit 62, a large output voltage is generated in the differentiating circuit 62 and is easily erroneously detected. Since no resistors or differentiating circuits are used, there is no false detection.

As described above, when the rising and falling of the pulse-shaped current as the current waveform of the load is made to rise and fall (when the current is inclined), the saturation region of the power MOS transistor is used. At the same time, paying attention to the fact that the linear region (non-saturation region) of the power MOS transistor is used to make the current constant in the pulse-shaped current. From the gate-source voltage Vgs of the power MOS transistor to the conduction current of the load 2. The portion of the waveform where the rising and falling are inclined is determined as the duration of the operating region (saturation region in the transistor characteristics) of the power MOS transistor 1. This method is more accurate and easier than the case where the rising time and the falling time in the current waveform are obtained from the time change of the current flowing through the load 2 (the case of FIG. 12). The noise can be reduced to a certain value or less by controlling the gradient when a pulse-shaped current having rising and falling slopes is applied to the load 2 and the current waveform of the load 2 It is possible to suppress the heat generation due to the energization of the load by controlling the rising time and the falling time. Therefore, even if the resistance value of the load 2 changes due to the driving of the load 2, the rising and falling current slopes in the current waveform of the load 2 are set to a predetermined value or less, and the rising and falling times are set to a predetermined value. The following can be achieved, and noise and heat generation can be suppressed.

Further, the rise and fall times Tup and Tdown can be set to desired values even when the power supply voltage (Vcc) changes. Since the threshold voltage of the power MOS transistor varies depending on the temperature, the temperature of the power element may be detected and the rising / falling time may be measured using the threshold voltage at that temperature. That is, temperature compensation of the Vt value may be performed.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of a power MOS transistor control device according to an embodiment.

FIG. 2 is a configuration diagram of a gate voltage control circuit.

FIG. 3 is a time chart for explaining the operation.

FIG. 4 is a graph showing transistor characteristics.

FIG. 5 is a circuit configuration diagram showing an example of a time measuring circuit in a control logic.

FIG. 6 is a time chart for explaining the operation.

FIG. 7 is a time chart for explaining the operation.

FIG. 8 is a time chart for explaining the operation.

FIG. 9 is a configuration diagram of a power MOS transistor control device for explaining a conventional technique.

FIG. 10 is a diagram showing a current waveform.

FIG. 11 is a diagram for explaining a difference in inclination time due to a difference in load current.

FIG. 12 is a configuration diagram of a power MOS transistor control device for explaining a conventional technique.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Power MOS transistor, 2 ... Load, 3 ... Gate voltage control circuit, 4 ... Control logic, 5 ... Gate-source voltage detection circuit, 6 ... Differential amplifier, 7,8,9,10 ...
Resistance, 11 ... Voltage detection circuit, 12 ... Comparator, 13
... voltage detection circuit, 14 ... comparator, 15 ... reference power supply, 16 ... reference power supply, Vcc ... power supply.

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5H420 BB02 BB13 CC02 DD02 EA12                       EA39 EB04 FF04 FF15 FF23                 5J055 AX12 AX25 AX55 AX56 AX64                       BX16 CX07 CX22 DX13 DX22                       DX53 DX54 EX01 EX02 EX17                       EY01 EY10 EY17 EZ03 EZ07                       EZ10 EZ25 EZ26 EZ31 FX05                       FX38 GX01 GX02 GX04

Claims (5)

[Claims] 1. A power MOS transistor (1) and a load (2) are connected in series to a power source (Vcc), and a power M
A controller for a power MOS transistor, wherein a voltage is applied to a gate terminal of an OS transistor (1) so that a pulse-shaped current having a rising and falling slope is applied to a load (2). Gate-source voltage detection means (5) for detecting a gate-source voltage (Vgs) of the power MOS transistor (1) accompanying application of a voltage to the gate terminal of the power MOS transistor (1), and the gate-source The gate-source voltage (V of the power MOS transistor (1) by the voltage detecting means (5)
gs), the deviation between the target value and the rising and falling times (Tup, Tdown) in the current waveform of the load (2) this time is found, and the power MOS transistor (1) is feedback-controlled so as to eliminate the deviation. And a feedback means (4) for controlling the power MOS transistor. 2. The rise and fall times (Tup, Tdown) in the current waveform of the load (2) at this time are obtained by measuring the duration of the saturation region in the transistor characteristics. The control device for a power MOS transistor according to claim 1, wherein the control device is a power MOS transistor. 3. The detected gate-source voltage (Vgs)
Is compared with a first judgment value between the off-time voltage and the threshold voltage, and the detected gate-source voltage (Vgs) is compared with the threshold voltage and the on-voltage. Second comparison means (13) for comparing the second judgment value between the first judgment value and the second judgment value based on the comparison result by the first and second comparison means (11, 13). 3. The control of the power MOS transistor according to claim 2, further comprising: a clocking unit (4) for measuring a duration between the determination value and the determination value as the duration of a saturation region in the transistor characteristic. apparatus. 4. The power MOS transistor (1) is feedback-controlled so that the rise time is constant and the fall time is constant. Power MO described in
S-transistor controller. 5. The power M according to claim 1, wherein the load (2) is a lamp.
Control device for OS transistor.